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https://github.com/openjdk/jdk.git
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8154156: PPC64: improve array copy stubs by using vector instructions
Reviewed-by: goetz, mdoerr
This commit is contained in:
Gustavo Romero
Martin Doerr
parent
05540f90da
commit
066208e368
@ -503,6 +503,10 @@ class Assembler : public AbstractAssembler {
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LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
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LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
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// Vector-Scalar (VSX) instruction support.
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LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
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STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
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// Vector Permute and Formatting
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VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
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VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
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@ -1085,6 +1089,19 @@ class Assembler : public AbstractAssembler {
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static int vrs( VectorRegister r) { return vrs(r->encoding());}
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static int vrt( VectorRegister r) { return vrt(r->encoding());}
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// Support Vector-Scalar (VSX) instructions.
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static int vsra( int x) { return opp_u_field(x, 15, 11); }
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static int vsrb( int x) { return opp_u_field(x, 20, 16); }
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static int vsrc( int x) { return opp_u_field(x, 25, 21); }
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static int vsrs( int x) { return opp_u_field(x, 10, 6); }
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static int vsrt( int x) { return opp_u_field(x, 10, 6); }
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static int vsra( VectorSRegister r) { return vsra(r->encoding());}
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static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
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static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
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static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
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static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
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static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions
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static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions
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static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction
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@ -2065,6 +2082,10 @@ class Assembler : public AbstractAssembler {
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inline void mtvscr( VectorRegister b);
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inline void mfvscr( VectorRegister d);
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// Vector-Scalar (VSX) instructions.
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inline void lxvd2x( VectorSRegister d, Register a, Register b);
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inline void stxvd2x( VectorSRegister d, Register a, Register b);
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// AES (introduced with Power 8)
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inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
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@ -721,6 +721,10 @@ inline void Assembler::stvxl( VectorRegister d, Register s1, Register s2) { emit
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inline void Assembler::lvsl( VectorRegister d, Register s1, Register s2) { emit_int32( LVSL_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
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inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
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// Vector-Scalar (VSX) instructions.
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inline void Assembler::lxvd2x (VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(s1) | rb(s2)); }
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inline void Assembler::stxvd2x(VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra(s1) | rb(s2)); }
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inline void Assembler::vpkpx( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKPX_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vpkshss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSHSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vpkswss( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPKSWSS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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@ -75,3 +75,14 @@ const char* VectorRegisterImpl::name() const {
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};
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return is_valid() ? names[encoding()] : "vnoreg";
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}
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const char* VectorSRegisterImpl::name() const {
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const char* names[number_of_registers] = {
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"VSR0", "VSR1", "VSR2", "VSR3", "VSR4", "VSR5", "VSR6", "VSR7",
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"VSR8", "VSR9", "VSR10", "VSR11", "VSR12", "VSR13", "VSR14", "VSR15",
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"VSR16", "VSR17", "VSR18", "VSR19", "VSR20", "VSR21", "VSR22", "VSR23",
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"VSR24", "VSR25", "VSR26", "VSR27", "VSR28", "VSR29", "VSR30", "VSR31"
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};
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return is_valid() ? names[encoding()] : "vsnoreg";
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}
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@ -491,6 +491,106 @@ CONSTANT_REGISTER_DECLARATION(VectorRegister, VR31, (31));
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#endif // DONT_USE_REGISTER_DEFINES
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// Use VectorSRegister as a shortcut.
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class VectorSRegisterImpl;
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typedef VectorSRegisterImpl* VectorSRegister;
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inline VectorSRegister as_VectorSRegister(int encoding) {
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return (VectorSRegister)(intptr_t)encoding;
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}
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// The implementation of Vector-Scalar (VSX) registers on POWER architecture.
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class VectorSRegisterImpl: public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = 32
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};
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// construction
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inline friend VectorSRegister as_VectorSRegister(int encoding);
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// accessors
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int encoding() const { assert(is_valid(), "invalid register"); return value(); }
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// testers
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bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
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const char* name() const;
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};
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// The Vector-Scalar (VSX) registers of the POWER architecture.
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, vsnoreg, (-1));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR0, ( 0));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR1, ( 1));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR2, ( 2));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR3, ( 3));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR4, ( 4));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR5, ( 5));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR6, ( 6));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR7, ( 7));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR8, ( 8));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR9, ( 9));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR10, (10));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR11, (11));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR12, (12));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR13, (13));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR14, (14));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR15, (15));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR16, (16));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR17, (17));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR18, (18));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR19, (19));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR20, (20));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR21, (21));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR22, (22));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR23, (23));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR24, (24));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR25, (25));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR26, (26));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR27, (27));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR28, (28));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR29, (29));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR30, (30));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR31, (31));
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#ifndef DONT_USE_REGISTER_DEFINES
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#define vsnoregi ((VectorSRegister)(vsnoreg_VectorSRegisterEnumValue))
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#define VSR0 ((VectorSRegister)( VSR0_VectorSRegisterEnumValue))
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#define VSR1 ((VectorSRegister)( VSR1_VectorSRegisterEnumValue))
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#define VSR2 ((VectorSRegister)( VSR2_VectorSRegisterEnumValue))
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#define VSR3 ((VectorSRegister)( VSR3_VectorSRegisterEnumValue))
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#define VSR4 ((VectorSRegister)( VSR4_VectorSRegisterEnumValue))
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#define VSR5 ((VectorSRegister)( VSR5_VectorSRegisterEnumValue))
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#define VSR6 ((VectorSRegister)( VSR6_VectorSRegisterEnumValue))
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#define VSR7 ((VectorSRegister)( VSR7_VectorSRegisterEnumValue))
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#define VSR8 ((VectorSRegister)( VSR8_VectorSRegisterEnumValue))
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#define VSR9 ((VectorSRegister)( VSR9_VectorSRegisterEnumValue))
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#define VSR10 ((VectorSRegister)( VSR10_VectorSRegisterEnumValue))
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#define VSR11 ((VectorSRegister)( VSR11_VectorSRegisterEnumValue))
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#define VSR12 ((VectorSRegister)( VSR12_VectorSRegisterEnumValue))
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#define VSR13 ((VectorSRegister)( VSR13_VectorSRegisterEnumValue))
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#define VSR14 ((VectorSRegister)( VSR14_VectorSRegisterEnumValue))
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#define VSR15 ((VectorSRegister)( VSR15_VectorSRegisterEnumValue))
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#define VSR16 ((VectorSRegister)( VSR16_VectorSRegisterEnumValue))
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#define VSR17 ((VectorSRegister)( VSR17_VectorSRegisterEnumValue))
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#define VSR18 ((VectorSRegister)( VSR18_VectorSRegisterEnumValue))
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#define VSR19 ((VectorSRegister)( VSR19_VectorSRegisterEnumValue))
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#define VSR20 ((VectorSRegister)( VSR20_VectorSRegisterEnumValue))
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#define VSR21 ((VectorSRegister)( VSR21_VectorSRegisterEnumValue))
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#define VSR22 ((VectorSRegister)( VSR22_VectorSRegisterEnumValue))
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#define VSR23 ((VectorSRegister)( VSR23_VectorSRegisterEnumValue))
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#define VSR24 ((VectorSRegister)( VSR24_VectorSRegisterEnumValue))
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#define VSR25 ((VectorSRegister)( VSR25_VectorSRegisterEnumValue))
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#define VSR26 ((VectorSRegister)( VSR26_VectorSRegisterEnumValue))
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#define VSR27 ((VectorSRegister)( VSR27_VectorSRegisterEnumValue))
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#define VSR28 ((VectorSRegister)( VSR28_VectorSRegisterEnumValue))
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#define VSR29 ((VectorSRegister)( VSR29_VectorSRegisterEnumValue))
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#define VSR30 ((VectorSRegister)( VSR30_VectorSRegisterEnumValue))
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#define VSR31 ((VectorSRegister)( VSR31_VectorSRegisterEnumValue))
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#endif // DONT_USE_REGISTER_DEFINES
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// Maximum number of incoming arguments that can be passed in i registers.
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const int PPC_ARGS_IN_REGS_NUM = 8;
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@ -1341,10 +1341,13 @@ class StubGenerator: public StubCodeGenerator {
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Register tmp3 = R8_ARG6;
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Register tmp4 = R9_ARG7;
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VectorSRegister tmp_vsr1 = VSR1;
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VectorSRegister tmp_vsr2 = VSR2;
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address start = __ function_entry();
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assert_positive_int(R5_ARG3);
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Label l_1, l_2, l_3, l_4, l_5, l_6, l_7, l_8;
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Label l_1, l_2, l_3, l_4, l_5, l_6, l_7, l_8, l_9;
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// don't try anything fancy if arrays don't have many elements
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__ li(tmp3, 0);
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@ -1403,22 +1406,60 @@ class StubGenerator: public StubCodeGenerator {
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__ andi_(R5_ARG3, R5_ARG3, 15);
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__ mtctr(tmp1);
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__ bind(l_8);
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// Use unrolled version for mass copying (copy 16 elements a time).
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// Load feeding store gets zero latency on Power6, however not on Power5.
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// Therefore, the following sequence is made for the good of both.
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__ ld(tmp1, 0, R3_ARG1);
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__ ld(tmp2, 8, R3_ARG1);
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__ ld(tmp3, 16, R3_ARG1);
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__ ld(tmp4, 24, R3_ARG1);
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__ std(tmp1, 0, R4_ARG2);
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__ std(tmp2, 8, R4_ARG2);
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__ std(tmp3, 16, R4_ARG2);
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__ std(tmp4, 24, R4_ARG2);
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__ addi(R3_ARG1, R3_ARG1, 32);
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__ addi(R4_ARG2, R4_ARG2, 32);
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__ bdnz(l_8);
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}
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if (!VM_Version::has_vsx()) {
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__ bind(l_8);
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// Use unrolled version for mass copying (copy 16 elements a time).
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// Load feeding store gets zero latency on Power6, however not on Power5.
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// Therefore, the following sequence is made for the good of both.
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__ ld(tmp1, 0, R3_ARG1);
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__ ld(tmp2, 8, R3_ARG1);
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__ ld(tmp3, 16, R3_ARG1);
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__ ld(tmp4, 24, R3_ARG1);
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__ std(tmp1, 0, R4_ARG2);
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__ std(tmp2, 8, R4_ARG2);
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__ std(tmp3, 16, R4_ARG2);
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__ std(tmp4, 24, R4_ARG2);
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__ addi(R3_ARG1, R3_ARG1, 32);
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__ addi(R4_ARG2, R4_ARG2, 32);
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__ bdnz(l_8);
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} else { // Processor supports VSX, so use it to mass copy.
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// Prefetch src data into L2 cache.
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__ dcbt(R3_ARG1, 0);
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// If supported set DSCR pre-fetch to deepest.
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if (VM_Version::has_mfdscr()) {
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__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
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__ mtdscr(tmp2);
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}
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__ li(tmp1, 16);
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// Backbranch target aligned to 32-byte. It's not aligned 16-byte
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// as loop contains < 8 instructions that fit inside a single
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// i-cache sector.
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__ align(32);
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__ bind(l_9);
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// Use loop with VSX load/store instructions to
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// copy 16 elements a time.
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__ lxvd2x(tmp_vsr1, 0, R3_ARG1); // Load from src.
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__ stxvd2x(tmp_vsr1, 0, R4_ARG2); // Store to dst.
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__ lxvd2x(tmp_vsr2, R3_ARG1, tmp1); // Load from src + 16.
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__ stxvd2x(tmp_vsr2, R4_ARG2, tmp1); // Store to dst + 16.
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__ addi(R3_ARG1, R3_ARG1, 32); // Update src+=32.
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__ addi(R4_ARG2, R4_ARG2, 32); // Update dsc+=32.
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__ bdnz(l_9); // Dec CTR and loop if not zero.
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// Restore DSCR pre-fetch value.
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if (VM_Version::has_mfdscr()) {
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__ load_const_optimized(tmp2, VM_Version::_dscr_val);
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__ mtdscr(tmp2);
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}
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}
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} // FasterArrayCopy
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__ bind(l_6);
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// copy 2 elements at a time
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@ -38,7 +38,7 @@
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# include <sys/sysinfo.h>
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bool VM_Version::_is_determine_features_test_running = false;
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uint64_t VM_Version::_dscr_val = 0;
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#define MSG(flag) \
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if (flag && !FLAG_IS_DEFAULT(flag)) \
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@ -111,7 +111,7 @@ void VM_Version::initialize() {
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// Create and print feature-string.
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char buf[(num_features+1) * 16]; // Max 16 chars per feature.
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jio_snprintf(buf, sizeof(buf),
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"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s",
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"ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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(has_fsqrt() ? " fsqrt" : ""),
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(has_isel() ? " isel" : ""),
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(has_lxarxeh() ? " lxarxeh" : ""),
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@ -125,7 +125,8 @@ void VM_Version::initialize() {
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(has_vcipher() ? " aes" : ""),
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(has_vpmsumb() ? " vpmsumb" : ""),
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(has_tcheck() ? " tcheck" : ""),
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(has_mfdscr() ? " mfdscr" : "")
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(has_mfdscr() ? " mfdscr" : ""),
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(has_vsx() ? " vsx" : "")
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// Make sure number of %s matches num_features!
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);
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_features_string = os::strdup(buf);
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@ -643,6 +644,7 @@ void VM_Version::determine_features() {
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a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
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a->tcheck(0); // code[12] -> tcheck
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a->mfdscr(R0); // code[13] -> mfdscr
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a->lxvd2x(VSR0, 0, R3_ARG1); // code[14] -> vsx
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a->blr();
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// Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
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@ -691,6 +693,7 @@ void VM_Version::determine_features() {
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if (code[feature_cntr++]) features |= vpmsumb_m;
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if (code[feature_cntr++]) features |= tcheck_m;
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if (code[feature_cntr++]) features |= mfdscr_m;
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if (code[feature_cntr++]) features |= vsx_m;
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// Print the detection code.
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if (PrintAssembly) {
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@ -733,31 +736,31 @@ void VM_Version::config_dscr() {
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}
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// Apply the configuration if needed.
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uint64_t dscr_val = (*get_dscr)();
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_dscr_val = (*get_dscr)();
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if (Verbose) {
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tty->print_cr("dscr value was 0x%lx" , dscr_val);
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tty->print_cr("dscr value was 0x%lx" , _dscr_val);
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}
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bool change_requested = false;
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if (DSCR_PPC64 != (uintx)-1) {
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dscr_val = DSCR_PPC64;
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_dscr_val = DSCR_PPC64;
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change_requested = true;
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}
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if (DSCR_DPFD_PPC64 <= 7) {
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uint64_t mask = 0x7;
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if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
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dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
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if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
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_dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
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change_requested = true;
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}
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}
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if (DSCR_URG_PPC64 <= 7) {
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uint64_t mask = 0x7 << 6;
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if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
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dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
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||||
if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
|
||||
_dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
|
||||
change_requested = true;
|
||||
}
|
||||
}
|
||||
if (change_requested) {
|
||||
(*set_dscr)(dscr_val);
|
||||
(*set_dscr)(_dscr_val);
|
||||
if (Verbose) {
|
||||
tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
|
||||
}
|
||||
|
||||
@ -46,6 +46,7 @@ protected:
|
||||
vpmsumb,
|
||||
tcheck,
|
||||
mfdscr,
|
||||
vsx,
|
||||
num_features // last entry to count features
|
||||
};
|
||||
enum Feature_Flag_Set {
|
||||
@ -64,6 +65,7 @@ protected:
|
||||
vpmsumb_m = (1 << vpmsumb),
|
||||
tcheck_m = (1 << tcheck ),
|
||||
mfdscr_m = (1 << mfdscr ),
|
||||
vsx_m = (1 << vsx ),
|
||||
all_features_m = (unsigned long)-1
|
||||
};
|
||||
|
||||
@ -97,10 +99,14 @@ public:
|
||||
static bool has_vpmsumb() { return (_features & vpmsumb_m) != 0; }
|
||||
static bool has_tcheck() { return (_features & tcheck_m) != 0; }
|
||||
static bool has_mfdscr() { return (_features & mfdscr_m) != 0; }
|
||||
static bool has_vsx() { return (_features & vsx_m) != 0; }
|
||||
|
||||
// Assembler testing
|
||||
static void allow_all();
|
||||
static void revert();
|
||||
|
||||
// POWER 8: DSCR current value.
|
||||
static uint64_t _dscr_val;
|
||||
};
|
||||
|
||||
#endif // CPU_PPC_VM_VM_VERSION_PPC_HPP
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user