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8251216: Implement MD5 intrinsics on AArch64
Co-authored-by: Ludovic Henry <luhenry@openjdk.org> Reviewed-by: aph, neliasso
This commit is contained in:
Patric Hedlin
parent
a093cdddaf
commit
088b244ec6
@ -3210,6 +3210,194 @@ class StubGenerator: public StubCodeGenerator {
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return start;
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}
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// Arguments:
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//
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// Inputs:
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// c_rarg0 - byte[] source+offset
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// c_rarg1 - int[] SHA.state
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// c_rarg2 - int offset
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// c_rarg3 - int limit
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//
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address generate_md5_implCompress(bool multi_block, const char *name) {
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__ align(CodeEntryAlignment);
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StubCodeMark mark(this, "StubRoutines", name);
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address start = __ pc();
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Register buf = c_rarg0;
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Register state = c_rarg1;
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Register ofs = c_rarg2;
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Register limit = c_rarg3;
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Register a = r4;
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Register b = r5;
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Register c = r6;
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Register d = r7;
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Register rscratch3 = r10;
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Register rscratch4 = r11;
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Label keys;
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Label md5_loop;
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__ BIND(md5_loop);
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// Save hash values for addition after rounds
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__ ldrw(a, Address(state, 0));
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__ ldrw(b, Address(state, 4));
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__ ldrw(c, Address(state, 8));
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__ ldrw(d, Address(state, 12));
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#define FF(r1, r2, r3, r4, k, s, t) \
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__ eorw(rscratch3, r3, r4); \
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__ movw(rscratch2, t); \
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__ andw(rscratch3, rscratch3, r2); \
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__ addw(rscratch4, r1, rscratch2); \
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__ ldrw(rscratch1, Address(buf, k*4)); \
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__ eorw(rscratch3, rscratch3, r4); \
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__ addw(rscratch3, rscratch3, rscratch1); \
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__ addw(rscratch3, rscratch3, rscratch4); \
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__ rorw(rscratch2, rscratch3, 32 - s); \
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__ addw(r1, rscratch2, r2);
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#define GG(r1, r2, r3, r4, k, s, t) \
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__ eorw(rscratch2, r2, r3); \
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__ ldrw(rscratch1, Address(buf, k*4)); \
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__ andw(rscratch3, rscratch2, r4); \
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__ movw(rscratch2, t); \
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__ eorw(rscratch3, rscratch3, r3); \
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__ addw(rscratch4, r1, rscratch2); \
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__ addw(rscratch3, rscratch3, rscratch1); \
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__ addw(rscratch3, rscratch3, rscratch4); \
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__ rorw(rscratch2, rscratch3, 32 - s); \
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__ addw(r1, rscratch2, r2);
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#define HH(r1, r2, r3, r4, k, s, t) \
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__ eorw(rscratch3, r3, r4); \
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__ movw(rscratch2, t); \
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__ addw(rscratch4, r1, rscratch2); \
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__ ldrw(rscratch1, Address(buf, k*4)); \
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__ eorw(rscratch3, rscratch3, r2); \
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__ addw(rscratch3, rscratch3, rscratch1); \
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__ addw(rscratch3, rscratch3, rscratch4); \
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__ rorw(rscratch2, rscratch3, 32 - s); \
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__ addw(r1, rscratch2, r2);
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#define II(r1, r2, r3, r4, k, s, t) \
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__ movw(rscratch3, t); \
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__ ornw(rscratch2, r2, r4); \
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__ addw(rscratch4, r1, rscratch3); \
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__ ldrw(rscratch1, Address(buf, k*4)); \
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__ eorw(rscratch3, rscratch2, r3); \
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__ addw(rscratch3, rscratch3, rscratch1); \
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__ addw(rscratch3, rscratch3, rscratch4); \
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__ rorw(rscratch2, rscratch3, 32 - s); \
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__ addw(r1, rscratch2, r2);
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// Round 1
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FF(a, b, c, d, 0, 7, 0xd76aa478)
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FF(d, a, b, c, 1, 12, 0xe8c7b756)
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FF(c, d, a, b, 2, 17, 0x242070db)
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FF(b, c, d, a, 3, 22, 0xc1bdceee)
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FF(a, b, c, d, 4, 7, 0xf57c0faf)
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FF(d, a, b, c, 5, 12, 0x4787c62a)
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FF(c, d, a, b, 6, 17, 0xa8304613)
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FF(b, c, d, a, 7, 22, 0xfd469501)
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FF(a, b, c, d, 8, 7, 0x698098d8)
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FF(d, a, b, c, 9, 12, 0x8b44f7af)
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FF(c, d, a, b, 10, 17, 0xffff5bb1)
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FF(b, c, d, a, 11, 22, 0x895cd7be)
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FF(a, b, c, d, 12, 7, 0x6b901122)
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FF(d, a, b, c, 13, 12, 0xfd987193)
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FF(c, d, a, b, 14, 17, 0xa679438e)
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FF(b, c, d, a, 15, 22, 0x49b40821)
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// Round 2
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GG(a, b, c, d, 1, 5, 0xf61e2562)
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GG(d, a, b, c, 6, 9, 0xc040b340)
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GG(c, d, a, b, 11, 14, 0x265e5a51)
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GG(b, c, d, a, 0, 20, 0xe9b6c7aa)
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GG(a, b, c, d, 5, 5, 0xd62f105d)
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GG(d, a, b, c, 10, 9, 0x02441453)
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GG(c, d, a, b, 15, 14, 0xd8a1e681)
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GG(b, c, d, a, 4, 20, 0xe7d3fbc8)
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GG(a, b, c, d, 9, 5, 0x21e1cde6)
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GG(d, a, b, c, 14, 9, 0xc33707d6)
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GG(c, d, a, b, 3, 14, 0xf4d50d87)
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GG(b, c, d, a, 8, 20, 0x455a14ed)
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GG(a, b, c, d, 13, 5, 0xa9e3e905)
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GG(d, a, b, c, 2, 9, 0xfcefa3f8)
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GG(c, d, a, b, 7, 14, 0x676f02d9)
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GG(b, c, d, a, 12, 20, 0x8d2a4c8a)
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// Round 3
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HH(a, b, c, d, 5, 4, 0xfffa3942)
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HH(d, a, b, c, 8, 11, 0x8771f681)
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HH(c, d, a, b, 11, 16, 0x6d9d6122)
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HH(b, c, d, a, 14, 23, 0xfde5380c)
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HH(a, b, c, d, 1, 4, 0xa4beea44)
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HH(d, a, b, c, 4, 11, 0x4bdecfa9)
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HH(c, d, a, b, 7, 16, 0xf6bb4b60)
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HH(b, c, d, a, 10, 23, 0xbebfbc70)
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HH(a, b, c, d, 13, 4, 0x289b7ec6)
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HH(d, a, b, c, 0, 11, 0xeaa127fa)
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HH(c, d, a, b, 3, 16, 0xd4ef3085)
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HH(b, c, d, a, 6, 23, 0x04881d05)
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HH(a, b, c, d, 9, 4, 0xd9d4d039)
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HH(d, a, b, c, 12, 11, 0xe6db99e5)
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HH(c, d, a, b, 15, 16, 0x1fa27cf8)
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HH(b, c, d, a, 2, 23, 0xc4ac5665)
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// Round 4
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II(a, b, c, d, 0, 6, 0xf4292244)
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II(d, a, b, c, 7, 10, 0x432aff97)
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II(c, d, a, b, 14, 15, 0xab9423a7)
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II(b, c, d, a, 5, 21, 0xfc93a039)
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II(a, b, c, d, 12, 6, 0x655b59c3)
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II(d, a, b, c, 3, 10, 0x8f0ccc92)
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II(c, d, a, b, 10, 15, 0xffeff47d)
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II(b, c, d, a, 1, 21, 0x85845dd1)
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II(a, b, c, d, 8, 6, 0x6fa87e4f)
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II(d, a, b, c, 15, 10, 0xfe2ce6e0)
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II(c, d, a, b, 6, 15, 0xa3014314)
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II(b, c, d, a, 13, 21, 0x4e0811a1)
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II(a, b, c, d, 4, 6, 0xf7537e82)
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II(d, a, b, c, 11, 10, 0xbd3af235)
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II(c, d, a, b, 2, 15, 0x2ad7d2bb)
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II(b, c, d, a, 9, 21, 0xeb86d391)
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#undef FF
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#undef GG
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#undef HH
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#undef II
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// write hash values back in the correct order
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__ ldrw(rscratch1, Address(state, 0));
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__ addw(rscratch1, rscratch1, a);
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__ strw(rscratch1, Address(state, 0));
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__ ldrw(rscratch2, Address(state, 4));
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__ addw(rscratch2, rscratch2, b);
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__ strw(rscratch2, Address(state, 4));
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__ ldrw(rscratch3, Address(state, 8));
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__ addw(rscratch3, rscratch3, c);
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__ strw(rscratch3, Address(state, 8));
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__ ldrw(rscratch4, Address(state, 12));
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__ addw(rscratch4, rscratch4, d);
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__ strw(rscratch4, Address(state, 12));
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if (multi_block) {
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__ add(buf, buf, 64);
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__ add(ofs, ofs, 64);
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__ cmp(ofs, limit);
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__ br(Assembler::LE, md5_loop);
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__ mov(c_rarg0, ofs); // return ofs
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}
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__ ret(lr);
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return start;
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}
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// Arguments:
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//
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// Inputs:
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@ -7501,6 +7689,10 @@ class StubGenerator: public StubCodeGenerator {
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StubRoutines::_galoisCounterMode_AESCrypt = generate_galoisCounterMode_AESCrypt();
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}
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if (UseMD5Intrinsics) {
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StubRoutines::_md5_implCompress = generate_md5_implCompress(false, "md5_implCompress");
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StubRoutines::_md5_implCompressMB = generate_md5_implCompress(true, "md5_implCompressMB");
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}
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if (UseSHA1Intrinsics) {
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StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress");
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StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB");
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@ -36,7 +36,7 @@ static bool returns_to_call_stub(address return_pc) {
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enum platform_dependent_constants {
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code_size1 = 19000, // simply increase if too small (assembler will crash if too small)
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code_size2 = 38000 // simply increase if too small (assembler will crash if too small)
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code_size2 = 45000 // simply increase if too small (assembler will crash if too small)
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};
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class aarch64 {
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@ -301,9 +301,8 @@ void VM_Version::initialize() {
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FLAG_SET_DEFAULT(UseFMA, true);
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}
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if (UseMD5Intrinsics) {
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warning("MD5 intrinsics are not available on this CPU");
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FLAG_SET_DEFAULT(UseMD5Intrinsics, false);
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if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
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UseMD5Intrinsics = true;
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}
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if (_features & (CPU_SHA1 | CPU_SHA2 | CPU_SHA3 | CPU_SHA512)) {
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@ -60,10 +60,11 @@ public class IntrinsicPredicates {
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};
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public static final BooleanSupplier MD5_INSTRUCTION_AVAILABLE
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= // x86 variants
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= new OrPredicate(new CPUSpecificPredicate("aarch64.*", null, null),
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// x86 variants
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new OrPredicate(new CPUSpecificPredicate("amd64.*", null, null),
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new OrPredicate(new CPUSpecificPredicate("i386.*", null, null),
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new CPUSpecificPredicate("x86.*", null, null)));
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new CPUSpecificPredicate("x86.*", null, null))));
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public static final BooleanSupplier SHA1_INSTRUCTION_AVAILABLE
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= new OrPredicate(new CPUSpecificPredicate("aarch64.*", new String[] { "sha1" }, null),
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