diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad
index 0687a025a6d..de4c2b408d4 100644
--- a/src/hotspot/cpu/riscv/riscv_v.ad
+++ b/src/hotspot/cpu/riscv/riscv_v.ad
@@ -151,16 +151,11 @@ source %{
   }
 %}
 
-definitions %{
-  int_def VEC_COST             (200, 200);
-%}
-
 // All VEC instructions
 
 // vector load/store
 instruct loadV(vReg dst, vmemA mem) %{
   match(Set dst (LoadVector mem));
-  ins_cost(VEC_COST);
   format %{ "loadV $dst, $mem\t# vector (rvv)" %}
   ins_encode %{
     VectorRegister dst_reg = as_VectorRegister($dst$$reg);
@@ -172,7 +167,6 @@ instruct loadV(vReg dst, vmemA mem) %{
 
 instruct storeV(vReg src, vmemA mem) %{
   match(Set mem (StoreVector mem src));
-  ins_cost(VEC_COST);
   format %{ "storeV $mem, $src\t# vector (rvv)" %}
   ins_encode %{
     VectorRegister src_reg = as_VectorRegister($src$$reg);
@@ -294,7 +288,6 @@ instruct vabs(vReg dst, vReg src, vReg tmp) %{
   match(Set dst (AbsVS src));
   match(Set dst (AbsVI src));
   match(Set dst (AbsVL src));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vabs $dst, $src\t# KILL $tmp" %}
   ins_encode %{
@@ -309,7 +302,6 @@ instruct vabs(vReg dst, vReg src, vReg tmp) %{
 instruct vabs_fp(vReg dst, vReg src) %{
   match(Set dst (AbsVF src));
   match(Set dst (AbsVD src));
-  ins_cost(VEC_COST);
   format %{ "vabs_fp $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -326,7 +318,6 @@ instruct vabs_masked(vReg dst_src, vRegMask_V0 v0, vReg tmp) %{
   match(Set dst_src (AbsVS dst_src v0));
   match(Set dst_src (AbsVI dst_src v0));
   match(Set dst_src (AbsVL dst_src v0));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vabs_masked $dst_src, $dst_src, $v0\t# KILL $tmp" %}
   ins_encode %{
@@ -343,7 +334,6 @@ instruct vabs_masked(vReg dst_src, vRegMask_V0 v0, vReg tmp) %{
 instruct vabs_fp_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (AbsVF dst_src v0));
   match(Set dst_src (AbsVD dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vabs_fp_masked $dst_src, $dst_src, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -360,7 +350,6 @@ instruct vadd(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (AddVS src1 src2));
   match(Set dst (AddVI src1 src2));
   match(Set dst (AddVL src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vadd $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -374,7 +363,6 @@ instruct vadd(vReg dst, vReg src1, vReg src2) %{
 
 instruct vadd_hfp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (AddVHF src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vadd_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -390,7 +378,6 @@ instruct vadd_hfp(vReg dst, vReg src1, vReg src2) %{
 instruct vadd_fp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (AddVF src1 src2));
   match(Set dst (AddVD src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vadd_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -409,7 +396,6 @@ instruct vadd_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (AddVS (Binary dst_src1 src2) v0));
   match(Set dst_src1 (AddVI (Binary dst_src1 src2) v0));
   match(Set dst_src1 (AddVL (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vadd_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -424,7 +410,6 @@ instruct vadd_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 instruct vadd_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (AddVF (Binary dst_src1 src2) v0));
   match(Set dst_src1 (AddVD (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vadd_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -559,7 +544,6 @@ instruct vsub(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (SubVS src1 src2));
   match(Set dst (SubVI src1 src2));
   match(Set dst (SubVL src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vsub $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -572,7 +556,6 @@ instruct vsub(vReg dst, vReg src1, vReg src2) %{
 
 instruct vsub_hfp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (SubVHF src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vsub_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -587,7 +570,6 @@ instruct vsub_hfp(vReg dst, vReg src1, vReg src2) %{
 instruct vsub_fp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (SubVF src1 src2));
   match(Set dst (SubVD src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vsub_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -605,7 +587,6 @@ instruct vsub_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (SubVS (Binary dst_src1 src2) v0));
   match(Set dst_src1 (SubVI (Binary dst_src1 src2) v0));
   match(Set dst_src1 (SubVL (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vsub_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -619,7 +600,6 @@ instruct vsub_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 instruct vsub_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (SubVF (Binary dst_src1 src2) v0));
   match(Set dst_src1 (SubVD (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vsub_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -695,7 +675,6 @@ instruct vsubL_vx_masked(vReg dst_src, iRegL src2, vRegMask_V0 v0) %{
 instruct vsadd(vReg dst, vReg src1, vReg src2) %{
   predicate(n->is_SaturatingVector() && !n->as_SaturatingVector()->is_unsigned());
   match(Set dst (SaturatingAddV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vsadd $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -712,7 +691,6 @@ instruct vsadd(vReg dst, vReg src1, vReg src2) %{
 instruct vsaddu(vReg dst, vReg src1, vReg src2) %{
   predicate(n->is_SaturatingVector() && n->as_SaturatingVector()->is_unsigned());
   match(Set dst (SaturatingAddV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vsaddu $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -729,7 +707,6 @@ instruct vsaddu(vReg dst, vReg src1, vReg src2) %{
 instruct vsadd_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
   predicate(n->is_SaturatingVector() && !n->as_SaturatingVector()->is_unsigned());
   match(Set dst_src (SaturatingAddV (Binary dst_src src1) v0));
-  ins_cost(VEC_COST);
   format %{ "vsadd_masked $dst_src, $dst_src, $src1, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -746,7 +723,6 @@ instruct vsadd_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
 instruct vsaddu_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
   predicate(n->is_SaturatingVector() && n->as_SaturatingVector()->is_unsigned());
   match(Set dst_src (SaturatingAddV (Binary dst_src src1) v0));
-  ins_cost(VEC_COST);
   format %{ "vsaddu_masked $dst_src, $dst_src, $src1, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -763,7 +739,6 @@ instruct vsaddu_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
 instruct vssub(vReg dst, vReg src1, vReg src2) %{
   predicate(n->is_SaturatingVector() && !n->as_SaturatingVector()->is_unsigned());
   match(Set dst (SaturatingSubV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vssub $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -780,7 +755,6 @@ instruct vssub(vReg dst, vReg src1, vReg src2) %{
 instruct vssubu(vReg dst, vReg src1, vReg src2) %{
   predicate(n->is_SaturatingVector() && n->as_SaturatingVector()->is_unsigned());
   match(Set dst (SaturatingSubV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vssubu $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -797,7 +771,6 @@ instruct vssubu(vReg dst, vReg src1, vReg src2) %{
 instruct vssub_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
   predicate(n->is_SaturatingVector() && !n->as_SaturatingVector()->is_unsigned());
   match(Set dst_src (SaturatingSubV (Binary dst_src src1) v0));
-  ins_cost(VEC_COST);
   format %{ "vssub_masked $dst_src, $dst_src, $src1, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -814,7 +787,6 @@ instruct vssub_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
 instruct vssubu_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
   predicate(n->is_SaturatingVector() && n->as_SaturatingVector()->is_unsigned());
   match(Set dst_src (SaturatingSubV (Binary dst_src src1) v0));
-  ins_cost(VEC_COST);
   format %{ "vssubu_masked $dst_src, $dst_src, $src1, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -830,7 +802,6 @@ instruct vssubu_masked(vReg dst_src, vReg src1, vRegMask_V0 v0) %{
 
 instruct vand(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (AndV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vand $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -846,7 +817,6 @@ instruct vand(vReg dst, vReg src1, vReg src2) %{
 
 instruct vand_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (AndV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vand_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -986,7 +956,6 @@ instruct vandL_vx_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
 
 instruct vor(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (OrV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vor $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1002,7 +971,6 @@ instruct vor(vReg dst, vReg src1, vReg src2) %{
 
 instruct vor_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (OrV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vor_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1142,7 +1110,6 @@ instruct vorL_vx_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
 
 instruct vxor(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (XorV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vxor $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1158,7 +1125,6 @@ instruct vxor(vReg dst, vReg src1, vReg src2) %{
 
 instruct vxor_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (XorV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vxor_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1582,7 +1548,6 @@ instruct vnotL_masked(vReg dst_src, immI_M1 m1, vRegMask_V0 v0) %{
 
 instruct vdiv_hfp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (DivVHF src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vdiv_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -1598,7 +1563,6 @@ instruct vdiv_hfp(vReg dst, vReg src1, vReg src2) %{
 instruct vdiv_fp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (DivVF src1 src2));
   match(Set dst (DivVD src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vdiv_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1615,7 +1579,6 @@ instruct vdiv_fp(vReg dst, vReg src1, vReg src2) %{
 instruct vdiv_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (DivVF (Binary dst_src1 src2) v0));
   match(Set dst_src1 (DivVD (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vdiv_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1633,7 +1596,6 @@ instruct vmax(vReg dst, vReg src1, vReg src2) %{
   predicate(Matcher::vector_element_basic_type(n) != T_FLOAT &&
             Matcher::vector_element_basic_type(n) != T_DOUBLE);
   match(Set dst (MaxV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmax $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1648,7 +1610,6 @@ instruct vmin(vReg dst, vReg src1, vReg src2) %{
   predicate(Matcher::vector_element_basic_type(n) != T_FLOAT &&
             Matcher::vector_element_basic_type(n) != T_DOUBLE);
   match(Set dst (MinV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmin $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1665,7 +1626,6 @@ instruct vmax_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   predicate(Matcher::vector_element_basic_type(n) != T_FLOAT &&
             Matcher::vector_element_basic_type(n) != T_DOUBLE);
   match(Set dst_src1 (MaxV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vmax_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1680,7 +1640,6 @@ instruct vmin_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   predicate(Matcher::vector_element_basic_type(n) != T_FLOAT &&
             Matcher::vector_element_basic_type(n) != T_DOUBLE);
   match(Set dst_src1 (MinV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vmin_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1695,7 +1654,6 @@ instruct vmin_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 
 instruct vmaxu(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (UMaxV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmaxu $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1709,7 +1667,6 @@ instruct vmaxu(vReg dst, vReg src1, vReg src2) %{
 
 instruct vminu(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (UMinV src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vminu $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1725,7 +1682,6 @@ instruct vminu(vReg dst, vReg src1, vReg src2) %{
 
 instruct vmaxu_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (UMaxV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vmaxu_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1739,7 +1695,6 @@ instruct vmaxu_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 
 instruct vminu_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (UMinV (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vminu_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1756,7 +1711,6 @@ instruct vminu_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 instruct vmax_hfp(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst (MaxVHF src1 src2));
   effect(TEMP_DEF dst, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmax_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -1771,7 +1725,6 @@ instruct vmax_hfp(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
 instruct vmin_hfp(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst (MinVHF src1 src2));
   effect(TEMP_DEF dst, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmin_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -1790,7 +1743,6 @@ instruct vmax_fp(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
             Matcher::vector_element_basic_type(n) == T_DOUBLE);
   match(Set dst (MaxV src1 src2));
   effect(TEMP_DEF dst, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmax_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1806,7 +1758,6 @@ instruct vmin_fp(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{
             Matcher::vector_element_basic_type(n) == T_DOUBLE);
   match(Set dst (MinV src1 src2));
   effect(TEMP_DEF dst, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmin_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1824,7 +1775,6 @@ instruct vmax_fp_masked(vReg dst_src1, vReg src2, vRegMask vmask, vReg tmp1, vRe
             Matcher::vector_element_basic_type(n) == T_DOUBLE);
   match(Set dst_src1 (MaxV (Binary dst_src1 src2) vmask));
   effect(TEMP_DEF dst_src1, TEMP tmp1, TEMP tmp2, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmax_fp_masked $dst_src1, $dst_src1, $src2, $vmask\t# KILL $tmp1, $tmp2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1841,7 +1791,6 @@ instruct vmin_fp_masked(vReg dst_src1, vReg src2, vRegMask vmask, vReg tmp1, vRe
             Matcher::vector_element_basic_type(n) == T_DOUBLE);
   match(Set dst_src1 (MinV (Binary dst_src1 src2) vmask));
   effect(TEMP_DEF dst_src1, TEMP tmp1, TEMP tmp2, TEMP v0);
-  ins_cost(VEC_COST);
   format %{ "vmin_fp_masked $dst_src1, $dst_src1, $src2, $vmask\t# KILL $tmp1, $tmp2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -1858,7 +1807,6 @@ instruct vmin_fp_masked(vReg dst_src1, vReg src2, vRegMask vmask, vReg tmp1, vRe
 // dst_src1 = src2 * src3 + dst_src1 (half precision)
 instruct vhfmla(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVHF dst_src1 (Binary src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vhfmla $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -1875,7 +1823,6 @@ instruct vhfmla(vReg dst_src1, vReg src2, vReg src3) %{
 instruct vfmla(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVF dst_src1 (Binary src2 src3)));
   match(Set dst_src1 (FmaVD dst_src1 (Binary src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vfmla $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -1910,7 +1857,6 @@ instruct vfmadd_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
 // "(-src2) * src3 + dst_src1" has been idealized to "src3 * (-src2) + dst_src1"
 instruct vfmlsF(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVF dst_src1 (Binary src2 (NegVF src3))));
-  ins_cost(VEC_COST);
   format %{ "vfmlsF $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -1925,7 +1871,6 @@ instruct vfmlsF(vReg dst_src1, vReg src2, vReg src3) %{
 // "(-src2) * src3 + dst_src1" has been idealized to "src3 * (-src2) + dst_src1"
 instruct vfmlsD(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVD dst_src1 (Binary src2 (NegVD src3))));
-  ins_cost(VEC_COST);
   format %{ "vfmlsD $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -1959,7 +1904,6 @@ instruct vfnmsub_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
 // "(-src2) * src3 - dst_src1" has been idealized to "src3 * (-src2) - dst_src1"
 instruct vfnmlaF(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 (NegVF src3))));
-  ins_cost(VEC_COST);
   format %{ "vfnmlaF $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -1974,7 +1918,6 @@ instruct vfnmlaF(vReg dst_src1, vReg src2, vReg src3) %{
 // "(-src2) * src3 - dst_src1" has been idealized to "src3 * (-src2) - dst_src1"
 instruct vfnmlaD(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 (NegVD src3))));
-  ins_cost(VEC_COST);
   format %{ "vfnmlaD $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -2007,7 +1950,6 @@ instruct vfnmadd_masked(vReg dst_src1, vReg src2, vReg src3, vRegMask_V0 v0) %{
 // dst_src1 = src2 * src3 - dst_src1
 instruct vfnmlsF(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vfnmlsF $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -2021,7 +1963,6 @@ instruct vfnmlsF(vReg dst_src1, vReg src2, vReg src3) %{
 // dst_src1 = -dst_src1 + src2 * src3
 instruct vfnmlsD(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vfnmlsD $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     assert(UseFMA, "Needs FMA instructions support.");
@@ -2057,7 +1998,6 @@ instruct vmla(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (AddVS dst_src1 (MulVS src2 src3)));
   match(Set dst_src1 (AddVI dst_src1 (MulVI src2 src3)));
   match(Set dst_src1 (AddVL dst_src1 (MulVL src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vmla $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2093,7 +2033,6 @@ instruct vmls(vReg dst_src1, vReg src2, vReg src3) %{
   match(Set dst_src1 (SubVS dst_src1 (MulVS src2 src3)));
   match(Set dst_src1 (SubVI dst_src1 (MulVI src2 src3)));
   match(Set dst_src1 (SubVL dst_src1 (MulVL src2 src3)));
-  ins_cost(VEC_COST);
   format %{ "vmls $dst_src1, $dst_src1, $src2, $src3" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2128,7 +2067,6 @@ instruct vmul(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (MulVS src1 src2));
   match(Set dst (MulVI src1 src2));
   match(Set dst (MulVL src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmul $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2141,7 +2079,6 @@ instruct vmul(vReg dst, vReg src1, vReg src2) %{
 
 instruct vmul_hfp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (MulVHF src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmul_hfp $dst, $src1, $src2" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -2156,7 +2093,6 @@ instruct vmul_hfp(vReg dst, vReg src1, vReg src2) %{
 instruct vmul_fp(vReg dst, vReg src1, vReg src2) %{
   match(Set dst (MulVF src1 src2));
   match(Set dst (MulVD src1 src2));
-  ins_cost(VEC_COST);
   format %{ "vmul_fp $dst, $src1, $src2" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2174,7 +2110,6 @@ instruct vmul_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (MulVS (Binary dst_src1 src2) v0));
   match(Set dst_src1 (MulVI (Binary dst_src1 src2) v0));
   match(Set dst_src1 (MulVL (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vmul_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2188,7 +2123,6 @@ instruct vmul_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
 instruct vmul_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{
   match(Set dst_src1 (MulVF (Binary dst_src1 src2) v0));
   match(Set dst_src1 (MulVD (Binary dst_src1 src2) v0));
-  ins_cost(VEC_COST);
   format %{ "vmul_fp_masked $dst_src1, $dst_src1, $src2, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2262,7 +2196,6 @@ instruct vmulL_vx_masked(vReg dst_src, iRegL src2, vRegMask_V0 v0) %{
 instruct vneg(vReg dst, vReg src) %{
   match(Set dst (NegVI src));
   match(Set dst (NegVL src));
-  ins_cost(VEC_COST);
   format %{ "vneg $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2277,7 +2210,6 @@ instruct vneg(vReg dst, vReg src) %{
 instruct vneg_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (NegVI dst_src v0));
   match(Set dst_src (NegVL dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vneg_masked $dst_src, $dst_src, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2293,7 +2225,6 @@ instruct vneg_masked(vReg dst_src, vRegMask_V0 v0) %{
 instruct vfneg(vReg dst, vReg src) %{
   match(Set dst (NegVF src));
   match(Set dst (NegVD src));
-  ins_cost(VEC_COST);
   format %{ "vfneg $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2308,7 +2239,6 @@ instruct vfneg(vReg dst, vReg src) %{
 instruct vfneg_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (NegVF dst_src v0));
   match(Set dst_src (NegVD dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vfneg_masked $dst_src, $dst_src, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -2327,7 +2257,6 @@ instruct reduce_and(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (AndReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_and $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2342,7 +2271,6 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (AndReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_andL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2361,7 +2289,6 @@ instruct reduce_and_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (AndReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_and_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2377,7 +2304,6 @@ instruct reduce_andL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v0
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (AndReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_andL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2397,7 +2323,6 @@ instruct reduce_or(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (OrReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_or $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2412,7 +2337,6 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (OrReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_orL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2431,7 +2355,6 @@ instruct reduce_or_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V0
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (OrReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_or_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2447,7 +2370,6 @@ instruct reduce_orL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v0,
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (OrReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_orL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2467,7 +2389,6 @@ instruct reduce_xor(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (XorReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_xor $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2482,7 +2403,6 @@ instruct reduce_xorL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (XorReductionV src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_xorL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2501,7 +2421,6 @@ instruct reduce_xor_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (XorReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_xor_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2517,7 +2436,6 @@ instruct reduce_xorL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v0
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (XorReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_xorL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2537,7 +2455,6 @@ instruct reduce_add(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (AddReductionVI src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_add $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2552,7 +2469,6 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (AddReductionVL src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2575,7 +2491,6 @@ instruct reduce_addF_ordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
   predicate(n->as_Reduction()->requires_strict_order());
   match(Set dst (AddReductionVF src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addF_ordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
@@ -2591,7 +2506,6 @@ instruct reduce_addF_unordered(fRegF dst, fRegF src1, vReg src2, vReg tmp) %{
   predicate(!n->as_Reduction()->requires_strict_order());
   match(Set dst (AddReductionVF src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addF_unordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
@@ -2607,7 +2521,6 @@ instruct reduce_addD_ordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
   predicate(n->as_Reduction()->requires_strict_order());
   match(Set dst (AddReductionVD src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addD_ordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
@@ -2623,7 +2536,6 @@ instruct reduce_addD_unordered(fRegD dst, fRegD src1, vReg src2, vReg tmp) %{
   predicate(!n->as_Reduction()->requires_strict_order());
   match(Set dst (AddReductionVD src1 src2));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addD_unordered $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
@@ -2643,7 +2555,6 @@ instruct reduce_add_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_V
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (AddReductionVI (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_add_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2659,7 +2570,6 @@ instruct reduce_addL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v0
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (AddReductionVL (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2674,7 +2584,6 @@ instruct reduce_addL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v0
 instruct reduce_addF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, vReg tmp) %{
   match(Set dst (AddReductionVF (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addF_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2));
@@ -2689,7 +2598,6 @@ instruct reduce_addF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, vR
 instruct reduce_addD_masked(fRegD dst, fRegD src1, vReg src2, vRegMask_V0 v0, vReg tmp) %{
   match(Set dst (AddReductionVD (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "reduce_addD_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2));
@@ -2708,7 +2616,6 @@ instruct vreduce_max(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (MaxReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vreduce_max $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
@@ -2723,7 +2630,6 @@ instruct vreduce_max(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
 instruct vreduce_maxL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (MaxReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vreduce_maxL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
@@ -2743,7 +2649,6 @@ instruct vreduce_max_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (MaxReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "vreduce_max_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2759,7 +2664,6 @@ instruct vreduce_maxL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (MaxReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "vreduce_maxL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2778,7 +2682,6 @@ instruct vreduce_min(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
             Matcher::vector_element_basic_type(n->in(2)) == T_SHORT ||
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (MinReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vreduce_min $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
@@ -2793,7 +2696,6 @@ instruct vreduce_min(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{
 instruct vreduce_minL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (MinReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP tmp);
   format %{ "vreduce_minL $dst, $src1, $src2\t# KILL $tmp" %}
   ins_encode %{
@@ -2813,7 +2715,6 @@ instruct vreduce_min_masked(iRegINoSp dst, iRegIorL2I src1, vReg src2, vRegMask_
             Matcher::vector_element_basic_type(n->in(2)) == T_INT);
   match(Set dst (MinReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "vreduce_min_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2829,7 +2730,6 @@ instruct vreduce_minL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_LONG);
   match(Set dst (MinReductionV (Binary src1 src2) v0));
   effect(TEMP tmp);
-  ins_cost(VEC_COST);
   format %{ "vreduce_minL_masked $dst, $src1, $src2, $v0\t# KILL $tmp" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this, $src2);
@@ -2846,7 +2746,6 @@ instruct vreduce_minL_masked(iRegLNoSp dst, iRegL src1, vReg src2, vRegMask_V0 v
 instruct vreduce_maxF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_FLOAT);
   match(Set dst (MaxReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_maxF $dst, $src1, $src2, $tmp1, $tmp2" %}
   ins_encode %{
@@ -2861,7 +2760,6 @@ instruct vreduce_maxF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
 instruct vreduce_maxD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_DOUBLE);
   match(Set dst (MaxReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_maxD $dst, $src1, $src2, $tmp1, $tmp2" %}
   ins_encode %{
@@ -2878,7 +2776,6 @@ instruct vreduce_maxD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
 instruct vreduce_maxF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_FLOAT);
   match(Set dst (MaxReductionV (Binary src1 src2) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_maxF_masked $dst, $src1, $src2, $v0\t# KILL $tmp1, $tmp2" %}
   ins_encode %{
@@ -2894,7 +2791,6 @@ instruct vreduce_maxF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, v
 instruct vreduce_maxD_masked(fRegD dst, fRegD src1, vReg src2, vRegMask_V0 v0, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_DOUBLE);
   match(Set dst (MaxReductionV (Binary src1 src2) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_maxD_masked $dst, $src1, $src2, $v0\t# KILL $tmp1, $tmp2" %}
   ins_encode %{
@@ -2912,7 +2808,6 @@ instruct vreduce_maxD_masked(fRegD dst, fRegD src1, vReg src2, vRegMask_V0 v0, v
 instruct vreduce_minF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_FLOAT);
   match(Set dst (MinReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_minF $dst, $src1, $src2, $tmp1, $tmp2" %}
   ins_encode %{
@@ -2927,7 +2822,6 @@ instruct vreduce_minF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{
 instruct vreduce_minD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_DOUBLE);
   match(Set dst (MinReductionV src1 src2));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_minD $dst, $src1, $src2, $tmp1, $tmp2" %}
   ins_encode %{
@@ -2944,7 +2838,6 @@ instruct vreduce_minD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{
 instruct vreduce_minF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_FLOAT);
   match(Set dst (MinReductionV (Binary src1 src2) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_minF_masked $dst, $src1, $src2, $v0\t# KILL $tmp1, $tmp2" %}
   ins_encode %{
@@ -2960,7 +2853,6 @@ instruct vreduce_minF_masked(fRegF dst, fRegF src1, vReg src2, vRegMask_V0 v0, v
 instruct vreduce_minD_masked(fRegD dst, fRegD src1, vReg src2, vRegMask_V0 v0, vReg tmp1, vReg tmp2) %{
   predicate(Matcher::vector_element_basic_type(n->in(2)) == T_DOUBLE);
   match(Set dst (MinReductionV (Binary src1 src2) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2);
   format %{ "vreduce_minD_masked $dst, $src1, $src2, $v0\t# KILL $tmp1, $tmp2" %}
   ins_encode %{
@@ -3039,7 +2931,6 @@ instruct reduce_mulL_masked(iRegLNoSp dst, iRegL isrc, vReg vsrc,
 instruct replicate(vReg dst, iRegIorL2I src) %{
   predicate(Matcher::is_non_long_integral_vector(n));
   match(Set dst (Replicate src));
-  ins_cost(VEC_COST);
   format %{ "replicate $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -3052,7 +2943,6 @@ instruct replicate(vReg dst, iRegIorL2I src) %{
 instruct replicateL(vReg dst, iRegL src) %{
   predicate(Matcher::vector_element_basic_type(n) == T_LONG);
   match(Set dst (Replicate src));
-  ins_cost(VEC_COST);
   format %{ "replicateL $dst, $src" %}
   ins_encode %{
     __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
@@ -3064,7 +2954,6 @@ instruct replicateL(vReg dst, iRegL src) %{
 instruct replicate_imm5(vReg dst, immI5 con) %{
   predicate(Matcher::is_non_long_integral_vector(n));
   match(Set dst (Replicate con));
-  ins_cost(VEC_COST);
   format %{ "replicate_imm5 $dst, $con" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -3077,7 +2966,6 @@ instruct replicate_imm5(vReg dst, immI5 con) %{
 instruct replicateL_imm5(vReg dst, immL5 con) %{
   predicate(Matcher::vector_element_basic_type(n) == T_LONG);
   match(Set dst (Replicate con));
-  ins_cost(VEC_COST);
   format %{ "replicateL_imm5 $dst, $con" %}
   ins_encode %{
     __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
@@ -3089,7 +2977,6 @@ instruct replicateL_imm5(vReg dst, immL5 con) %{
 instruct replicateHF(vReg dst, fRegF src) %{
   predicate(Matcher::vector_element_basic_type(n) == T_SHORT);
   match(Set dst (Replicate src));
-  ins_cost(VEC_COST);
   format %{ "replicateHF $dst, $src" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -3102,7 +2989,6 @@ instruct replicateHF(vReg dst, fRegF src) %{
 instruct replicateF(vReg dst, fRegF src) %{
   predicate(Matcher::vector_element_basic_type(n) == T_FLOAT);
   match(Set dst (Replicate src));
-  ins_cost(VEC_COST);
   format %{ "replicateF $dst, $src" %}
   ins_encode %{
     __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this));
@@ -3114,7 +3000,6 @@ instruct replicateF(vReg dst, fRegF src) %{
 instruct replicateD(vReg dst, fRegD src) %{
   predicate(Matcher::vector_element_basic_type(n) == T_DOUBLE);
   match(Set dst (Replicate src));
-  ins_cost(VEC_COST);
   format %{ "replicateD $dst, $src" %}
   ins_encode %{
     __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this));
@@ -3153,7 +3038,6 @@ instruct replicateD(vReg dst, fRegD src) %{
 
 instruct vasrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (RShiftVB src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vasrB $dst, $src, $shift" %}
   ins_encode %{
@@ -3172,7 +3056,6 @@ instruct vasrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vasrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (RShiftVS src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vasrS $dst, $src, $shift" %}
   ins_encode %{
@@ -3191,7 +3074,6 @@ instruct vasrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vasrI(vReg dst, vReg src, vReg shift) %{
   match(Set dst (RShiftVI src shift));
-  ins_cost(VEC_COST);
   format %{ "vasrI $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_INT, Matcher::vector_length(this));
@@ -3203,7 +3085,6 @@ instruct vasrI(vReg dst, vReg src, vReg shift) %{
 
 instruct vasrL(vReg dst, vReg src, vReg shift) %{
   match(Set dst (RShiftVL src shift));
-  ins_cost(VEC_COST);
   format %{ "vasrL $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
@@ -3215,7 +3096,6 @@ instruct vasrL(vReg dst, vReg src, vReg shift) %{
 
 instruct vasrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVB (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vasrB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3233,7 +3113,6 @@ instruct vasrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vasrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVS (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vasrS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3251,7 +3130,6 @@ instruct vasrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vasrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVI (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vasrI_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3264,7 +3142,6 @@ instruct vasrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vasrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVL (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vasrL_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3277,7 +3154,6 @@ instruct vasrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlslB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (LShiftVB src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vlslB $dst, $src, $shift" %}
   ins_encode %{
@@ -3296,7 +3172,6 @@ instruct vlslB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlslS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (LShiftVS src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vlslS $dst, $src, $shift" %}
   ins_encode %{
@@ -3315,7 +3190,6 @@ instruct vlslS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlslI(vReg dst, vReg src, vReg shift) %{
   match(Set dst (LShiftVI src shift));
-  ins_cost(VEC_COST);
   format %{ "vlslI $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_INT, Matcher::vector_length(this));
@@ -3327,7 +3201,6 @@ instruct vlslI(vReg dst, vReg src, vReg shift) %{
 
 instruct vlslL(vReg dst, vReg src, vReg shift) %{
   match(Set dst (LShiftVL src shift));
-  ins_cost(VEC_COST);
   format %{ "vlslL $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
@@ -3339,7 +3212,6 @@ instruct vlslL(vReg dst, vReg src, vReg shift) %{
 
 instruct vlslB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVB (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vlslB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3360,7 +3232,6 @@ instruct vlslB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vlslS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVS (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vlslS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3381,7 +3252,6 @@ instruct vlslS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vlslI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVI (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vlslI_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3394,7 +3264,6 @@ instruct vlslI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlslL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVL (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vlslL_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3407,7 +3276,6 @@ instruct vlslL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlsrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (URShiftVB src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vlsrB $dst, $src, $shift" %}
   ins_encode %{
@@ -3426,7 +3294,6 @@ instruct vlsrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlsrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst (URShiftVS src shift));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst, TEMP v0);
   format %{ "vlsrS $dst, $src, $shift" %}
   ins_encode %{
@@ -3445,7 +3312,6 @@ instruct vlsrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlsrI(vReg dst, vReg src, vReg shift) %{
   match(Set dst (URShiftVI src shift));
-  ins_cost(VEC_COST);
   format %{ "vlsrI $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_INT, Matcher::vector_length(this));
@@ -3457,7 +3323,6 @@ instruct vlsrI(vReg dst, vReg src, vReg shift) %{
 
 instruct vlsrL(vReg dst, vReg src, vReg shift) %{
   match(Set dst (URShiftVL src shift));
-  ins_cost(VEC_COST);
   format %{ "vlsrL $dst, $src, $shift" %}
   ins_encode %{
     __ vsetvli_helper(T_LONG, Matcher::vector_length(this));
@@ -3469,7 +3334,6 @@ instruct vlsrL(vReg dst, vReg src, vReg shift) %{
 
 instruct vlsrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVB (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vlsrB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3490,7 +3354,6 @@ instruct vlsrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vlsrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVS (Binary dst_src shift) vmask));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src, TEMP v0);
   format %{ "vlsrS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %}
   ins_encode %{
@@ -3511,7 +3374,6 @@ instruct vlsrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0)
 
 instruct vlsrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVI (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vlsrI_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3524,7 +3386,6 @@ instruct vlsrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vlsrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVL (Binary dst_src shift) v0));
-  ins_cost(VEC_COST);
   effect(TEMP_DEF dst_src);
   format %{ "vlsrL_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
@@ -3537,7 +3398,6 @@ instruct vlsrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{
 
 instruct vasrB_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (RShiftVB src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vasrB_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3555,7 +3415,6 @@ instruct vasrB_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vasrS_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (RShiftVS src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vasrS_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3573,7 +3432,6 @@ instruct vasrS_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vasrI_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (RShiftVI src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vasrI_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3591,7 +3449,6 @@ instruct vasrI_vi(vReg dst, vReg src, immI shift) %{
 instruct vasrL_vi(vReg dst, vReg src, immI shift) %{
   predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst (RShiftVL src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vasrL_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3608,7 +3465,6 @@ instruct vasrL_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vasrB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVB (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vasrB_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3625,7 +3481,6 @@ instruct vasrB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vasrS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVS (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vasrS_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3642,7 +3497,6 @@ instruct vasrS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vasrI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (RShiftVI (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vasrI_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3659,7 +3513,6 @@ instruct vasrI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 instruct vasrL_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   predicate((n->in(1)->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst_src (RShiftVL (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vasrL_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3675,7 +3528,6 @@ instruct vasrL_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlsrB_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (URShiftVB src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlsrB_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3697,7 +3549,6 @@ instruct vlsrB_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlsrS_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (URShiftVS src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlsrS_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3719,7 +3570,6 @@ instruct vlsrS_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlsrI_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (URShiftVI src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlsrI_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3737,7 +3587,6 @@ instruct vlsrI_vi(vReg dst, vReg src, immI shift) %{
 instruct vlsrL_vi(vReg dst, vReg src, immI shift) %{
   predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst (URShiftVL src (RShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlsrL_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3754,7 +3603,6 @@ instruct vlsrL_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlsrB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVB (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlsrB_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3775,7 +3623,6 @@ instruct vlsrB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlsrS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVS (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlsrS_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3796,7 +3643,6 @@ instruct vlsrS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlsrI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (URShiftVI (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlsrI_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3813,7 +3659,6 @@ instruct vlsrI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 instruct vlsrL_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   predicate((n->in(1)->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst_src (URShiftVL (Binary dst_src (RShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlsrL_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3829,7 +3674,6 @@ instruct vlsrL_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlslB_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (LShiftVB src (LShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlslB_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3846,7 +3690,6 @@ instruct vlslB_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlslS_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (LShiftVS src (LShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlslS_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3863,7 +3706,6 @@ instruct vlslS_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlslI_vi(vReg dst, vReg src, immI shift) %{
   match(Set dst (LShiftVI src (LShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlslI_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3876,7 +3718,6 @@ instruct vlslI_vi(vReg dst, vReg src, immI shift) %{
 instruct vlslL_vi(vReg dst, vReg src, immI shift) %{
   predicate((n->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst (LShiftVL src (LShiftCntV shift)));
-  ins_cost(VEC_COST);
   format %{ "vlslL_vi $dst, $src, $shift" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3888,7 +3729,6 @@ instruct vlslL_vi(vReg dst, vReg src, immI shift) %{
 
 instruct vlslB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVB (Binary dst_src (LShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlslB_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3906,7 +3746,6 @@ instruct vlslB_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlslS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVS (Binary dst_src (LShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlslS_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3924,7 +3763,6 @@ instruct vlslS_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vlslI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   match(Set dst_src (LShiftVI (Binary dst_src (LShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlslI_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -3938,7 +3776,6 @@ instruct vlslI_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 instruct vlslL_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
   predicate((n->in(1)->in(2)->in(1)->get_int() & 0x3f) < 32);
   match(Set dst_src (LShiftVL (Binary dst_src (LShiftCntV shift)) v0));
-  ins_cost(VEC_COST);
   format %{ "vlslL_vi_masked $dst_src, $dst_src, $shift, $v0" %}
   ins_encode %{
     uint32_t con = (unsigned)$shift$$constant & 0x1f;
@@ -4144,7 +3981,6 @@ instruct vrotate_left_vi_masked(vReg dst_src, immI shift, vRegMask_V0 v0) %{
 
 instruct vsqrt_hfp(vReg dst, vReg src) %{
   match(Set dst (SqrtVHF src));
-  ins_cost(VEC_COST);
   format %{ "vsqrt_hfp $dst, $src" %}
   ins_encode %{
     assert(UseZvfh, "must");
@@ -4158,7 +3994,6 @@ instruct vsqrt_hfp(vReg dst, vReg src) %{
 instruct vsqrt_fp(vReg dst, vReg src) %{
   match(Set dst (SqrtVF src));
   match(Set dst (SqrtVD src));
-  ins_cost(VEC_COST);
   format %{ "vsqrt_fp $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -4173,7 +4008,6 @@ instruct vsqrt_fp(vReg dst, vReg src) %{
 instruct vsqrt_fp_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (SqrtVF dst_src v0));
   match(Set dst_src (SqrtVD dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vsqrt_fp_masked $dst_src, $dst_src, $v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -4472,7 +4306,6 @@ instruct vclearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, Universe dummy,
 // Vector Load Const
 instruct vloadcon(vReg dst, immI0 src) %{
   match(Set dst (VectorLoadConst src));
-  ins_cost(VEC_COST);
   format %{ "vloadcon $dst\t# generate iota indices" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5341,7 +5174,6 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)
 instruct vpopcount_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (PopCountVI dst_src v0));
   match(Set dst_src (PopCountVL dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vcpop_v $dst_src, $dst_src, $v0\t# vcpop_v with mask" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5355,7 +5187,6 @@ instruct vpopcount_masked(vReg dst_src, vRegMask_V0 v0) %{
 instruct vpopcount(vReg dst, vReg src) %{
   match(Set dst (PopCountVI src));
   match(Set dst (PopCountVL src));
-  ins_cost(VEC_COST);
   format %{ "vcpop_v $dst, $src\t# vcpop_v without mask" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5370,7 +5201,6 @@ instruct vpopcount(vReg dst, vReg src) %{
 
 instruct vcountLeadingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (CountLeadingZerosV dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vcount_leading_zeros_masked $dst_src, $dst_src, v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5383,7 +5213,6 @@ instruct vcountLeadingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
 
 instruct vcountLeadingZeros(vReg dst, vReg src) %{
   match(Set dst (CountLeadingZerosV src));
-  ins_cost(VEC_COST);
   format %{ "vcount_leading_zeros $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5398,7 +5227,6 @@ instruct vcountLeadingZeros(vReg dst, vReg src) %{
 
 instruct vcountTrailingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
   match(Set dst_src (CountTrailingZerosV dst_src v0));
-  ins_cost(VEC_COST);
   format %{ "vcount_trailing_zeros_masked $dst_src, $dst_src, v0" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);
@@ -5411,7 +5239,6 @@ instruct vcountTrailingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
 
 instruct vcountTrailingZeros(vReg dst, vReg src) %{
   match(Set dst (CountTrailingZerosV src));
-  ins_cost(VEC_COST);
   format %{ "vcount_trailing_zeros $dst, $src" %}
   ins_encode %{
     BasicType bt = Matcher::vector_element_basic_type(this);