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Move helper functions into c2_MacroAssembler_aarch64.hpp

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This commit is contained in:
erfang 2026-01-26 09:20:11 +00:00
parent fc3dee3d08
commit 10d74f13d7
2 changed files with 40 additions and 78 deletions
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81
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp
View File

@ -1961,86 +1961,23 @@ void C2_MacroAssembler::neon_reduce_logical(int opc, Register dst, BasicType bt,
}
// Helper function to decode min/max reduction operation properties
static void decode_minmax_reduction_opc(int opc, bool& is_min, bool& is_unsigned,
Assembler::Condition& cond) {
void C2_MacroAssembler::decode_minmax_reduction_opc(int opc, bool* is_min,
bool* is_unsigned,
Condition* cond) {
switch(opc) {
case Op_MinReductionV:
is_min = true; is_unsigned = false; cond = Assembler::LT; break;
*is_min = true; *is_unsigned = false; *cond = LT; break;
case Op_MaxReductionV:
is_min = false; is_unsigned = false; cond = Assembler::GT; break;
*is_min = false; *is_unsigned = false; *cond = GT; break;
case Op_UMinReductionV:
is_min = true; is_unsigned = true; cond = Assembler::LO; break;
*is_min = true; *is_unsigned = true; *cond = LO; break;
case Op_UMaxReductionV:
is_min = false; is_unsigned = true; cond = Assembler::HI; break;
*is_min = false; *is_unsigned = true; *cond = HI; break;
default:
ShouldNotReachHere();
}
}
// neon minp: pairwise minimum operation
void C2_MacroAssembler::neon_minp(bool is_unsigned, FloatRegister dst,
SIMD_Arrangement size, FloatRegister src1,
FloatRegister src2) {
if (is_unsigned) {
uminp(dst, size, src1, src2);
} else {
sminp(dst, size, src1, src2);
}
}
// neon maxp: pairwise maximum operation
void C2_MacroAssembler::neon_maxp(bool is_unsigned, FloatRegister dst,
SIMD_Arrangement size, FloatRegister src1,
FloatRegister src2) {
if (is_unsigned) {
umaxp(dst, size, src1, src2);
} else {
smaxp(dst, size, src1, src2);
}
}
// neon minv: reduction minimum operation
void C2_MacroAssembler::neon_minv(bool is_unsigned, FloatRegister dst,
SIMD_Arrangement size, FloatRegister src) {
if (is_unsigned) {
uminv(dst, size, src);
} else {
sminv(dst, size, src);
}
}
// neon maxv: reduction maximum operation
void C2_MacroAssembler::neon_maxv(bool is_unsigned, FloatRegister dst,
SIMD_Arrangement size, FloatRegister src) {
if (is_unsigned) {
umaxv(dst, size, src);
} else {
smaxv(dst, size, src);
}
}
// sve minv: reduction minimum operation
void C2_MacroAssembler::sve_minv(bool is_unsigned, FloatRegister dst,
SIMD_RegVariant size, PRegister pg,
FloatRegister src) {
if (is_unsigned) {
sve_uminv(dst, size, pg, src);
} else {
sve_sminv(dst, size, pg, src);
}
}
// sve maxv: reduction maximum operation
void C2_MacroAssembler::sve_maxv(bool is_unsigned, FloatRegister dst,
SIMD_RegVariant size, PRegister pg,
FloatRegister src) {
if (is_unsigned) {
sve_umaxv(dst, size, pg, src);
} else {
sve_smaxv(dst, size, pg, src);
}
}
// Vector reduction min/max/umin/umax for integral type with ASIMD instructions.
// Note: vtmp is not used and expected to be fnoreg for T_LONG case.
// Clobbers: rscratch1, rflags
@ -2057,7 +1994,7 @@ void C2_MacroAssembler::neon_reduce_minmax_integral(int opc, Register dst, Basic
bool is_min;
bool is_unsigned;
Condition cond;
decode_minmax_reduction_opc(opc, is_min, is_unsigned, cond);
decode_minmax_reduction_opc(opc, &is_min, &is_unsigned, &cond);
BLOCK_COMMENT("neon_reduce_minmax_integral {");
if (bt == T_LONG) {
assert(vtmp == fnoreg, "should be");
@ -2173,7 +2110,7 @@ void C2_MacroAssembler::sve_reduce_integral(int opc, Register dst, BasicType bt,
bool is_min;
bool is_unsigned;
Condition cond;
decode_minmax_reduction_opc(opc, is_min, is_unsigned, cond);
decode_minmax_reduction_opc(opc, &is_min, &is_unsigned, &cond);
is_min ? sve_minv(is_unsigned, tmp, size, pg, src2)
: sve_maxv(is_unsigned, tmp, size, pg, src2);
// Move result from vector to general register

37
src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp
View File

@ -34,19 +34,44 @@
void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
// Typedefs used to disambiguate overloaded member functions.
typedef void (Assembler::*neon_reduction2)
(FloatRegister, Assembler::SIMD_Arrangement, FloatRegister);
typedef void (Assembler::*sve_reduction3)
(FloatRegister, Assembler::SIMD_RegVariant, PRegister, FloatRegister);
// Helper functions for min/max reduction operations
void decode_minmax_reduction_opc(int opc, bool* is_min, bool* is_unsigned, Condition* cond);
void neon_minp(bool is_unsigned, FloatRegister dst, SIMD_Arrangement size,
FloatRegister src1, FloatRegister src2);
FloatRegister src1, FloatRegister src2) {
auto m = is_unsigned ? &Assembler::uminp : &Assembler::sminp;
(this->*m)(dst, size, src1, src2);
}
void neon_maxp(bool is_unsigned, FloatRegister dst, SIMD_Arrangement size,
FloatRegister src1, FloatRegister src2);
FloatRegister src1, FloatRegister src2) {
auto m = is_unsigned ? &Assembler::umaxp : &Assembler::smaxp;
(this->*m)(dst, size, src1, src2);
}
void neon_minv(bool is_unsigned, FloatRegister dst, SIMD_Arrangement size,
FloatRegister src);
FloatRegister src) {
auto m = is_unsigned ? (neon_reduction2)&Assembler::uminv : &Assembler::sminv;
(this->*m)(dst, size, src);
}
void neon_maxv(bool is_unsigned, FloatRegister dst, SIMD_Arrangement size,
FloatRegister src);
FloatRegister src) {
auto m = is_unsigned ? (neon_reduction2)&Assembler::umaxv : &Assembler::smaxv;
(this->*m)(dst, size, src);
}
void sve_minv(bool is_unsigned, FloatRegister dst, SIMD_RegVariant size,
PRegister pg, FloatRegister src);
PRegister pg, FloatRegister src) {
auto m = is_unsigned ? (sve_reduction3)&Assembler::sve_uminv : &Assembler::sve_sminv;
(this->*m)(dst, size, pg, src);
}
void sve_maxv(bool is_unsigned, FloatRegister dst, SIMD_RegVariant size,
PRegister pg, FloatRegister src);
PRegister pg, FloatRegister src) {
auto m = is_unsigned ? (sve_reduction3)&Assembler::sve_umaxv : &Assembler::sve_smaxv;
(this->*m)(dst, size, pg, src);
}
void select_from_two_vectors_neon(FloatRegister dst, FloatRegister src1,
FloatRegister src2, FloatRegister index,