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8346038: [REDO] - [C1] LIR Operations with one input should be implemented as LIR_Op1

Browse Source 
Co-authored-by: Sandhya Viswanathan <sviswanathan@openjdk.org>
Reviewed-by: kvn, sviswanathan
This commit is contained in:
Martin Doerr 2025-01-13 20:03:34 +00:00
parent 7c883c284d
commit 13e1ea53c5
12 changed files with 113 additions and 171 deletions
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2
src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp
View File

@ -779,13 +779,11 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
}
case vmIntrinsics::_floatToFloat16: {
LIR_Opr tmp = new_register(T_FLOAT);
__ move(LIR_OprFact::floatConst(-0.0), tmp);
__ f2hf(src, dst, tmp);
break;
}
case vmIntrinsics::_float16ToFloat: {
LIR_Opr tmp = new_register(T_FLOAT);
__ move(LIR_OprFact::floatConst(-0.0), tmp);
__ hf2f(src, dst, tmp);
break;
}

2
src/hotspot/cpu/ppc/c1_LIRGenerator_ppc.cpp
View File

@ -702,8 +702,6 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
value.load_item();
LIR_Opr dst = rlock_result(x);
LIR_Opr tmp = new_register(T_FLOAT);
// f2hf treats tmp as live_in. Workaround: initialize to some value.
__ move(LIR_OprFact::floatConst(-0.0), tmp); // just to satisfy LinearScan
__ f2hf(value.result(), dst, tmp);
break;
}

64
src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
View File

@ -2393,21 +2393,13 @@ void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_
switch(code) {
case lir_abs :
{
#ifdef _LP64
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
assert(tmp->is_valid(), "need temporary");
__ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
} else
#endif
{
if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
__ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
}
assert(!tmp->is_valid(), "do not need temporary");
__ andpd(dest->as_xmm_double_reg(),
ExternalAddress((address)double_signmask_pool),
rscratch1);
if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
__ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
}
assert(!tmp->is_valid(), "do not need temporary");
__ andpd(dest->as_xmm_double_reg(),
ExternalAddress((address)double_signmask_pool),
rscratch1);
}
break;
@ -3798,41 +3790,21 @@ void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
#endif // _LP64
} else if (dest->is_single_xmm()) {
#ifdef _LP64
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
assert(tmp->is_valid(), "need temporary");
assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
__ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
}
else
#endif
{
assert(!tmp->is_valid(), "do not need temporary");
if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
__ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
}
__ xorps(dest->as_xmm_float_reg(),
ExternalAddress((address)float_signflip_pool),
rscratch1);
assert(!tmp->is_valid(), "do not need temporary");
if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
__ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
}
__ xorps(dest->as_xmm_float_reg(),
ExternalAddress((address)float_signflip_pool),
rscratch1);
} else if (dest->is_double_xmm()) {
#ifdef _LP64
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
assert(tmp->is_valid(), "need temporary");
assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
__ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
}
else
#endif
{
assert(!tmp->is_valid(), "do not need temporary");
if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
__ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
}
__ xorpd(dest->as_xmm_double_reg(),
ExternalAddress((address)double_signflip_pool),
rscratch1);
assert(!tmp->is_valid(), "do not need temporary");
if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
__ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
}
__ xorpd(dest->as_xmm_double_reg(),
ExternalAddress((address)double_signflip_pool),
rscratch1);
#ifndef _LP64
} else if (left->is_single_fpu() || left->is_double_fpu()) {
assert(left->fpu() == 0, "arg must be on TOS");

23
src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp
View File

@ -344,20 +344,7 @@ void LIRGenerator::do_NegateOp(NegateOp* x) {
value.load_item();
LIR_Opr reg = rlock(x);
LIR_Opr tmp = LIR_OprFact::illegalOpr;
#ifdef _LP64
if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
if (x->type()->tag() == doubleTag) {
tmp = new_register(T_DOUBLE);
__ move(LIR_OprFact::doubleConst(-0.0), tmp);
}
else if (x->type()->tag() == floatTag) {
tmp = new_register(T_FLOAT);
__ move(LIR_OprFact::floatConst(-0.0), tmp);
}
}
#endif
__ negate(value.result(), reg, tmp);
__ negate(value.result(), reg);
set_result(x, round_item(reg));
}
@ -830,16 +817,8 @@ void LIRGenerator::do_MathIntrinsic(Intrinsic* x) {
LIR_Opr calc_result = rlock_result(x);
LIR_Opr tmp = LIR_OprFact::illegalOpr;
#ifdef _LP64
if (UseAVX > 2 && (!VM_Version::supports_avx512vl()) &&
(x->id() == vmIntrinsics::_dabs)) {
tmp = new_register(T_DOUBLE);
__ move(LIR_OprFact::doubleConst(-0.0), tmp);
}
#endif
if (x->id() == vmIntrinsics::_floatToFloat16) {
tmp = new_register(T_FLOAT);
__ move(LIR_OprFact::floatConst(-0.0), tmp);
}
switch(x->id()) {

40
src/hotspot/cpu/x86/c1_LinearScan_x86.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2005, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2005, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -635,6 +635,24 @@ void FpuStackAllocator::handle_op1(LIR_Op1* op1) {
break;
}
case lir_abs:
case lir_sqrt:
case lir_neg: {
assert(in->is_fpu_register(), "must be");
assert(res->is_fpu_register(), "must be");
assert(in->is_last_use(), "old value gets destroyed");
insert_free_if_dead(res, in);
insert_exchange(in);
do_rename(in, res);
new_in = to_fpu_stack_top(res);
new_res = new_in;
op1->set_fpu_stack_size(sim()->stack_size());
break;
}
default: {
assert(!in->is_float_kind() && !res->is_float_kind(), "missed a fpu-operation");
}
@ -756,26 +774,6 @@ void FpuStackAllocator::handle_op2(LIR_Op2* op2) {
break;
}
case lir_abs:
case lir_sqrt:
case lir_neg: {
// Right argument appears to be unused
assert(right->is_illegal(), "must be");
assert(left->is_fpu_register(), "must be");
assert(res->is_fpu_register(), "must be");
assert(left->is_last_use(), "old value gets destroyed");
insert_free_if_dead(res, left);
insert_exchange(left);
do_rename(left, res);
new_left = to_fpu_stack_top(res);
new_res = new_left;
op2->set_fpu_stack_size(sim()->stack_size());
break;
}
default: {
assert(false, "missed a fpu-operation");
}

32
src/hotspot/cpu/x86/c1_LinearScan_x86.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2005, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -66,35 +66,7 @@ inline bool LinearScan::is_caller_save(int assigned_reg) {
inline void LinearScan::pd_add_temps(LIR_Op* op) {
switch (op->code()) {
case lir_tan: {
// The slow path for these functions may need to save and
// restore all live registers but we don't want to save and
// restore everything all the time, so mark the xmms as being
// killed. If the slow path were explicit or we could propagate
// live register masks down to the assembly we could do better
// but we don't have any easy way to do that right now. We
// could also consider not killing all xmm registers if we
// assume that slow paths are uncommon but it's not clear that
// would be a good idea.
if (UseSSE > 0) {
#ifdef ASSERT
if (TraceLinearScanLevel >= 2) {
tty->print_cr("killing XMMs for trig");
}
#endif
int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
int op_id = op->id();
for (int xmm = 0; xmm < num_caller_save_xmm_regs; xmm++) {
LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(xmm);
add_temp(reg_num(opr), op_id, noUse, T_ILLEGAL);
}
}
break;
}
default:
break;
}
// No special case behaviours yet
}

33
src/hotspot/cpu/x86/macroAssembler_x86.cpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -1194,7 +1194,11 @@ void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratc
assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
assert(rscratch != noreg || always_reachable(src), "missing");
if (reachable(src)) {
if (UseAVX > 2 &&
(!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
(dst->encoding() >= 16)) {
vpand(dst, dst, src, AVX_512bit, rscratch);
} else if (reachable(src)) {
Assembler::andpd(dst, as_Address(src));
} else {
lea(rscratch, src);
@ -3332,7 +3336,12 @@ void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratc
// Used in sign-bit flipping with aligned address.
assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
if (reachable(src)) {
if (UseAVX > 2 &&
(!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
(dst->encoding() >= 16)) {
vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
} else if (reachable(src)) {
Assembler::xorpd(dst, as_Address(src));
} else {
lea(rscratch, src);
@ -3341,16 +3350,19 @@ void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratc
}
void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
if (UseAVX > 2 &&
(!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
((dst->encoding() >= 16) || (src->encoding() >= 16))) {
Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
}
else {
} else {
Assembler::xorpd(dst, src);
}
}
void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
if (UseAVX > 2 &&
(!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
((dst->encoding() >= 16) || (src->encoding() >= 16))) {
Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
} else {
Assembler::xorps(dst, src);
@ -3362,7 +3374,12 @@ void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratc
// Used in sign-bit flipping with aligned address.
assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
if (reachable(src)) {
if (UseAVX > 2 &&
(!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
(dst->encoding() >= 16)) {
vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
} else if (reachable(src)) {
Assembler::xorps(dst, as_Address(src));
} else {
lea(rscratch, src);

23
src/hotspot/share/c1/c1_LIR.cpp
View File

@ -452,12 +452,18 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
case lir_monaddr: // input and result always valid, info always invalid
case lir_null_check: // input and info always valid, result always invalid
case lir_move: // input and result always valid, may have info
case lir_sqrt: // FP Ops have no info, but input and result
case lir_abs:
case lir_neg:
case lir_f2hf:
case lir_hf2f:
{
assert(op->as_Op1() != nullptr, "must be");
LIR_Op1* op1 = (LIR_Op1*)op;
if (op1->_info) do_info(op1->_info);
if (op1->_opr->is_valid()) do_input(op1->_opr);
if (op1->_tmp->is_valid()) do_temp(op1->_tmp);
if (op1->_result->is_valid()) do_output(op1->_result);
break;
@ -483,6 +489,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
assert(op1->_info != nullptr, ""); do_info(op1->_info);
if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
assert(op1->_tmp->is_illegal(), "not used");
assert(op1->_result->is_illegal(), "safepoint does not produce value");
break;
@ -566,11 +573,6 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
case lir_add:
case lir_sub:
case lir_rem:
case lir_sqrt:
case lir_abs:
case lir_neg:
case lir_f2hf:
case lir_hf2f:
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor:
@ -667,6 +669,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
assert(op1->_info == nullptr, "no info");
assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
assert(op1->_tmp->is_illegal(), "not used");
assert(op1->_result->is_illegal(), "no result");
break;
@ -1730,6 +1733,11 @@ const char * LIR_Op::name() const {
case lir_cond_float_branch: s = "flt_cond_br"; break;
case lir_move: s = "move"; break;
case lir_roundfp: s = "roundfp"; break;
case lir_abs: s = "abs"; break;
case lir_neg: s = "neg"; break;
case lir_sqrt: s = "sqrt"; break;
case lir_f2hf: s = "f2hf"; break;
case lir_hf2f: s = "hf2f"; break;
case lir_rtcall: s = "rtcall"; break;
case lir_throw: s = "throw"; break;
case lir_unwind: s = "unwind"; break;
@ -1746,11 +1754,6 @@ const char * LIR_Op::name() const {
case lir_mul: s = "mul"; break;
case lir_div: s = "div"; break;
case lir_rem: s = "rem"; break;
case lir_abs: s = "abs"; break;
case lir_neg: s = "neg"; break;
case lir_sqrt: s = "sqrt"; break;
case lir_f2hf: s = "f2hf"; break;
case lir_hf2f: s = "hf2f"; break;
case lir_logic_and: s = "logic_and"; break;
case lir_logic_or: s = "logic_or"; break;
case lir_logic_xor: s = "logic_xor"; break;

36
src/hotspot/share/c1/c1_LIR.hpp
View File

@ -939,6 +939,11 @@ enum LIR_Code {
, lir_alloc_object
, lir_monaddr
, lir_roundfp
, lir_sqrt
, lir_abs
, lir_neg
, lir_f2hf
, lir_hf2f
, lir_safepoint
, lir_unwind
, lir_load_klass
@ -955,13 +960,6 @@ enum LIR_Code {
, lir_mul
, lir_div
, lir_rem
, lir_sqrt
, lir_abs
, lir_neg
, lir_tan
, lir_f2hf
, lir_hf2f
, lir_log10
, lir_logic_and
, lir_logic_or
, lir_logic_xor
@ -1357,6 +1355,7 @@ class LIR_Op1: public LIR_Op {
protected:
LIR_Opr _opr; // input operand
LIR_Opr _tmp;
BasicType _type; // Operand types
LIR_PatchCode _patch; // only required with patchin (NEEDS_CLEANUP: do we want a special instruction for patching?)
@ -1371,12 +1370,21 @@ class LIR_Op1: public LIR_Op {
LIR_Op1(LIR_Code code, LIR_Opr opr, LIR_Opr result = LIR_OprFact::illegalOpr, BasicType type = T_ILLEGAL, LIR_PatchCode patch = lir_patch_none, CodeEmitInfo* info = nullptr)
: LIR_Op(code, result, info)
, _opr(opr)
, _tmp(LIR_OprFact::illegalOpr)
, _type(type)
, _patch(patch) { assert(is_in_range(code, begin_op1, end_op1), "code check"); }
LIR_Op1(LIR_Code code, LIR_Opr opr, LIR_Opr result, LIR_Opr tmp, BasicType type = T_ILLEGAL, LIR_PatchCode patch = lir_patch_none, CodeEmitInfo* info = nullptr)
: LIR_Op(code, result, info)
, _opr(opr)
, _tmp(tmp)
, _type(type)
, _patch(patch) { assert(is_in_range(code, begin_op1, end_op1), "code check"); }
LIR_Op1(LIR_Code code, LIR_Opr opr, LIR_Opr result, BasicType type, LIR_PatchCode patch, CodeEmitInfo* info, LIR_MoveKind kind)
: LIR_Op(code, result, info)
, _opr(opr)
, _tmp(LIR_OprFact::illegalOpr)
, _type(type)
, _patch(patch) {
assert(code == lir_move, "must be");
@ -1386,10 +1394,12 @@ class LIR_Op1: public LIR_Op {
LIR_Op1(LIR_Code code, LIR_Opr opr, CodeEmitInfo* info)
: LIR_Op(code, LIR_OprFact::illegalOpr, info)
, _opr(opr)
, _tmp(LIR_OprFact::illegalOpr)
, _type(T_ILLEGAL)
, _patch(lir_patch_none) { assert(is_in_range(code, begin_op1, end_op1), "code check"); }
LIR_Opr in_opr() const { return _opr; }
LIR_Opr tmp_opr() const { return _tmp; }
LIR_PatchCode patch_code() const { return _patch; }
BasicType type() const { return _type; }
@ -2272,15 +2282,13 @@ class LIR_List: public CompilationResourceObj {
void cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_abs , from, tmp, to)); }
void negate(LIR_Opr from, LIR_Opr to, LIR_Opr tmp = LIR_OprFact::illegalOpr) { append(new LIR_Op2(lir_neg, from, tmp, to)); }
void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_sqrt, from, tmp, to)); }
void abs (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op1(lir_abs , from, to, tmp)); }
void negate(LIR_Opr from, LIR_Opr to, LIR_Opr tmp = LIR_OprFact::illegalOpr) { append(new LIR_Op1(lir_neg, from, to, tmp)); }
void sqrt(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op1(lir_sqrt, from, to, tmp)); }
void fmad(LIR_Opr from, LIR_Opr from1, LIR_Opr from2, LIR_Opr to) { append(new LIR_Op3(lir_fmad, from, from1, from2, to)); }
void fmaf(LIR_Opr from, LIR_Opr from1, LIR_Opr from2, LIR_Opr to) { append(new LIR_Op3(lir_fmaf, from, from1, from2, to)); }
void log10 (LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_log10, from, LIR_OprFact::illegalOpr, to, tmp)); }
void tan (LIR_Opr from, LIR_Opr to, LIR_Opr tmp1, LIR_Opr tmp2) { append(new LIR_Op2(lir_tan , from, tmp1, to, tmp2)); }
void f2hf(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_f2hf, from, tmp, to)); }
void hf2f(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op2(lir_hf2f, from, tmp, to)); }
void f2hf(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op1(lir_f2hf, from, to, tmp)); }
void hf2f(LIR_Opr from, LIR_Opr to, LIR_Opr tmp) { append(new LIR_Op1(lir_hf2f, from, to, tmp)); }
void add (LIR_Opr left, LIR_Opr right, LIR_Opr res) { append(new LIR_Op2(lir_add, left, right, res)); }
void sub (LIR_Opr left, LIR_Opr right, LIR_Opr res, CodeEmitInfo* info = nullptr) { append(new LIR_Op2(lir_sub, left, right, res, info)); }

24
src/hotspot/share/c1/c1_LIRAssembler.cpp
View File

@ -526,6 +526,17 @@ void LIR_Assembler::emit_op1(LIR_Op1* op) {
break;
}
case lir_abs:
case lir_sqrt:
case lir_f2hf:
case lir_hf2f:
intrinsic_op(op->code(), op->in_opr(), op->tmp_opr(), op->result_opr(), op);
break;
case lir_neg:
negate(op->in_opr(), op->result_opr(), op->tmp_opr());
break;
case lir_return: {
assert(op->as_OpReturn() != nullptr, "sanity");
LIR_OpReturn *ret_op = (LIR_OpReturn*)op;
@ -723,19 +734,6 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) {
op->fpu_pop_count() == 1);
break;
case lir_abs:
case lir_sqrt:
case lir_tan:
case lir_log10:
case lir_f2hf:
case lir_hf2f:
intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
break;
case lir_neg:
negate(op->in_opr1(), op->result_opr(), op->in_opr2());
break;
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor:

4
src/hotspot/share/c1/c1_LIRAssembler.hpp
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2000, 2024, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@ -208,7 +208,7 @@ class LIR_Assembler: public CompilationResourceObj {
void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack);
void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info);
void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op);
void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr temp, LIR_Opr dest, LIR_Op* op);
#ifdef ASSERT
void emit_assert(LIR_OpAssert* op);
#endif

1
src/hotspot/share/c1/c1_LinearScan.cpp
View File

@ -6739,7 +6739,6 @@ void LinearScanStatistic::collect(LinearScan* allocator) {
case lir_abs:
case lir_f2hf:
case lir_hf2f:
case lir_log10:
case lir_logic_and:
case lir_logic_or:
case lir_logic_xor: