From 23e3b3ff6ab17a71b16fdf2e61548a7413ddb6d4 Mon Sep 17 00:00:00 2001 From: Aleksey Shipilev Date: Mon, 31 Mar 2025 08:16:10 +0000 Subject: [PATCH] 8351156: C1: Remove FPU stack support after 32-bit x86 removal Reviewed-by: vlivanov, kvn --- .../cpu/aarch64/c1_FpuStackSim_aarch64.cpp | 30 - .../cpu/aarch64/c1_FpuStackSim_aarch64.hpp | 32 - .../cpu/aarch64/c1_LIRAssembler_aarch64.cpp | 18 +- .../cpu/aarch64/c1_LIRAssembler_aarch64.hpp | 2 - .../cpu/aarch64/c1_LinearScan_aarch64.cpp | 31 - src/hotspot/cpu/arm/c1_FpuStackSim_arm.cpp | 25 - src/hotspot/cpu/arm/c1_FpuStackSim_arm.hpp | 30 - src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp | 6 +- src/hotspot/cpu/arm/c1_LinearScan_arm.cpp | 31 - src/hotspot/cpu/ppc/c1_FpuStackSim_ppc.hpp | 32 - src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp | 6 +- src/hotspot/cpu/ppc/c1_LinearScan_ppc.cpp | 33 - .../cpu/riscv/c1_FpuStackSim_riscv.cpp | 30 - .../cpu/riscv/c1_FpuStackSim_riscv.hpp | 32 - .../cpu/riscv/c1_LIRAssembler_arith_riscv.cpp | 2 +- .../cpu/riscv/c1_LIRAssembler_riscv.cpp | 14 +- src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp | 32 - src/hotspot/cpu/s390/c1_FpuStackSim_s390.hpp | 32 - src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp | 6 +- src/hotspot/cpu/s390/c1_LinearScan_s390.cpp | 32 - src/hotspot/cpu/x86/c1_FpuStackSim_x86.cpp | 200 --- src/hotspot/cpu/x86/c1_FpuStackSim_x86.hpp | 72 -- src/hotspot/cpu/x86/c1_FrameMap_x86.cpp | 4 - src/hotspot/cpu/x86/c1_FrameMap_x86.hpp | 2 - src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp | 393 +----- src/hotspot/cpu/x86/c1_LIRAssembler_x86.hpp | 9 - src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp | 77 +- src/hotspot/cpu/x86/c1_LinearScan_x86.cpp | 1113 ----------------- src/hotspot/cpu/x86/c1_LinearScan_x86.hpp | 74 -- src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp | 6 - src/hotspot/share/c1/c1_FpuStackSim.hpp | 37 - src/hotspot/share/c1/c1_Instruction.hpp | 4 - src/hotspot/share/c1/c1_LIR.cpp | 6 - src/hotspot/share/c1/c1_LIR.hpp | 23 +- src/hotspot/share/c1/c1_LIRAssembler.cpp | 25 +- src/hotspot/share/c1/c1_LIRAssembler.hpp | 8 +- src/hotspot/share/c1/c1_LinearScan.cpp | 70 +- src/hotspot/share/c1/c1_LinearScan.hpp | 17 - src/hotspot/share/c1/c1_globals.hpp | 6 - 39 files changed, 47 insertions(+), 2555 deletions(-) delete mode 100644 src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp delete mode 100644 src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.hpp delete mode 100644 src/hotspot/cpu/aarch64/c1_LinearScan_aarch64.cpp delete mode 100644 src/hotspot/cpu/arm/c1_FpuStackSim_arm.cpp delete mode 100644 src/hotspot/cpu/arm/c1_FpuStackSim_arm.hpp delete mode 100644 src/hotspot/cpu/arm/c1_LinearScan_arm.cpp delete mode 100644 src/hotspot/cpu/ppc/c1_FpuStackSim_ppc.hpp delete mode 100644 src/hotspot/cpu/ppc/c1_LinearScan_ppc.cpp delete mode 100644 src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp delete mode 100644 src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp delete mode 100644 src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp delete mode 100644 src/hotspot/cpu/s390/c1_FpuStackSim_s390.hpp delete mode 100644 src/hotspot/cpu/s390/c1_LinearScan_s390.cpp delete mode 100644 src/hotspot/cpu/x86/c1_FpuStackSim_x86.cpp delete mode 100644 src/hotspot/cpu/x86/c1_FpuStackSim_x86.hpp delete mode 100644 src/hotspot/cpu/x86/c1_LinearScan_x86.cpp delete mode 100644 src/hotspot/share/c1/c1_FpuStackSim.hpp diff --git a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp deleted file mode 100644 index 158af57603c..00000000000 --- a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -//-------------------------------------------------------- -// FpuStackSim -//-------------------------------------------------------- - -// No FPU stack on AARCH64 diff --git a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.hpp deleted file mode 100644 index e1cfcf3de6c..00000000000 --- a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.hpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2014, Red Hat Inc. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_AARCH64_C1_FPUSTACKSIM_AARCH64_HPP -#define CPU_AARCH64_C1_FPUSTACKSIM_AARCH64_HPP - -// No FPU stack on AARCH64 -class FpuStackSim; - -#endif // CPU_AARCH64_C1_FPUSTACKSIM_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp index 0c11d26a476..9730e75f266 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp @@ -584,14 +584,14 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix())); else { const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); - reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); + reg2stack(FrameMap::rscratch1_opr, dest, c->type()); } } break; case T_ADDRESS: { const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr); - reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false); + reg2stack(FrameMap::rscratch1_opr, dest, c->type()); } case T_INT: case T_FLOAT: @@ -716,7 +716,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { } } -void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { precond(src->is_register() && dest->is_stack()); uint const c_sz32 = sizeof(uint32_t); @@ -752,7 +752,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po } -void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { +void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { LIR_Address* to_addr = dest->as_address_ptr(); PatchingStub* patch = nullptr; Register compressed_src = rscratch1; @@ -905,7 +905,7 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { temp = FrameMap::rscratch1_opr; stack2reg(src, temp, src->type()); - reg2stack(temp, dest, dest->type(), false); + reg2stack(temp, dest, dest->type()); } @@ -1598,7 +1598,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond); } -void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { +void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) { assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); if (left->is_single_cpu()) { @@ -1769,9 +1769,6 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr } } -void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); } - - void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { switch(code) { case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break; @@ -2849,8 +2846,7 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { if (dest->is_address() || src->is_address()) { - move_op(src, dest, type, lir_patch_none, info, - /*pop_fpu_stack*/false, /*wide*/false); + move_op(src, dest, type, lir_patch_none, info, /*wide*/false); } else { ShouldNotReachHere(); } diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp index d3cf6c9187d..12b941fc4f7 100644 --- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp @@ -33,8 +33,6 @@ friend class ArrayCopyStub; int array_element_size(BasicType type) const; - void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack); - // helper functions which checks for overflow and sets bailout if it // occurs. Always returns a valid embeddable pointer but in the // bailout case the pointer won't be to unique storage. diff --git a/src/hotspot/cpu/aarch64/c1_LinearScan_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LinearScan_aarch64.cpp deleted file mode 100644 index d99916ecb88..00000000000 --- a/src/hotspot/cpu/aarch64/c1_LinearScan_aarch64.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_Instruction.hpp" -#include "c1/c1_LinearScan.hpp" -#include "utilities/bitMap.inline.hpp" - -void LinearScan::allocate_fpu_stack() { - // No FPU stack on AArch64 -} diff --git a/src/hotspot/cpu/arm/c1_FpuStackSim_arm.cpp b/src/hotspot/cpu/arm/c1_FpuStackSim_arm.cpp deleted file mode 100644 index 287f4e412d7..00000000000 --- a/src/hotspot/cpu/arm/c1_FpuStackSim_arm.cpp +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2008, 2017, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -// Nothing needed here diff --git a/src/hotspot/cpu/arm/c1_FpuStackSim_arm.hpp b/src/hotspot/cpu/arm/c1_FpuStackSim_arm.hpp deleted file mode 100644 index 74e5ebc81b7..00000000000 --- a/src/hotspot/cpu/arm/c1_FpuStackSim_arm.hpp +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_ARM_C1_FPUSTACKSIM_ARM_HPP -#define CPU_ARM_C1_FPUSTACKSIM_ARM_HPP - -// Nothing needed here - -#endif // CPU_ARM_C1_FPUSTACKSIM_ARM_HPP diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp index 14a51bf4b13..66c7b916f1f 100644 --- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp +++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp @@ -454,7 +454,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { } } -void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { assert(src->is_register(), "should not call otherwise"); assert(dest->is_stack(), "should not call otherwise"); @@ -493,7 +493,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, - bool pop_fpu_stack, bool wide) { + bool wide) { LIR_Address* to_addr = dest->as_address_ptr(); Register base_reg = to_addr->base()->as_pointer_register(); const bool needs_patching = (patch_code != lir_patch_none); @@ -1512,7 +1512,7 @@ static int reg_size(LIR_Opr op) { } #endif -void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { +void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) { assert(info == nullptr, "unused on this code path"); assert(dest->is_register(), "wrong items state"); diff --git a/src/hotspot/cpu/arm/c1_LinearScan_arm.cpp b/src/hotspot/cpu/arm/c1_LinearScan_arm.cpp deleted file mode 100644 index f1d6c6a0ff9..00000000000 --- a/src/hotspot/cpu/arm/c1_LinearScan_arm.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2008, 2025, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_Instruction.hpp" -#include "c1/c1_LinearScan.hpp" -#include "utilities/bitMap.inline.hpp" - -void LinearScan::allocate_fpu_stack() { - // No FPU stack on ARM -} diff --git a/src/hotspot/cpu/ppc/c1_FpuStackSim_ppc.hpp b/src/hotspot/cpu/ppc/c1_FpuStackSim_ppc.hpp deleted file mode 100644 index 84d180a9b03..00000000000 --- a/src/hotspot/cpu/ppc/c1_FpuStackSim_ppc.hpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2015 SAP SE. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_PPC_C1_FPUSTACKSIM_PPC_HPP -#define CPU_PPC_C1_FPUSTACKSIM_PPC_HPP - -// No FPU stack on PPC. -class FpuStackSim; - -#endif // CPU_PPC_C1_FPUSTACKSIM_PPC_HPP diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp index cae192982d5..c678f409c49 100644 --- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp +++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp @@ -1203,7 +1203,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { } -void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type) { Address addr; if (dest->is_single_word()) { addr = frame_map()->address_for_slot(dest->single_stack_ix()); @@ -1246,7 +1246,7 @@ void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, - LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, + LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { assert(type != T_METADATA, "store of metadata ptr not supported"); LIR_Address* addr = dest->as_address_ptr(); @@ -1617,7 +1617,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, - CodeEmitInfo* info, bool pop_fpu_stack) { + CodeEmitInfo* info) { assert(info == nullptr, "unused on this code path"); assert(left->is_register(), "wrong items state"); assert(dest->is_register(), "wrong items state"); diff --git a/src/hotspot/cpu/ppc/c1_LinearScan_ppc.cpp b/src/hotspot/cpu/ppc/c1_LinearScan_ppc.cpp deleted file mode 100644 index d6ceab8b27b..00000000000 --- a/src/hotspot/cpu/ppc/c1_LinearScan_ppc.cpp +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2015 SAP SE. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_Instruction.hpp" -#include "c1/c1_LinearScan.hpp" -#include "utilities/bitMap.inline.hpp" - -void LinearScan::allocate_fpu_stack() { - Unimplemented(); - // No FPU stack on PPC -} diff --git a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp b/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp deleted file mode 100644 index e3a2606c532..00000000000 --- a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.cpp +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -//-------------------------------------------------------- -// FpuStackSim -//-------------------------------------------------------- - -// No FPU stack on RISCV diff --git a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp b/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp deleted file mode 100644 index 7bc3d311501..00000000000 --- a/src/hotspot/cpu/riscv/c1_FpuStackSim_riscv.hpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP -#define CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP - -// No FPU stack on RISCV -class FpuStackSim; - -#endif // CPU_RISCV_C1_FPUSTACKSIM_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp index 6d53282bba5..787868d4c38 100644 --- a/src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp +++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_arith_riscv.cpp @@ -265,7 +265,7 @@ void LIR_Assembler::arith_op_double_fpu(LIR_Code code, LIR_Opr left, LIR_Opr rig } void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, - CodeEmitInfo* info, bool pop_fpu_stack) { + CodeEmitInfo* info) { assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); if (left->is_single_cpu()) { diff --git a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp index c6af2de3cd4..08d35c2831a 100644 --- a/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp @@ -498,12 +498,12 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { __ sd(zr, frame_map()->address_for_slot(dest->single_stack_ix())); } else { const2reg(src, FrameMap::t1_opr, lir_patch_none, nullptr); - reg2stack(FrameMap::t1_opr, dest, c->type(), false); + reg2stack(FrameMap::t1_opr, dest, c->type()); } break; case T_ADDRESS: // fall through const2reg(src, FrameMap::t1_opr, lir_patch_none, nullptr); - reg2stack(FrameMap::t1_opr, dest, c->type(), false); + reg2stack(FrameMap::t1_opr, dest, c->type()); case T_INT: // fall through case T_FLOAT: if (c->as_jint_bits() == 0) { @@ -620,7 +620,7 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { } } -void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { precond(src->is_register() && dest->is_stack()); uint const c_sz32 = sizeof(uint32_t); @@ -653,7 +653,7 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po } } -void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { +void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { LIR_Address* to_addr = dest->as_address_ptr(); // t0 was used as tmp reg in as_Address, so we use t1 as compressed_src Register compressed_src = t1; @@ -772,7 +772,7 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { } stack2reg(src, temp, src->type()); - reg2stack(temp, dest, dest->type(), false); + reg2stack(temp, dest, dest->type()); } void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { @@ -891,12 +891,10 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L Label done; move_op(opr2, result, type, lir_patch_none, nullptr, - false, // pop_fpu_stack false); // wide __ j(done); __ bind(label); move_op(opr1, result, type, lir_patch_none, nullptr, - false, // pop_fpu_stack false); // wide __ bind(done); } @@ -1868,7 +1866,7 @@ void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* arg void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { if (dest->is_address() || src->is_address()) { - move_op(src, dest, type, lir_patch_none, info, /* pop_fpu_stack */ false, /* wide */ false); + move_op(src, dest, type, lir_patch_none, info, /* wide */ false); } else { ShouldNotReachHere(); } diff --git a/src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp b/src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp deleted file mode 100644 index 8a6dfbbdf1e..00000000000 --- a/src/hotspot/cpu/riscv/c1_LinearScan_riscv.cpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2020, 2022, Huawei Technologies Co., Ltd. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_Instruction.hpp" -#include "c1/c1_LinearScan.hpp" -#include "utilities/bitMap.inline.hpp" - -void LinearScan::allocate_fpu_stack() { - // No FPU stack on RISCV -} diff --git a/src/hotspot/cpu/s390/c1_FpuStackSim_s390.hpp b/src/hotspot/cpu/s390/c1_FpuStackSim_s390.hpp deleted file mode 100644 index 9a13f6ec70c..00000000000 --- a/src/hotspot/cpu/s390/c1_FpuStackSim_s390.hpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016 SAP SE. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_S390_C1_FPUSTACKSIM_S390_HPP -#define CPU_S390_C1_FPUSTACKSIM_S390_HPP - -// No FPU stack on ZARCH_64 -class FpuStackSim; - -#endif // CPU_S390_C1_FPUSTACKSIM_S390_HPP diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp index 48bd5c3afde..8df38d1658b 100644 --- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp +++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp @@ -1016,7 +1016,7 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { } } -void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { assert(src->is_register(), "should not call otherwise"); assert(dest->is_stack(), "should not call otherwise"); @@ -1074,7 +1074,7 @@ void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { } void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type, - LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, + LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { assert(type != T_METADATA, "store of metadata ptr not supported"); LIR_Address* addr = dest_opr->as_address_ptr(); @@ -1501,7 +1501,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L } void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, - CodeEmitInfo* info, bool pop_fpu_stack) { + CodeEmitInfo* info) { assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); if (left->is_single_cpu()) { diff --git a/src/hotspot/cpu/s390/c1_LinearScan_s390.cpp b/src/hotspot/cpu/s390/c1_LinearScan_s390.cpp deleted file mode 100644 index a5edd65ada8..00000000000 --- a/src/hotspot/cpu/s390/c1_LinearScan_s390.cpp +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2016, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2016 SAP SE. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_LinearScan.hpp" -#include "utilities/debug.hpp" - -void LinearScan::allocate_fpu_stack() { - // No FPU stack on ZARCH_64. - ShouldNotCallThis(); -} diff --git a/src/hotspot/cpu/x86/c1_FpuStackSim_x86.cpp b/src/hotspot/cpu/x86/c1_FpuStackSim_x86.cpp deleted file mode 100644 index 878c94c99da..00000000000 --- a/src/hotspot/cpu/x86/c1_FpuStackSim_x86.cpp +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_FpuStackSim.hpp" -#include "c1/c1_FrameMap.hpp" -#include "utilities/growableArray.hpp" -#include "utilities/ostream.hpp" - -//-------------------------------------------------------- -// FpuStackSim -//-------------------------------------------------------- - -// This class maps the FPU registers to their stack locations; it computes -// the offsets between individual registers and simulates the FPU stack. - -const int EMPTY = -1; - -int FpuStackSim::regs_at(int i) const { - assert(i >= 0 && i < FrameMap::nof_fpu_regs, "out of bounds"); - return _regs[i]; -} - -void FpuStackSim::set_regs_at(int i, int val) { - assert(i >= 0 && i < FrameMap::nof_fpu_regs, "out of bounds"); - _regs[i] = val; -} - -void FpuStackSim::dec_stack_size() { - _stack_size--; - assert(_stack_size >= 0, "FPU stack underflow"); -} - -void FpuStackSim::inc_stack_size() { - _stack_size++; - assert(_stack_size <= FrameMap::nof_fpu_regs, "FPU stack overflow"); -} - -FpuStackSim::FpuStackSim(Compilation* compilation) - : _compilation(compilation) -{ - _stack_size = 0; - for (int i = 0; i < FrameMap::nof_fpu_regs; i++) { - set_regs_at(i, EMPTY); - } -} - - -void FpuStackSim::pop() { - if (TraceFPUStack) { tty->print("FPU-pop "); print(); tty->cr(); } - set_regs_at(tos_index(), EMPTY); - dec_stack_size(); -} - -void FpuStackSim::pop(int rnr) { - if (TraceFPUStack) { tty->print("FPU-pop %d", rnr); print(); tty->cr(); } - assert(regs_at(tos_index()) == rnr, "rnr is not on TOS"); - set_regs_at(tos_index(), EMPTY); - dec_stack_size(); -} - - -void FpuStackSim::push(int rnr) { - if (TraceFPUStack) { tty->print("FPU-push %d", rnr); print(); tty->cr(); } - assert(regs_at(stack_size()) == EMPTY, "should be empty"); - set_regs_at(stack_size(), rnr); - inc_stack_size(); -} - - -void FpuStackSim::swap(int offset) { - if (TraceFPUStack) { tty->print("FPU-swap %d", offset); print(); tty->cr(); } - int t = regs_at(tos_index() - offset); - set_regs_at(tos_index() - offset, regs_at(tos_index())); - set_regs_at(tos_index(), t); -} - - -int FpuStackSim::offset_from_tos(int rnr) const { - for (int i = tos_index(); i >= 0; i--) { - if (regs_at(i) == rnr) { - return tos_index() - i; - } - } - assert(false, "FpuStackSim: register not found"); - BAILOUT_("FpuStackSim: register not found", 0); -} - - -int FpuStackSim::get_slot(int tos_offset) const { - return regs_at(tos_index() - tos_offset); -} - -void FpuStackSim::set_slot(int tos_offset, int rnr) { - set_regs_at(tos_index() - tos_offset, rnr); -} - -void FpuStackSim::rename(int old_rnr, int new_rnr) { - if (TraceFPUStack) { tty->print("FPU-rename %d %d", old_rnr, new_rnr); print(); tty->cr(); } - if (old_rnr == new_rnr) - return; - bool found = false; - for (int i = 0; i < stack_size(); i++) { - assert(regs_at(i) != new_rnr, "should not see old occurrences of new_rnr on the stack"); - if (regs_at(i) == old_rnr) { - set_regs_at(i, new_rnr); - found = true; - } - } - assert(found, "should have found at least one instance of old_rnr"); -} - - -bool FpuStackSim::contains(int rnr) { - for (int i = 0; i < stack_size(); i++) { - if (regs_at(i) == rnr) { - return true; - } - } - return false; -} - -bool FpuStackSim::is_empty() { -#ifdef ASSERT - if (stack_size() == 0) { - for (int i = 0; i < FrameMap::nof_fpu_regs; i++) { - assert(regs_at(i) == EMPTY, "must be empty"); - } - } -#endif - return stack_size() == 0; -} - - -bool FpuStackSim::slot_is_empty(int tos_offset) { - return (regs_at(tos_index() - tos_offset) == EMPTY); -} - - -void FpuStackSim::clear() { - if (TraceFPUStack) { tty->print("FPU-clear"); print(); tty->cr(); } - for (int i = tos_index(); i >= 0; i--) { - set_regs_at(i, EMPTY); - } - _stack_size = 0; -} - - -intArray* FpuStackSim::write_state() { - intArray* res = new intArray(1 + FrameMap::nof_fpu_regs); - res->append(stack_size()); - for (int i = 0; i < FrameMap::nof_fpu_regs; i++) { - res->append(regs_at(i)); - } - return res; -} - - -void FpuStackSim::read_state(intArray* fpu_stack_state) { - _stack_size = fpu_stack_state->at(0); - for (int i = 0; i < FrameMap::nof_fpu_regs; i++) { - set_regs_at(i, fpu_stack_state->at(1 + i)); - } -} - - -#ifndef PRODUCT -void FpuStackSim::print() { - tty->print(" N=%d[", stack_size());\ - for (int i = 0; i < stack_size(); i++) { - int reg = regs_at(i); - if (reg != EMPTY) { - tty->print("%d", reg); - } else { - tty->print("_"); - } - }; - tty->print(" ]"); -} -#endif diff --git a/src/hotspot/cpu/x86/c1_FpuStackSim_x86.hpp b/src/hotspot/cpu/x86/c1_FpuStackSim_x86.hpp deleted file mode 100644 index 405aebe9a75..00000000000 --- a/src/hotspot/cpu/x86/c1_FpuStackSim_x86.hpp +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef CPU_X86_C1_FPUSTACKSIM_X86_HPP -#define CPU_X86_C1_FPUSTACKSIM_X86_HPP - -// Simulates the FPU stack and maintains mapping [fpu-register -> stack offset] -// FPU registers are described as numbers from 0..nof_fpu_regs-1 - -class Compilation; - -class FpuStackSim { - private: - Compilation* _compilation; - int _stack_size; - int _regs[FrameMap::nof_fpu_regs]; - - int tos_index() const { return _stack_size - 1; } - - int regs_at(int i) const; - void set_regs_at(int i, int val); - void dec_stack_size(); - void inc_stack_size(); - - // unified bailout support - Compilation* compilation() const { return _compilation; } - void bailout(const char* msg) const { compilation()->bailout(msg); } - bool bailed_out() const { return compilation()->bailed_out(); } - - public: - FpuStackSim(Compilation* compilation); - void pop (); - void pop (int rnr); // rnr must be on tos - void push(int rnr); - void swap(int offset); // exchange tos with tos + offset - int offset_from_tos(int rnr) const; // return the offset of the topmost instance of rnr from TOS - int get_slot(int tos_offset) const; // return the entry at the given offset from TOS - void set_slot(int tos_offset, int rnr); // set the entry at the given offset from TOS - void rename(int old_rnr, int new_rnr); // rename all instances of old_rnr to new_rnr - bool contains(int rnr); // debugging support only - bool is_empty(); - bool slot_is_empty(int tos_offset); - int stack_size() const { return _stack_size; } - void clear(); - intArray* write_state(); - void read_state(intArray* fpu_stack_state); - - void print() PRODUCT_RETURN; -}; - -#endif // CPU_X86_C1_FPUSTACKSIM_X86_HPP diff --git a/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp b/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp index cff2be393bc..e3c78792602 100644 --- a/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp +++ b/src/hotspot/cpu/x86/c1_FrameMap_x86.cpp @@ -108,8 +108,6 @@ LIR_Opr FrameMap::rcx_metadata_opr; LIR_Opr FrameMap::long0_opr; LIR_Opr FrameMap::long1_opr; -LIR_Opr FrameMap::fpu0_float_opr; -LIR_Opr FrameMap::fpu0_double_opr; LIR_Opr FrameMap::xmm0_float_opr; LIR_Opr FrameMap::xmm0_double_opr; @@ -194,8 +192,6 @@ void FrameMap::initialize() { long0_opr = LIR_OprFact::double_cpu(3 /*eax*/, 4 /*edx*/); long1_opr = LIR_OprFact::double_cpu(2 /*ebx*/, 5 /*ecx*/); #endif // _LP64 - fpu0_float_opr = LIR_OprFact::single_fpu(0); - fpu0_double_opr = LIR_OprFact::double_fpu(0); xmm0_float_opr = LIR_OprFact::single_xmm(0); xmm0_double_opr = LIR_OprFact::double_xmm(0); diff --git a/src/hotspot/cpu/x86/c1_FrameMap_x86.hpp b/src/hotspot/cpu/x86/c1_FrameMap_x86.hpp index f2bedcb1d27..ce892efbed2 100644 --- a/src/hotspot/cpu/x86/c1_FrameMap_x86.hpp +++ b/src/hotspot/cpu/x86/c1_FrameMap_x86.hpp @@ -112,8 +112,6 @@ static LIR_Opr long0_opr; static LIR_Opr long1_opr; - static LIR_Opr fpu0_float_opr; - static LIR_Opr fpu0_double_opr; static LIR_Opr xmm0_float_opr; static LIR_Opr xmm0_double_opr; diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp index de1fa1a9cc6..ed16f81cba1 100644 --- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp @@ -161,24 +161,6 @@ address LIR_Assembler::double_constant(double d) { } } -#ifndef _LP64 -void LIR_Assembler::fpop() { - __ fpop(); -} - -void LIR_Assembler::fxch(int i) { - __ fxch(i); -} - -void LIR_Assembler::fld(int i) { - __ fld_s(i); -} - -void LIR_Assembler::ffree(int i) { - __ ffree(i); -} -#endif // !_LP64 - void LIR_Assembler::breakpoint() { __ int3(); } @@ -602,52 +584,28 @@ void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_cod case T_FLOAT: { if (dest->is_single_xmm()) { - if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) { + if (UseAVX <= 2 && c->is_zero_float()) { __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); } else { __ movflt(dest->as_xmm_float_reg(), InternalAddress(float_constant(c->as_jfloat()))); } } else { -#ifndef _LP64 - assert(dest->is_single_fpu(), "must be"); - assert(dest->fpu_regnr() == 0, "dest must be TOS"); - if (c->is_zero_float()) { - __ fldz(); - } else if (c->is_one_float()) { - __ fld1(); - } else { - __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); - } -#else ShouldNotReachHere(); -#endif // !_LP64 } break; } case T_DOUBLE: { if (dest->is_double_xmm()) { - if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) { + if (UseAVX <= 2 && c->is_zero_double()) { __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); } else { __ movdbl(dest->as_xmm_double_reg(), InternalAddress(double_constant(c->as_jdouble()))); } } else { -#ifndef _LP64 - assert(dest->is_double_fpu(), "must be"); - assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); - if (c->is_zero_double()) { - __ fldz(); - } else if (c->is_one_double()) { - __ fld1(); - } else { - __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); - } -#else ShouldNotReachHere(); -#endif // !_LP64 } break; } @@ -841,23 +799,6 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { } #endif // LP64 -#ifndef _LP64 - // special moves from fpu-register to xmm-register - // necessary for method results - } else if (src->is_single_xmm() && !dest->is_single_xmm()) { - __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); - __ fld_s(Address(rsp, 0)); - } else if (src->is_double_xmm() && !dest->is_double_xmm()) { - __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); - __ fld_d(Address(rsp, 0)); - } else if (dest->is_single_xmm() && !src->is_single_xmm()) { - __ fstp_s(Address(rsp, 0)); - __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); - } else if (dest->is_double_xmm() && !src->is_double_xmm()) { - __ fstp_d(Address(rsp, 0)); - __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); -#endif // !_LP64 - // move between xmm-registers } else if (dest->is_single_xmm()) { assert(src->is_single_xmm(), "must match"); @@ -866,19 +807,12 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { assert(src->is_double_xmm(), "must match"); __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); -#ifndef _LP64 - // move between fpu-registers (no instruction necessary because of fpu-stack) - } else if (dest->is_single_fpu() || dest->is_double_fpu()) { - assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); - assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); -#endif // !_LP64 - } else { ShouldNotReachHere(); } } -void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { +void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { assert(src->is_register(), "should not call otherwise"); assert(dest->is_stack(), "should not call otherwise"); @@ -907,27 +841,13 @@ void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool po Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); __ movdbl(dst_addr, src->as_xmm_double_reg()); -#ifndef _LP64 - } else if (src->is_single_fpu()) { - assert(src->fpu_regnr() == 0, "argument must be on TOS"); - Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); - if (pop_fpu_stack) __ fstp_s (dst_addr); - else __ fst_s (dst_addr); - - } else if (src->is_double_fpu()) { - assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); - Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); - if (pop_fpu_stack) __ fstp_d (dst_addr); - else __ fst_d (dst_addr); -#endif // !_LP64 - } else { ShouldNotReachHere(); } } -void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { +void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { LIR_Address* to_addr = dest->as_address_ptr(); PatchingStub* patch = nullptr; Register compressed_src = rscratch1; @@ -954,36 +874,14 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch int null_check_here = code_offset(); switch (type) { case T_FLOAT: { -#ifdef _LP64 assert(src->is_single_xmm(), "not a float"); __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); -#else - if (src->is_single_xmm()) { - __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); - } else { - assert(src->is_single_fpu(), "must be"); - assert(src->fpu_regnr() == 0, "argument must be on TOS"); - if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); - else __ fst_s (as_Address(to_addr)); - } -#endif // _LP64 break; } case T_DOUBLE: { -#ifdef _LP64 assert(src->is_double_xmm(), "not a double"); __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); -#else - if (src->is_double_xmm()) { - __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); - } else { - assert(src->is_double_fpu(), "must be"); - assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); - if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); - else __ fst_d (as_Address(to_addr)); - } -#endif // _LP64 break; } @@ -1100,18 +998,6 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); __ movdbl(dest->as_xmm_double_reg(), src_addr); -#ifndef _LP64 - } else if (dest->is_single_fpu()) { - assert(dest->fpu_regnr() == 0, "dest must be TOS"); - Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); - __ fld_s(src_addr); - - } else if (dest->is_double_fpu()) { - assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); - Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); - __ fld_d(src_addr); -#endif // _LP64 - } else { ShouldNotReachHere(); } @@ -1194,13 +1080,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch if (dest->is_single_xmm()) { __ movflt(dest->as_xmm_float_reg(), from_addr); } else { -#ifndef _LP64 - assert(dest->is_single_fpu(), "must be"); - assert(dest->fpu_regnr() == 0, "dest must be TOS"); - __ fld_s(from_addr); -#else ShouldNotReachHere(); -#endif // !LP64 } break; } @@ -1209,13 +1089,7 @@ void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch if (dest->is_double_xmm()) { __ movdbl(dest->as_xmm_double_reg(), from_addr); } else { -#ifndef _LP64 - assert(dest->is_double_fpu(), "must be"); - assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); - __ fld_d(from_addr); -#else ShouldNotReachHere(); -#endif // !LP64 } break; } @@ -1457,8 +1331,6 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { __ sign_extend_short(dest->as_register()); break; - -#ifdef _LP64 case Bytecodes::_f2d: __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); break; @@ -1498,74 +1370,6 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { case Bytecodes::_d2l: __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg()); break; -#else - case Bytecodes::_f2d: - case Bytecodes::_d2f: - if (dest->is_single_xmm()) { - __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); - } else if (dest->is_double_xmm()) { - __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); - } else { - assert(src->fpu() == dest->fpu(), "register must be equal"); - // do nothing (float result is rounded later through spilling) - } - break; - - case Bytecodes::_i2f: - case Bytecodes::_i2d: - if (dest->is_single_xmm()) { - __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); - } else if (dest->is_double_xmm()) { - __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); - } else { - assert(dest->fpu() == 0, "result must be on TOS"); - __ movl(Address(rsp, 0), src->as_register()); - __ fild_s(Address(rsp, 0)); - } - break; - - case Bytecodes::_l2f: - case Bytecodes::_l2d: - assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); - assert(dest->fpu() == 0, "result must be on TOS"); - __ movptr(Address(rsp, 0), src->as_register_lo()); - __ movl(Address(rsp, BytesPerWord), src->as_register_hi()); - __ fild_d(Address(rsp, 0)); - // float result is rounded later through spilling - break; - - case Bytecodes::_f2i: - case Bytecodes::_d2i: - if (src->is_single_xmm()) { - __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); - } else if (src->is_double_xmm()) { - __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); - } else { - assert(src->fpu() == 0, "input must be on TOS"); - __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_trunc())); - __ fist_s(Address(rsp, 0)); - __ movl(dest->as_register(), Address(rsp, 0)); - __ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std())); - } - // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub - assert(op->stub() != nullptr, "stub required"); - __ cmpl(dest->as_register(), 0x80000000); - __ jcc(Assembler::equal, *op->stub()->entry()); - __ bind(*op->stub()->continuation()); - break; - - case Bytecodes::_f2l: - case Bytecodes::_d2l: - assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); - assert(src->fpu() == 0, "input must be on TOS"); - assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); - - // instruction sequence too long to inline it here - { - __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::fpu2long_stub_id))); - } - break; -#endif // _LP64 default: ShouldNotReachHere(); } @@ -2032,7 +1836,7 @@ void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, L } -void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { +void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) { assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); if (left->is_single_cpu()) { @@ -2213,80 +2017,6 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr } } -#ifndef _LP64 - } else if (left->is_single_fpu()) { - assert(dest->is_single_fpu(), "fpu stack allocation required"); - - if (right->is_single_fpu()) { - arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); - - } else { - assert(left->fpu_regnr() == 0, "left must be on TOS"); - assert(dest->fpu_regnr() == 0, "dest must be on TOS"); - - Address raddr; - if (right->is_single_stack()) { - raddr = frame_map()->address_for_slot(right->single_stack_ix()); - } else if (right->is_constant()) { - address const_addr = float_constant(right->as_jfloat()); - assert(const_addr != nullptr, "incorrect float/double constant maintenance"); - // hack for now - raddr = __ as_Address(InternalAddress(const_addr)); - } else { - ShouldNotReachHere(); - } - - switch (code) { - case lir_add: __ fadd_s(raddr); break; - case lir_sub: __ fsub_s(raddr); break; - case lir_mul: __ fmul_s(raddr); break; - case lir_div: __ fdiv_s(raddr); break; - default: ShouldNotReachHere(); - } - } - - } else if (left->is_double_fpu()) { - assert(dest->is_double_fpu(), "fpu stack allocation required"); - - if (code == lir_mul || code == lir_div) { - // Double values require special handling for strictfp mul/div on x86 - __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias1())); - __ fmulp(left->fpu_regnrLo() + 1); - } - - if (right->is_double_fpu()) { - arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); - - } else { - assert(left->fpu_regnrLo() == 0, "left must be on TOS"); - assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); - - Address raddr; - if (right->is_double_stack()) { - raddr = frame_map()->address_for_slot(right->double_stack_ix()); - } else if (right->is_constant()) { - // hack for now - raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); - } else { - ShouldNotReachHere(); - } - - switch (code) { - case lir_add: __ fadd_d(raddr); break; - case lir_sub: __ fsub_d(raddr); break; - case lir_mul: __ fmul_d(raddr); break; - case lir_div: __ fdiv_d(raddr); break; - default: ShouldNotReachHere(); - } - } - - if (code == lir_mul || code == lir_div) { - // Double values require special handling for strictfp mul/div on x86 - __ fld_x(ExternalAddress(StubRoutines::x86::addr_fpu_subnormal_bias2())); - __ fmulp(dest->fpu_regnrLo() + 1); - } -#endif // !_LP64 - } else if (left->is_single_stack() || left->is_address()) { assert(left == dest, "left and dest must be equal"); @@ -2328,64 +2058,6 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr } } -#ifndef _LP64 -void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { - assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); - assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); - assert(left_index == 0 || right_index == 0, "either must be on top of stack"); - - bool left_is_tos = (left_index == 0); - bool dest_is_tos = (dest_index == 0); - int non_tos_index = (left_is_tos ? right_index : left_index); - - switch (code) { - case lir_add: - if (pop_fpu_stack) __ faddp(non_tos_index); - else if (dest_is_tos) __ fadd (non_tos_index); - else __ fadda(non_tos_index); - break; - - case lir_sub: - if (left_is_tos) { - if (pop_fpu_stack) __ fsubrp(non_tos_index); - else if (dest_is_tos) __ fsub (non_tos_index); - else __ fsubra(non_tos_index); - } else { - if (pop_fpu_stack) __ fsubp (non_tos_index); - else if (dest_is_tos) __ fsubr (non_tos_index); - else __ fsuba (non_tos_index); - } - break; - - case lir_mul: - if (pop_fpu_stack) __ fmulp(non_tos_index); - else if (dest_is_tos) __ fmul (non_tos_index); - else __ fmula(non_tos_index); - break; - - case lir_div: - if (left_is_tos) { - if (pop_fpu_stack) __ fdivrp(non_tos_index); - else if (dest_is_tos) __ fdiv (non_tos_index); - else __ fdivra(non_tos_index); - } else { - if (pop_fpu_stack) __ fdivp (non_tos_index); - else if (dest_is_tos) __ fdivr (non_tos_index); - else __ fdiva (non_tos_index); - } - break; - - case lir_rem: - assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); - __ fremr(noreg); - break; - - default: - ShouldNotReachHere(); - } -} -#endif // _LP64 - void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) { if (value->is_double_xmm()) { @@ -2407,15 +2079,6 @@ void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_ default : ShouldNotReachHere(); } -#ifndef _LP64 - } else if (value->is_double_fpu()) { - assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); - switch(code) { - case lir_abs : __ fabs() ; break; - case lir_sqrt : __ fsqrt(); break; - default : ShouldNotReachHere(); - } -#endif // !_LP64 } else if (code == lir_f2hf) { __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg()); } else if (code == lir_hf2f) { @@ -2733,13 +2396,6 @@ void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, ShouldNotReachHere(); } -#ifndef _LP64 - } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { - assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); - assert(opr2->is_fpu_register(), "both must be registers"); - __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); -#endif // LP64 - } else if (opr1->is_address() && opr2->is_constant()) { LIR_Const* c = opr2->as_constant_ptr(); #ifdef _LP64 @@ -2782,16 +2438,7 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); } else { -#ifdef _LP64 ShouldNotReachHere(); -#else - assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); - assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); - - assert(left->fpu() == 0, "left must be on TOS"); - __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), - op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); -#endif // LP64 } } else { assert(code == lir_cmp_l2i, "check"); @@ -3804,13 +3451,6 @@ void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) { __ xorpd(dest->as_xmm_double_reg(), ExternalAddress((address)double_signflip_pool), rscratch1); -#ifndef _LP64 - } else if (left->is_single_fpu() || left->is_double_fpu()) { - assert(left->fpu() == 0, "arg must be on TOS"); - assert(dest->fpu() == 0, "dest must be TOS"); - __ fchs(); -#endif // !_LP64 - } else { ShouldNotReachHere(); } @@ -3879,29 +3519,6 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, } else { ShouldNotReachHere(); } - -#ifndef _LP64 - } else if (src->is_double_fpu()) { - assert(src->fpu_regnrLo() == 0, "must be TOS"); - if (dest->is_double_stack()) { - __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); - } else if (dest->is_address()) { - __ fistp_d(as_Address(dest->as_address_ptr())); - } else { - ShouldNotReachHere(); - } - - } else if (dest->is_double_fpu()) { - assert(dest->fpu_regnrLo() == 0, "must be TOS"); - if (src->is_double_stack()) { - __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); - } else if (src->is_address()) { - __ fild_d(as_Address(src->as_address_ptr())); - } else { - ShouldNotReachHere(); - } -#endif // !_LP64 - } else { ShouldNotReachHere(); } diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.hpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.hpp index 7dae8ba8a5e..c8f97cece6d 100644 --- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.hpp +++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.hpp @@ -58,13 +58,4 @@ public: void store_parameter(jobject c, int offset_from_esp_in_words); void store_parameter(Metadata* c, int offset_from_esp_in_words); -#ifndef _LP64 - void arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack); - - void fpop(); - void fxch(int i); - void fld(int i); - void ffree(int i); -#endif // !_LP64 - #endif // CPU_X86_C1_LIRASSEMBLER_X86_HPP diff --git a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp index 107107a75b9..fe6d6a58b00 100644 --- a/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp +++ b/src/hotspot/cpu/x86/c1_LIRGenerator_x86.cpp @@ -92,13 +92,8 @@ LIR_Opr LIRGenerator::result_register_for(ValueType* type, bool callee) { case intTag: opr = FrameMap::rax_opr; break; case objectTag: opr = FrameMap::rax_oop_opr; break; case longTag: opr = FrameMap::long0_opr; break; -#ifdef _LP64 case floatTag: opr = FrameMap::xmm0_float_opr; break; case doubleTag: opr = FrameMap::xmm0_double_opr; break; -#else - case floatTag: opr = UseSSE >= 1 ? FrameMap::xmm0_float_opr : FrameMap::fpu0_float_opr; break; - case doubleTag: opr = UseSSE >= 2 ? FrameMap::xmm0_double_opr : FrameMap::fpu0_double_opr; break; -#endif // _LP64 case addressTag: default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr; } @@ -870,62 +865,6 @@ void LIRGenerator::do_LibmIntrinsic(Intrinsic* x) { value.load_item_force(cc->at(0)); } -#ifndef _LP64 - LIR_Opr tmp = FrameMap::fpu0_double_opr; - result_reg = tmp; - switch(x->id()) { - case vmIntrinsics::_dexp: - if (StubRoutines::dexp() != nullptr) { - __ call_runtime_leaf(StubRoutines::dexp(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dexp), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dlog: - if (StubRoutines::dlog() != nullptr) { - __ call_runtime_leaf(StubRoutines::dlog(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dlog10: - if (StubRoutines::dlog10() != nullptr) { - __ call_runtime_leaf(StubRoutines::dlog10(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dlog10), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dpow: - if (StubRoutines::dpow() != nullptr) { - __ call_runtime_leaf(StubRoutines::dpow(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dsin: - if (VM_Version::supports_sse2() && StubRoutines::dsin() != nullptr) { - __ call_runtime_leaf(StubRoutines::dsin(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dcos: - if (VM_Version::supports_sse2() && StubRoutines::dcos() != nullptr) { - __ call_runtime_leaf(StubRoutines::dcos(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), getThreadTemp(), result_reg, cc->args()); - } - break; - case vmIntrinsics::_dtan: - if (StubRoutines::dtan() != nullptr) { - __ call_runtime_leaf(StubRoutines::dtan(), getThreadTemp(), result_reg, cc->args()); - } else { - __ call_runtime_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), getThreadTemp(), result_reg, cc->args()); - } - break; - default: ShouldNotReachHere(); - } -#else switch (x->id()) { case vmIntrinsics::_dexp: if (StubRoutines::dexp() != nullptr) { @@ -984,7 +923,7 @@ void LIRGenerator::do_LibmIntrinsic(Intrinsic* x) { break; default: ShouldNotReachHere(); } -#endif // _LP64 + __ move(result_reg, calc_result); } @@ -1274,20 +1213,6 @@ void LIRGenerator::do_vectorizedMismatch(Intrinsic* x) { __ move(result_reg, result); } -#ifndef _LP64 -// _i2l, _i2f, _i2d, _l2i, _l2f, _l2d, _f2i, _f2l, _f2d, _d2i, _d2l, _d2f -// _i2b, _i2c, _i2s -static LIR_Opr fixed_register_for(BasicType type) { - switch (type) { - case T_FLOAT: return FrameMap::fpu0_float_opr; - case T_DOUBLE: return FrameMap::fpu0_double_opr; - case T_INT: return FrameMap::rax_opr; - case T_LONG: return FrameMap::long0_opr; - default: ShouldNotReachHere(); return LIR_OprFact::illegalOpr; - } -} -#endif - void LIRGenerator::do_Convert(Convert* x) { #ifdef _LP64 LIRItem value(x->value(), this); diff --git a/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp b/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp deleted file mode 100644 index 58816098435..00000000000 --- a/src/hotspot/cpu/x86/c1_LinearScan_x86.cpp +++ /dev/null @@ -1,1113 +0,0 @@ -/* - * Copyright (c) 2005, 2025, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#include "c1/c1_Instruction.hpp" -#include "c1/c1_LinearScan.hpp" -#include "utilities/bitMap.inline.hpp" - - -#ifdef _LP64 -void LinearScan::allocate_fpu_stack() { - // No FPU stack used on x86-64 -} -#else -//---------------------------------------------------------------------- -// Allocation of FPU stack slots (Intel x86 only) -//---------------------------------------------------------------------- - -void LinearScan::allocate_fpu_stack() { - // First compute which FPU registers are live at the start of each basic block - // (To minimize the amount of work we have to do if we have to merge FPU stacks) - if (ComputeExactFPURegisterUsage) { - Interval* intervals_in_register, *intervals_in_memory; - create_unhandled_lists(&intervals_in_register, &intervals_in_memory, is_in_fpu_register, nullptr); - - // ignore memory intervals by overwriting intervals_in_memory - // the dummy interval is needed to enforce the walker to walk until the given id: - // without it, the walker stops when the unhandled-list is empty -> live information - // beyond this point would be incorrect. - Interval* dummy_interval = new Interval(any_reg); - dummy_interval->add_range(max_jint - 2, max_jint - 1); - dummy_interval->set_next(Interval::end()); - intervals_in_memory = dummy_interval; - - IntervalWalker iw(this, intervals_in_register, intervals_in_memory); - - const int num_blocks = block_count(); - for (int i = 0; i < num_blocks; i++) { - BlockBegin* b = block_at(i); - - // register usage is only needed for merging stacks -> compute only - // when more than one predecessor. - // the block must not have any spill moves at the beginning (checked by assertions) - // spill moves would use intervals that are marked as handled and so the usage bit - // would been set incorrectly - - // NOTE: the check for number_of_preds > 1 is necessary. A block with only one - // predecessor may have spill moves at the begin of the block. - // If an interval ends at the current instruction id, it is not possible - // to decide if the register is live or not at the block begin -> the - // register information would be incorrect. - if (b->number_of_preds() > 1) { - int id = b->first_lir_instruction_id(); - ResourceBitMap regs(FrameMap::nof_fpu_regs); - - iw.walk_to(id); // walk after the first instruction (always a label) of the block - assert(iw.current_position() == id, "did not walk completely to id"); - - // Only consider FPU values in registers - Interval* interval = iw.active_first(fixedKind); - while (interval != Interval::end()) { - int reg = interval->assigned_reg(); - assert(reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg, "no fpu register"); - assert(interval->assigned_regHi() == -1, "must not have hi register (doubles stored in one register)"); - assert(interval->from() <= id && id < interval->to(), "interval out of range"); - -#ifndef PRODUCT - if (TraceFPURegisterUsage) { - tty->print("fpu reg %d is live because of ", reg - pd_first_fpu_reg); interval->print(); - } -#endif - - regs.set_bit(reg - pd_first_fpu_reg); - interval = interval->next(); - } - - b->set_fpu_register_usage(regs); - -#ifndef PRODUCT - if (TraceFPURegisterUsage) { - tty->print("FPU regs for block %d, LIR instr %d): ", b->block_id(), id); regs.print_on(tty); tty->cr(); - } -#endif - } - } - } - - FpuStackAllocator alloc(ir()->compilation(), this); - _fpu_stack_allocator = &alloc; - alloc.allocate(); - _fpu_stack_allocator = nullptr; -} - - -FpuStackAllocator::FpuStackAllocator(Compilation* compilation, LinearScan* allocator) - : _compilation(compilation) - , _allocator(allocator) - , _lir(nullptr) - , _pos(-1) - , _sim(compilation) - , _temp_sim(compilation) -{} - -void FpuStackAllocator::allocate() { - int num_blocks = allocator()->block_count(); - for (int i = 0; i < num_blocks; i++) { - // Set up to process block - BlockBegin* block = allocator()->block_at(i); - intArray* fpu_stack_state = block->fpu_stack_state(); - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->cr(); - tty->print_cr("------- Begin of new Block %d -------", block->block_id()); - } -#endif - - assert(fpu_stack_state != nullptr || - block->end()->as_Base() != nullptr || - block->is_set(BlockBegin::exception_entry_flag), - "FPU stack state must be present due to linear-scan order for FPU stack allocation"); - // note: exception handler entries always start with an empty fpu stack - // because stack merging would be too complicated - - if (fpu_stack_state != nullptr) { - sim()->read_state(fpu_stack_state); - } else { - sim()->clear(); - } - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Reading FPU state for block %d:", block->block_id()); - sim()->print(); - tty->cr(); - } -#endif - - allocate_block(block); - CHECK_BAILOUT(); - } -} - -void FpuStackAllocator::allocate_block(BlockBegin* block) { - bool processed_merge = false; - LIR_OpList* insts = block->lir()->instructions_list(); - set_lir(block->lir()); - set_pos(0); - - - // Note: insts->length() may change during loop - while (pos() < insts->length()) { - LIR_Op* op = insts->at(pos()); - _debug_information_computed = false; - -#ifndef PRODUCT - if (TraceFPUStack) { - op->print(); - } - check_invalid_lir_op(op); -#endif - - LIR_OpBranch* branch = op->as_OpBranch(); - LIR_Op1* op1 = op->as_Op1(); - LIR_Op2* op2 = op->as_Op2(); - LIR_OpCall* opCall = op->as_OpCall(); - - if (branch != nullptr && branch->block() != nullptr) { - if (!processed_merge) { - // propagate stack at first branch to a successor - processed_merge = true; - bool required_merge = merge_fpu_stack_with_successors(block); - - assert(!required_merge || branch->cond() == lir_cond_always, "splitting of critical edges should prevent FPU stack mismatches at cond branches"); - } - - } else if (op1 != nullptr) { - handle_op1(op1); - } else if (op2 != nullptr) { - handle_op2(op2); - } else if (opCall != nullptr) { - handle_opCall(opCall); - } - - compute_debug_information(op); - - set_pos(1 + pos()); - } - - // Propagate stack when block does not end with branch - if (!processed_merge) { - merge_fpu_stack_with_successors(block); - } -} - - -void FpuStackAllocator::compute_debug_information(LIR_Op* op) { - if (!_debug_information_computed && op->id() != -1 && allocator()->has_info(op->id())) { - visitor.visit(op); - - // exception handling - if (allocator()->compilation()->has_exception_handlers()) { - XHandlers* xhandlers = visitor.all_xhandler(); - int n = xhandlers->length(); - for (int k = 0; k < n; k++) { - allocate_exception_handler(xhandlers->handler_at(k)); - } - } else { - assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); - } - - // compute debug information - int n = visitor.info_count(); - assert(n > 0, "should not visit operation otherwise"); - - for (int j = 0; j < n; j++) { - CodeEmitInfo* info = visitor.info_at(j); - // Compute debug information - allocator()->compute_debug_info(info, op->id()); - } - } - _debug_information_computed = true; -} - -void FpuStackAllocator::allocate_exception_handler(XHandler* xhandler) { - if (!sim()->is_empty()) { - LIR_List* old_lir = lir(); - int old_pos = pos(); - intArray* old_state = sim()->write_state(); - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->cr(); - tty->print_cr("------- begin of exception handler -------"); - } -#endif - - if (xhandler->entry_code() == nullptr) { - // need entry code to clear FPU stack - LIR_List* entry_code = new LIR_List(_compilation); - entry_code->jump(xhandler->entry_block()); - xhandler->set_entry_code(entry_code); - } - - LIR_OpList* insts = xhandler->entry_code()->instructions_list(); - set_lir(xhandler->entry_code()); - set_pos(0); - - // Note: insts->length() may change during loop - while (pos() < insts->length()) { - LIR_Op* op = insts->at(pos()); - -#ifndef PRODUCT - if (TraceFPUStack) { - op->print(); - } - check_invalid_lir_op(op); -#endif - - switch (op->code()) { - case lir_move: - assert(op->as_Op1() != nullptr, "must be LIR_Op1"); - assert(pos() != insts->length() - 1, "must not be last operation"); - - handle_op1((LIR_Op1*)op); - break; - - case lir_branch: - assert(op->as_OpBranch()->cond() == lir_cond_always, "must be unconditional branch"); - assert(pos() == insts->length() - 1, "must be last operation"); - - // remove all remaining dead registers from FPU stack - clear_fpu_stack(LIR_OprFact::illegalOpr); - break; - - default: - // other operations not allowed in exception entry code - ShouldNotReachHere(); - } - - set_pos(pos() + 1); - } - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->cr(); - tty->print_cr("------- end of exception handler -------"); - } -#endif - - set_lir(old_lir); - set_pos(old_pos); - sim()->read_state(old_state); - } -} - - -int FpuStackAllocator::fpu_num(LIR_Opr opr) { - assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); - return opr->is_single_fpu() ? opr->fpu_regnr() : opr->fpu_regnrLo(); -} - -int FpuStackAllocator::tos_offset(LIR_Opr opr) { - return sim()->offset_from_tos(fpu_num(opr)); -} - - -LIR_Opr FpuStackAllocator::to_fpu_stack(LIR_Opr opr) { - assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); - - int stack_offset = tos_offset(opr); - if (opr->is_single_fpu()) { - return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset(); - } else { - assert(opr->is_double_fpu(), "shouldn't call this otherwise"); - return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset(); - } -} - -LIR_Opr FpuStackAllocator::to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset) { - assert(opr->is_fpu_register() && !opr->is_xmm_register(), "shouldn't call this otherwise"); - assert(dont_check_offset || tos_offset(opr) == 0, "operand is not on stack top"); - - int stack_offset = 0; - if (opr->is_single_fpu()) { - return LIR_OprFact::single_fpu(stack_offset)->make_fpu_stack_offset(); - } else { - assert(opr->is_double_fpu(), "shouldn't call this otherwise"); - return LIR_OprFact::double_fpu(stack_offset)->make_fpu_stack_offset(); - } -} - - - -void FpuStackAllocator::insert_op(LIR_Op* op) { - lir()->insert_before(pos(), op); - set_pos(1 + pos()); -} - - -void FpuStackAllocator::insert_exchange(int offset) { - if (offset > 0) { - LIR_Op1* fxch_op = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr); - insert_op(fxch_op); - sim()->swap(offset); - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Exchanged register: %d New state: ", sim()->get_slot(0)); sim()->print(); tty->cr(); - } -#endif - - } -} - -void FpuStackAllocator::insert_exchange(LIR_Opr opr) { - insert_exchange(tos_offset(opr)); -} - - -void FpuStackAllocator::insert_free(int offset) { - // move stack slot to the top of stack and then pop it - insert_exchange(offset); - - LIR_Op* fpop = new LIR_Op0(lir_fpop_raw); - insert_op(fpop); - sim()->pop(); - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Inserted pop New state: "); sim()->print(); tty->cr(); - } -#endif -} - - -void FpuStackAllocator::insert_free_if_dead(LIR_Opr opr) { - if (sim()->contains(fpu_num(opr))) { - int res_slot = tos_offset(opr); - insert_free(res_slot); - } -} - -void FpuStackAllocator::insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore) { - if (fpu_num(opr) != fpu_num(ignore) && sim()->contains(fpu_num(opr))) { - int res_slot = tos_offset(opr); - insert_free(res_slot); - } -} - -void FpuStackAllocator::insert_copy(LIR_Opr from, LIR_Opr to) { - int offset = tos_offset(from); - LIR_Op1* fld = new LIR_Op1(lir_fld, LIR_OprFact::intConst(offset), LIR_OprFact::illegalOpr); - insert_op(fld); - - sim()->push(fpu_num(to)); - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Inserted copy (%d -> %d) New state: ", fpu_num(from), fpu_num(to)); sim()->print(); tty->cr(); - } -#endif -} - -void FpuStackAllocator::do_rename(LIR_Opr from, LIR_Opr to) { - sim()->rename(fpu_num(from), fpu_num(to)); -} - -void FpuStackAllocator::do_push(LIR_Opr opr) { - sim()->push(fpu_num(opr)); -} - -void FpuStackAllocator::pop_if_last_use(LIR_Op* op, LIR_Opr opr) { - assert(op->fpu_pop_count() == 0, "fpu_pop_count already set"); - assert(tos_offset(opr) == 0, "can only pop stack top"); - - if (opr->is_last_use()) { - op->set_fpu_pop_count(1); - sim()->pop(); - } -} - -void FpuStackAllocator::pop_always(LIR_Op* op, LIR_Opr opr) { - assert(op->fpu_pop_count() == 0, "fpu_pop_count already set"); - assert(tos_offset(opr) == 0, "can only pop stack top"); - - op->set_fpu_pop_count(1); - sim()->pop(); -} - -void FpuStackAllocator::clear_fpu_stack(LIR_Opr preserve) { - int result_stack_size = (preserve->is_fpu_register() && !preserve->is_xmm_register() ? 1 : 0); - while (sim()->stack_size() > result_stack_size) { - assert(!sim()->slot_is_empty(0), "not allowed"); - - if (result_stack_size == 0 || sim()->get_slot(0) != fpu_num(preserve)) { - insert_free(0); - } else { - // move "preserve" to bottom of stack so that all other stack slots can be popped - insert_exchange(sim()->stack_size() - 1); - } - } -} - - -void FpuStackAllocator::handle_op1(LIR_Op1* op1) { - LIR_Opr in = op1->in_opr(); - LIR_Opr res = op1->result_opr(); - - LIR_Opr new_in = in; // new operands relative to the actual fpu stack top - LIR_Opr new_res = res; - - // Note: this switch is processed for all LIR_Op1, regardless if they have FPU-arguments, - // so checks for is_float_kind() are necessary inside the cases - switch (op1->code()) { - - case lir_return: { - // FPU-Stack must only contain the (optional) fpu return value. - // All remaining dead values are popped from the stack - // If the input operand is a fpu-register, it is exchanged to the bottom of the stack - - clear_fpu_stack(in); - if (in->is_fpu_register() && !in->is_xmm_register()) { - new_in = to_fpu_stack_top(in); - } - - break; - } - - case lir_move: { - if (in->is_fpu_register() && !in->is_xmm_register()) { - if (res->is_xmm_register()) { - // move from fpu register to xmm register (necessary for operations that - // are not available in the SSE instruction set) - insert_exchange(in); - new_in = to_fpu_stack_top(in); - pop_always(op1, in); - - } else if (res->is_fpu_register() && !res->is_xmm_register()) { - // move from fpu-register to fpu-register: - // * input and result register equal: - // nothing to do - // * input register is last use: - // rename the input register to result register -> input register - // not present on fpu-stack afterwards - // * input register not last use: - // duplicate input register to result register to preserve input - // - // Note: The LIR-Assembler does not produce any code for fpu register moves, - // so input and result stack index must be equal - - if (fpu_num(in) == fpu_num(res)) { - // nothing to do - } else if (in->is_last_use()) { - insert_free_if_dead(res);//, in); - do_rename(in, res); - } else { - insert_free_if_dead(res); - insert_copy(in, res); - } - new_in = to_fpu_stack(res); - new_res = new_in; - - } else { - // move from fpu-register to memory - // input operand must be on top of stack - - insert_exchange(in); - - // create debug information here because afterwards the register may have been popped - compute_debug_information(op1); - - new_in = to_fpu_stack_top(in); - pop_if_last_use(op1, in); - } - - } else if (res->is_fpu_register() && !res->is_xmm_register()) { - // move from memory/constant to fpu register - // result is pushed on the stack - - insert_free_if_dead(res); - - // create debug information before register is pushed - compute_debug_information(op1); - - do_push(res); - new_res = to_fpu_stack_top(res); - } - break; - } - - case lir_convert: { - Bytecodes::Code bc = op1->as_OpConvert()->bytecode(); - switch (bc) { - case Bytecodes::_d2f: - case Bytecodes::_f2d: - assert(res->is_fpu_register(), "must be"); - assert(in->is_fpu_register(), "must be"); - - if (!in->is_xmm_register() && !res->is_xmm_register()) { - // this is quite the same as a move from fpu-register to fpu-register - // Note: input and result operands must have different types - if (fpu_num(in) == fpu_num(res)) { - // nothing to do - new_in = to_fpu_stack(in); - } else if (in->is_last_use()) { - insert_free_if_dead(res);//, in); - new_in = to_fpu_stack(in); - do_rename(in, res); - } else { - insert_free_if_dead(res); - insert_copy(in, res); - new_in = to_fpu_stack_top(in, true); - } - new_res = to_fpu_stack(res); - } - - break; - - case Bytecodes::_i2f: - case Bytecodes::_l2f: - case Bytecodes::_i2d: - case Bytecodes::_l2d: - assert(res->is_fpu_register(), "must be"); - if (!res->is_xmm_register()) { - insert_free_if_dead(res); - do_push(res); - new_res = to_fpu_stack_top(res); - } - break; - - case Bytecodes::_f2i: - case Bytecodes::_d2i: - assert(in->is_fpu_register(), "must be"); - if (!in->is_xmm_register()) { - insert_exchange(in); - new_in = to_fpu_stack_top(in); - - // TODO: update registers of stub - } - break; - - case Bytecodes::_f2l: - case Bytecodes::_d2l: - assert(in->is_fpu_register(), "must be"); - if (!in->is_xmm_register()) { - insert_exchange(in); - new_in = to_fpu_stack_top(in); - pop_always(op1, in); - } - break; - - case Bytecodes::_i2l: - case Bytecodes::_l2i: - case Bytecodes::_i2b: - case Bytecodes::_i2c: - case Bytecodes::_i2s: - // no fpu operands - break; - - default: - ShouldNotReachHere(); - } - break; - } - - case lir_abs: - case lir_sqrt: - case lir_neg: { - assert(in->is_fpu_register(), "must be"); - assert(res->is_fpu_register(), "must be"); - assert(in->is_last_use(), "old value gets destroyed"); - - insert_free_if_dead(res, in); - insert_exchange(in); - do_rename(in, res); - - new_in = to_fpu_stack_top(res); - new_res = new_in; - - break; - } - - default: { - assert(!in->is_float_kind() && !res->is_float_kind(), "missed a fpu-operation"); - } - } - - op1->set_in_opr(new_in); - op1->set_result_opr(new_res); -} - -void FpuStackAllocator::handle_op2(LIR_Op2* op2) { - LIR_Opr left = op2->in_opr1(); - if (!left->is_float_kind()) { - return; - } - if (left->is_xmm_register()) { - return; - } - - LIR_Opr right = op2->in_opr2(); - LIR_Opr res = op2->result_opr(); - LIR_Opr new_left = left; // new operands relative to the actual fpu stack top - LIR_Opr new_right = right; - LIR_Opr new_res = res; - - assert(!left->is_xmm_register() && !right->is_xmm_register() && !res->is_xmm_register(), "not for xmm registers"); - - switch (op2->code()) { - case lir_cmp: - case lir_cmp_fd2i: - case lir_ucmp_fd2i: - case lir_assert: { - assert(left->is_fpu_register(), "invalid LIR"); - assert(right->is_fpu_register(), "invalid LIR"); - - // the left-hand side must be on top of stack. - // the right-hand side is never popped, even if is_last_use is set - insert_exchange(left); - new_left = to_fpu_stack_top(left); - new_right = to_fpu_stack(right); - pop_if_last_use(op2, left); - break; - } - - case lir_mul: - case lir_div: { - if (res->is_double_fpu()) { - assert(op2->tmp1_opr()->is_fpu_register(), "strict operations need temporary fpu stack slot"); - insert_free_if_dead(op2->tmp1_opr()); - assert(sim()->stack_size() <= 7, "at least one stack slot must be free"); - } - // fall-through: continue with the normal handling of lir_mul and lir_div - } - case lir_add: - case lir_sub: { - assert(left->is_fpu_register(), "must be"); - assert(res->is_fpu_register(), "must be"); - assert(left->is_equal(res), "must be"); - - // either the left-hand or the right-hand side must be on top of stack - // (if right is not a register, left must be on top) - if (!right->is_fpu_register()) { - insert_exchange(left); - new_left = to_fpu_stack_top(left); - } else { - // no exchange necessary if right is already on top of stack - if (tos_offset(right) == 0) { - new_left = to_fpu_stack(left); - new_right = to_fpu_stack_top(right); - } else { - insert_exchange(left); - new_left = to_fpu_stack_top(left); - new_right = to_fpu_stack(right); - } - - if (right->is_last_use()) { - op2->set_fpu_pop_count(1); - - if (tos_offset(right) == 0) { - sim()->pop(); - } else { - // if left is on top of stack, the result is placed in the stack - // slot of right, so a renaming from right to res is necessary - assert(tos_offset(left) == 0, "must be"); - sim()->pop(); - do_rename(right, res); - } - } - } - new_res = to_fpu_stack(res); - - break; - } - - case lir_rem: { - assert(left->is_fpu_register(), "must be"); - assert(right->is_fpu_register(), "must be"); - assert(res->is_fpu_register(), "must be"); - assert(left->is_equal(res), "must be"); - - // Must bring both operands to top of stack with following operand ordering: - // * fpu stack before rem: ... right left - // * fpu stack after rem: ... left - if (tos_offset(right) != 1) { - insert_exchange(right); - insert_exchange(1); - } - insert_exchange(left); - assert(tos_offset(right) == 1, "check"); - assert(tos_offset(left) == 0, "check"); - - new_left = to_fpu_stack_top(left); - new_right = to_fpu_stack(right); - - op2->set_fpu_pop_count(1); - sim()->pop(); - do_rename(right, res); - - new_res = to_fpu_stack_top(res); - break; - } - - default: { - assert(false, "missed a fpu-operation"); - } - } - - op2->set_in_opr1(new_left); - op2->set_in_opr2(new_right); - op2->set_result_opr(new_res); -} - -void FpuStackAllocator::handle_opCall(LIR_OpCall* opCall) { - LIR_Opr res = opCall->result_opr(); - - // clear fpu-stack before call - // it may contain dead values that could not have been removed by previous operations - clear_fpu_stack(LIR_OprFact::illegalOpr); - assert(sim()->is_empty(), "fpu stack must be empty now"); - - // compute debug information before (possible) fpu result is pushed - compute_debug_information(opCall); - - if (res->is_fpu_register() && !res->is_xmm_register()) { - do_push(res); - opCall->set_result_opr(to_fpu_stack_top(res)); - } -} - -#ifndef PRODUCT -void FpuStackAllocator::check_invalid_lir_op(LIR_Op* op) { - switch (op->code()) { - case lir_fpop_raw: - case lir_fxch: - case lir_fld: - assert(false, "operations only inserted by FpuStackAllocator"); - break; - - default: - break; - } -} -#endif - - -void FpuStackAllocator::merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg) { - LIR_Op1* move = new LIR_Op1(lir_move, LIR_OprFact::doubleConst(0), LIR_OprFact::double_fpu(reg)->make_fpu_stack_offset()); - - instrs->instructions_list()->push(move); - - cur_sim->push(reg); - move->set_result_opr(to_fpu_stack(move->result_opr())); - - #ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Added new register: %d New state: ", reg); cur_sim->print(); tty->cr(); - } - #endif -} - -void FpuStackAllocator::merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot) { - assert(slot > 0, "no exchange necessary"); - - LIR_Op1* fxch = new LIR_Op1(lir_fxch, LIR_OprFact::intConst(slot)); - instrs->instructions_list()->push(fxch); - cur_sim->swap(slot); - - #ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Exchanged register: %d New state: ", cur_sim->get_slot(slot)); cur_sim->print(); tty->cr(); - } - #endif -} - -void FpuStackAllocator::merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim) { - int reg = cur_sim->get_slot(0); - - LIR_Op* fpop = new LIR_Op0(lir_fpop_raw); - instrs->instructions_list()->push(fpop); - cur_sim->pop(reg); - - #ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Removed register: %d New state: ", reg); cur_sim->print(); tty->cr(); - } - #endif -} - -bool FpuStackAllocator::merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot) { - int reg = cur_sim->get_slot(change_slot); - - for (int slot = start_slot; slot >= 0; slot--) { - int new_reg = sux_sim->get_slot(slot); - - if (!cur_sim->contains(new_reg)) { - cur_sim->set_slot(change_slot, new_reg); - - #ifndef PRODUCT - if (TraceFPUStack) { - tty->print("Renamed register %d to %d New state: ", reg, new_reg); cur_sim->print(); tty->cr(); - } - #endif - - return true; - } - } - return false; -} - - -void FpuStackAllocator::merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim) { -#ifndef PRODUCT - if (TraceFPUStack) { - tty->cr(); - tty->print("before merging: pred: "); cur_sim->print(); tty->cr(); - tty->print(" sux: "); sux_sim->print(); tty->cr(); - } - - int slot; - for (slot = 0; slot < cur_sim->stack_size(); slot++) { - assert(!cur_sim->slot_is_empty(slot), "not handled by algorithm"); - } - for (slot = 0; slot < sux_sim->stack_size(); slot++) { - assert(!sux_sim->slot_is_empty(slot), "not handled by algorithm"); - } -#endif - - // size difference between cur and sux that must be resolved by adding or removing values form the stack - int size_diff = cur_sim->stack_size() - sux_sim->stack_size(); - - if (!ComputeExactFPURegisterUsage) { - // add slots that are currently free, but used in successor - // When the exact FPU register usage is computed, the stack does - // not contain dead values at merging -> no values must be added - - int sux_slot = sux_sim->stack_size() - 1; - while (size_diff < 0) { - assert(sux_slot >= 0, "slot out of bounds -> error in algorithm"); - - int reg = sux_sim->get_slot(sux_slot); - if (!cur_sim->contains(reg)) { - merge_insert_add(instrs, cur_sim, reg); - size_diff++; - - if (sux_slot + size_diff != 0) { - merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff); - } - } - sux_slot--; - } - } - - assert(cur_sim->stack_size() >= sux_sim->stack_size(), "stack size must be equal or greater now"); - assert(size_diff == cur_sim->stack_size() - sux_sim->stack_size(), "must be"); - - // stack merge algorithm: - // 1) as long as the current stack top is not in the right location (that means - // it should not be on the stack top), exchange it into the right location - // 2) if the stack top is right, but the remaining stack is not ordered correctly, - // the stack top is exchanged away to get another value on top -> - // now step 1) can be continued - // the stack can also contain unused items -> these items are removed from stack - - int finished_slot = sux_sim->stack_size() - 1; - while (finished_slot >= 0 || size_diff > 0) { - while (size_diff > 0 || (cur_sim->stack_size() > 0 && cur_sim->get_slot(0) != sux_sim->get_slot(0))) { - int reg = cur_sim->get_slot(0); - if (sux_sim->contains(reg)) { - int sux_slot = sux_sim->offset_from_tos(reg); - merge_insert_xchg(instrs, cur_sim, sux_slot + size_diff); - - } else if (!merge_rename(cur_sim, sux_sim, finished_slot, 0)) { - assert(size_diff > 0, "must be"); - - merge_insert_pop(instrs, cur_sim); - size_diff--; - } - assert(cur_sim->stack_size() == 0 || cur_sim->get_slot(0) != reg, "register must have been changed"); - } - - while (finished_slot >= 0 && cur_sim->get_slot(finished_slot) == sux_sim->get_slot(finished_slot)) { - finished_slot--; - } - - if (finished_slot >= 0) { - int reg = cur_sim->get_slot(finished_slot); - - if (sux_sim->contains(reg) || !merge_rename(cur_sim, sux_sim, finished_slot, finished_slot)) { - assert(sux_sim->contains(reg) || size_diff > 0, "must be"); - merge_insert_xchg(instrs, cur_sim, finished_slot); - } - assert(cur_sim->get_slot(finished_slot) != reg, "register must have been changed"); - } - } - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("after merging: pred: "); cur_sim->print(); tty->cr(); - tty->print(" sux: "); sux_sim->print(); tty->cr(); - tty->cr(); - } -#endif - assert(cur_sim->stack_size() == sux_sim->stack_size(), "stack size must be equal now"); -} - - -void FpuStackAllocator::merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs) { -#ifndef PRODUCT - if (TraceFPUStack) { - tty->cr(); - tty->print("before cleanup: state: "); cur_sim->print(); tty->cr(); - tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr(); - } -#endif - - int slot = 0; - while (slot < cur_sim->stack_size()) { - int reg = cur_sim->get_slot(slot); - if (!live_fpu_regs.at(reg)) { - if (slot != 0) { - merge_insert_xchg(instrs, cur_sim, slot); - } - merge_insert_pop(instrs, cur_sim); - } else { - slot++; - } - } - -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print("after cleanup: state: "); cur_sim->print(); tty->cr(); - tty->print(" live: "); live_fpu_regs.print_on(tty); tty->cr(); - tty->cr(); - } - - // check if fpu stack only contains live registers - for (unsigned int i = 0; i < live_fpu_regs.size(); i++) { - if (live_fpu_regs.at(i) != cur_sim->contains(i)) { - tty->print_cr("mismatch between required and actual stack content"); - break; - } - } -#endif -} - - -bool FpuStackAllocator::merge_fpu_stack_with_successors(BlockBegin* block) { -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print_cr("Propagating FPU stack state for B%d at LIR_Op position %d to successors:", - block->block_id(), pos()); - sim()->print(); - tty->cr(); - } -#endif - - bool changed = false; - int number_of_sux = block->number_of_sux(); - - if (number_of_sux == 1 && block->sux_at(0)->number_of_preds() > 1) { - // The successor has at least two incoming edges, so a stack merge will be necessary - // If this block is the first predecessor, cleanup the current stack and propagate it - // If this block is not the first predecessor, a stack merge will be necessary - - BlockBegin* sux = block->sux_at(0); - intArray* state = sux->fpu_stack_state(); - LIR_List* instrs = new LIR_List(_compilation); - - if (state != nullptr) { - // Merge with a successors that already has a FPU stack state - // the block must only have one successor because critical edges must been split - FpuStackSim* cur_sim = sim(); - FpuStackSim* sux_sim = temp_sim(); - sux_sim->read_state(state); - - merge_fpu_stack(instrs, cur_sim, sux_sim); - - } else { - // propagate current FPU stack state to successor without state - // clean up stack first so that there are no dead values on the stack - if (ComputeExactFPURegisterUsage) { - FpuStackSim* cur_sim = sim(); - ResourceBitMap live_fpu_regs = block->sux_at(0)->fpu_register_usage(); - assert(live_fpu_regs.size() == FrameMap::nof_fpu_regs, "missing register usage"); - - merge_cleanup_fpu_stack(instrs, cur_sim, live_fpu_regs); - } - - intArray* state = sim()->write_state(); - if (TraceFPUStack) { - tty->print_cr("Setting FPU stack state of B%d (merge path)", sux->block_id()); - sim()->print(); tty->cr(); - } - sux->set_fpu_stack_state(state); - } - - if (instrs->instructions_list()->length() > 0) { - lir()->insert_before(pos(), instrs); - set_pos(instrs->instructions_list()->length() + pos()); - changed = true; - } - - } else { - // Propagate unmodified Stack to successors where a stack merge is not necessary - intArray* state = sim()->write_state(); - for (int i = 0; i < number_of_sux; i++) { - BlockBegin* sux = block->sux_at(i); - -#ifdef ASSERT - for (int j = 0; j < sux->number_of_preds(); j++) { - assert(block == sux->pred_at(j), "all critical edges must be broken"); - } - - // check if new state is same - if (sux->fpu_stack_state() != nullptr) { - intArray* sux_state = sux->fpu_stack_state(); - assert(state->length() == sux_state->length(), "overwriting existing stack state"); - for (int j = 0; j < state->length(); j++) { - assert(state->at(j) == sux_state->at(j), "overwriting existing stack state"); - } - } -#endif -#ifndef PRODUCT - if (TraceFPUStack) { - tty->print_cr("Setting FPU stack state of B%d", sux->block_id()); - sim()->print(); tty->cr(); - } -#endif - - sux->set_fpu_stack_state(state); - } - } - -#ifndef PRODUCT - // assertions that FPU stack state conforms to all successors' states - intArray* cur_state = sim()->write_state(); - for (int i = 0; i < number_of_sux; i++) { - BlockBegin* sux = block->sux_at(i); - intArray* sux_state = sux->fpu_stack_state(); - - assert(sux_state != nullptr, "no fpu state"); - assert(cur_state->length() == sux_state->length(), "incorrect length"); - for (int i = 0; i < cur_state->length(); i++) { - assert(cur_state->at(i) == sux_state->at(i), "element not equal"); - } - } -#endif - - return changed; -} -#endif // _LP64 diff --git a/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp b/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp index e40de213e7a..8669c9ab8a1 100644 --- a/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp +++ b/src/hotspot/cpu/x86/c1_LinearScan_x86.hpp @@ -88,78 +88,4 @@ inline bool LinearScanWalker::pd_init_regs_for_alloc(Interval* cur) { return false; } - -class FpuStackAllocator { - private: - Compilation* _compilation; - LinearScan* _allocator; - - LIR_OpVisitState visitor; - - LIR_List* _lir; - int _pos; - FpuStackSim _sim; - FpuStackSim _temp_sim; - - bool _debug_information_computed; - - LinearScan* allocator() { return _allocator; } - Compilation* compilation() const { return _compilation; } - - // unified bailout support - void bailout(const char* msg) const { compilation()->bailout(msg); } - bool bailed_out() const { return compilation()->bailed_out(); } - - int pos() { return _pos; } - void set_pos(int pos) { _pos = pos; } - LIR_Op* cur_op() { return lir()->instructions_list()->at(pos()); } - LIR_List* lir() { return _lir; } - void set_lir(LIR_List* lir) { _lir = lir; } - FpuStackSim* sim() { return &_sim; } - FpuStackSim* temp_sim() { return &_temp_sim; } - - int fpu_num(LIR_Opr opr); - int tos_offset(LIR_Opr opr); - LIR_Opr to_fpu_stack_top(LIR_Opr opr, bool dont_check_offset = false); - - // Helper functions for handling operations - void insert_op(LIR_Op* op); - void insert_exchange(int offset); - void insert_exchange(LIR_Opr opr); - void insert_free(int offset); - void insert_free_if_dead(LIR_Opr opr); - void insert_free_if_dead(LIR_Opr opr, LIR_Opr ignore); - void insert_copy(LIR_Opr from, LIR_Opr to); - void do_rename(LIR_Opr from, LIR_Opr to); - void do_push(LIR_Opr opr); - void pop_if_last_use(LIR_Op* op, LIR_Opr opr); - void pop_always(LIR_Op* op, LIR_Opr opr); - void clear_fpu_stack(LIR_Opr preserve); - void handle_op1(LIR_Op1* op1); - void handle_op2(LIR_Op2* op2); - void handle_opCall(LIR_OpCall* opCall); - void compute_debug_information(LIR_Op* op); - void allocate_exception_handler(XHandler* xhandler); - void allocate_block(BlockBegin* block); - -#ifndef PRODUCT - void check_invalid_lir_op(LIR_Op* op); -#endif - - // Helper functions for merging of fpu stacks - void merge_insert_add(LIR_List* instrs, FpuStackSim* cur_sim, int reg); - void merge_insert_xchg(LIR_List* instrs, FpuStackSim* cur_sim, int slot); - void merge_insert_pop(LIR_List* instrs, FpuStackSim* cur_sim); - bool merge_rename(FpuStackSim* cur_sim, FpuStackSim* sux_sim, int start_slot, int change_slot); - void merge_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, FpuStackSim* sux_sim); - void merge_cleanup_fpu_stack(LIR_List* instrs, FpuStackSim* cur_sim, BitMap& live_fpu_regs); - bool merge_fpu_stack_with_successors(BlockBegin* block); - - public: - LIR_Opr to_fpu_stack(LIR_Opr opr); // used by LinearScan for creation of debug information - - FpuStackAllocator(Compilation* compilation, LinearScan* allocator); - void allocate(); -}; - #endif // CPU_X86_C1_LINEARSCAN_X86_HPP diff --git a/src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp index e3c8792decd..238a1bd048a 100644 --- a/src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp +++ b/src/hotspot/cpu/x86/c1_MacroAssembler_x86.cpp @@ -332,12 +332,6 @@ void C1_MacroAssembler::build_frame(int frame_size_in_bytes, int bang_size_in_by if (PreserveFramePointer) { mov(rbp, rsp); } -#if !defined(_LP64) && defined(COMPILER2) - if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) { - // c2 leaves fpu stack dirty. Clean it on entry - empty_FPU_stack(); - } -#endif // !_LP64 && COMPILER2 decrement(rsp, frame_size_in_bytes); // does not emit code for frame_size == 0 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); diff --git a/src/hotspot/share/c1/c1_FpuStackSim.hpp b/src/hotspot/share/c1/c1_FpuStackSim.hpp deleted file mode 100644 index 3fcf1103eb5..00000000000 --- a/src/hotspot/share/c1/c1_FpuStackSim.hpp +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2005, 2019, Oracle and/or its affiliates. All rights reserved. - * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. - * - * This code is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 only, as - * published by the Free Software Foundation. - * - * This code is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * version 2 for more details (a copy is included in the LICENSE file that - * accompanied this code). - * - * You should have received a copy of the GNU General Public License version - * 2 along with this work; if not, write to the Free Software Foundation, - * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA - * or visit www.oracle.com if you need additional information or have any - * questions. - * - */ - -#ifndef SHARE_C1_C1_FPUSTACKSIM_HPP -#define SHARE_C1_C1_FPUSTACKSIM_HPP - -#include "c1/c1_FrameMap.hpp" -#include "utilities/macros.hpp" - -// Provides location for forward declaration of this class, which is -// only implemented on Intel -class FpuStackSim; - -#include CPU_HEADER(c1_FpuStackSim) - -#endif // SHARE_C1_C1_FPUSTACKSIM_HPP diff --git a/src/hotspot/share/c1/c1_Instruction.hpp b/src/hotspot/share/c1/c1_Instruction.hpp index af22d5b8fc9..6b5838f6062 100644 --- a/src/hotspot/share/c1/c1_Instruction.hpp +++ b/src/hotspot/share/c1/c1_Instruction.hpp @@ -1607,7 +1607,6 @@ LEAF(BlockBegin, StateSplit) ResourceBitMap _live_kill; // set of registers defined in this block ResourceBitMap _fpu_register_usage; - intArray* _fpu_stack_state; // For x86 FPU code generation with UseLinearScan int _first_lir_instruction_id; // ID of first LIR instruction in this block int _last_lir_instruction_id; // ID of last LIR instruction in this block @@ -1654,7 +1653,6 @@ LEAF(BlockBegin, StateSplit) , _live_gen() , _live_kill() , _fpu_register_usage() - , _fpu_stack_state(nullptr) , _first_lir_instruction_id(-1) , _last_lir_instruction_id(-1) { @@ -1682,7 +1680,6 @@ LEAF(BlockBegin, StateSplit) ResourceBitMap& live_gen() { return _live_gen; } ResourceBitMap& live_kill() { return _live_kill; } ResourceBitMap& fpu_register_usage() { return _fpu_register_usage; } - intArray* fpu_stack_state() const { return _fpu_stack_state; } int first_lir_instruction_id() const { return _first_lir_instruction_id; } int last_lir_instruction_id() const { return _last_lir_instruction_id; } int total_preds() const { return _total_preds; } @@ -1705,7 +1702,6 @@ LEAF(BlockBegin, StateSplit) void set_live_gen (const ResourceBitMap& map) { _live_gen = map; } void set_live_kill(const ResourceBitMap& map) { _live_kill = map; } void set_fpu_register_usage(const ResourceBitMap& map) { _fpu_register_usage = map; } - void set_fpu_stack_state(intArray* state) { _fpu_stack_state = state; } void set_first_lir_instruction_id(int id) { _first_lir_instruction_id = id; } void set_last_lir_instruction_id(int id) { _last_lir_instruction_id = id; } void increment_total_preds(int n = 1) { _total_preds += n; } diff --git a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp index e11b59cd0a5..e6ba03554cb 100644 --- a/src/hotspot/share/c1/c1_LIR.cpp +++ b/src/hotspot/share/c1/c1_LIR.cpp @@ -403,7 +403,6 @@ void LIR_OpVisitState::visit(LIR_Op* op) { switch (op->code()) { // LIR_Op0 - case lir_fpop_raw: // result and info always invalid case lir_breakpoint: // result and info always invalid case lir_membar: // result and info always invalid case lir_membar_acquire: // result and info always invalid @@ -443,8 +442,6 @@ void LIR_OpVisitState::visit(LIR_Op* op) { // LIR_Op1 - case lir_fxch: // input always valid, result and info always invalid - case lir_fld: // input always valid, result and info always invalid case lir_push: // input always valid, result and info always invalid case lir_pop: // input always valid, result and info always invalid case lir_leal: // input and result always valid, info always invalid @@ -1702,12 +1699,9 @@ const char * LIR_Op::name() const { case lir_on_spin_wait: s = "on_spin_wait"; break; case lir_std_entry: s = "std_entry"; break; case lir_osr_entry: s = "osr_entry"; break; - case lir_fpop_raw: s = "fpop_raw"; break; case lir_breakpoint: s = "breakpoint"; break; case lir_get_thread: s = "get_thread"; break; // LIR_Op1 - case lir_fxch: s = "fxch"; break; - case lir_fld: s = "fld"; break; case lir_push: s = "push"; break; case lir_pop: s = "pop"; break; case lir_null_check: s = "null_check"; break; diff --git a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp index a4e0cc18daa..0de69e658a3 100644 --- a/src/hotspot/share/c1/c1_LIR.hpp +++ b/src/hotspot/share/c1/c1_LIR.hpp @@ -43,7 +43,6 @@ class LIR_Op; class ciType; class ValueType; class LIR_OpVisitState; -class FpuStackSim; //--------------------------------------------------------------------- // LIR Operands @@ -236,9 +235,8 @@ class LIR_Opr { , virtual_bits = 1 , is_xmm_bits = 1 , last_use_bits = 1 - , is_fpu_stack_offset_bits = 1 // used in assertion checking on x86 for FPU stack slot allocation , non_data_bits = kind_bits + type_bits + size_bits + destroys_bits + virtual_bits - + is_xmm_bits + last_use_bits + is_fpu_stack_offset_bits + + is_xmm_bits + last_use_bits , data_bits = BitsPerInt - non_data_bits , reg_bits = data_bits / 2 // for two registers in one value encoding }; @@ -249,8 +247,7 @@ class LIR_Opr { , size_shift = type_shift + type_bits , destroys_shift = size_shift + size_bits , last_use_shift = destroys_shift + destroys_bits - , is_fpu_stack_offset_shift = last_use_shift + last_use_bits - , virtual_shift = is_fpu_stack_offset_shift + is_fpu_stack_offset_bits + , virtual_shift = last_use_shift + last_use_bits , is_xmm_shift = virtual_shift + virtual_bits , data_shift = is_xmm_shift + is_xmm_bits , reg1_shift = data_shift @@ -268,12 +265,11 @@ class LIR_Opr { , type_mask = right_n_bits(type_bits) << type_shift , size_mask = right_n_bits(size_bits) << size_shift , last_use_mask = right_n_bits(last_use_bits) << last_use_shift - , is_fpu_stack_offset_mask = right_n_bits(is_fpu_stack_offset_bits) << is_fpu_stack_offset_shift , virtual_mask = right_n_bits(virtual_bits) << virtual_shift , is_xmm_mask = right_n_bits(is_xmm_bits) << is_xmm_shift , pointer_mask = right_n_bits(pointer_bits) , lower_reg_mask = right_n_bits(reg_bits) - , no_type_mask = (int)(~(type_mask | last_use_mask | is_fpu_stack_offset_mask)) + , no_type_mask = (int)(~(type_mask | last_use_mask)) }; uint32_t data() const { return (uint32_t)value() >> data_shift; } @@ -426,9 +422,7 @@ class LIR_Opr { BasicType type_register() const { assert(is_register() || is_stack(), "type check"); return as_BasicType(type_field_valid()); } bool is_last_use() const { assert(is_register(), "only works for registers"); return (value() & last_use_mask) != 0; } - bool is_fpu_stack_offset() const { assert(is_register(), "only works for registers"); return (value() & is_fpu_stack_offset_mask) != 0; } LIR_Opr make_last_use() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | last_use_mask); } - LIR_Opr make_fpu_stack_offset() { assert(is_register(), "only works for registers"); return (LIR_Opr)(value() | is_fpu_stack_offset_mask); } int single_stack_ix() const { assert(is_single_stack() && !is_virtual(), "type check"); return (int)data(); } @@ -912,7 +906,6 @@ enum LIR_Code { , lir_nop , lir_std_entry , lir_osr_entry - , lir_fpop_raw , lir_breakpoint , lir_rtcall , lir_membar @@ -926,8 +919,6 @@ enum LIR_Code { , lir_on_spin_wait , end_op0 , begin_op1 - , lir_fxch - , lir_fld , lir_push , lir_pop , lir_null_check @@ -1070,7 +1061,6 @@ class LIR_Op: public CompilationResourceObj { unsigned short _flags; CodeEmitInfo* _info; int _id; // value id for register allocation - int _fpu_pop_count; Instruction* _source; // for debugging static void print_condition(outputStream* out, LIR_Condition cond) PRODUCT_RETURN; @@ -1090,7 +1080,6 @@ class LIR_Op: public CompilationResourceObj { , _flags(0) , _info(nullptr) , _id(-1) - , _fpu_pop_count(0) , _source(nullptr) {} LIR_Op(LIR_Code code, LIR_Opr result, CodeEmitInfo* info) @@ -1104,7 +1093,6 @@ class LIR_Op: public CompilationResourceObj { , _flags(0) , _info(info) , _id(-1) - , _fpu_pop_count(0) , _source(nullptr) {} CodeEmitInfo* info() const { return _info; } @@ -1125,11 +1113,6 @@ class LIR_Op: public CompilationResourceObj { int id() const { return _id; } void set_id(int id) { _id = id; } - // FPU stack simulation helpers -- only used on Intel - void set_fpu_pop_count(int count) { assert(count >= 0 && count <= 1, "currently only 0 and 1 are valid"); _fpu_pop_count = count; } - int fpu_pop_count() const { return _fpu_pop_count; } - bool pop_fpu_stack() { return _fpu_pop_count > 0; } - Instruction* source() const { return _source; } void set_source(Instruction* ins) { _source = ins; } diff --git a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp index 4d50a863801..7cf414ae7dc 100644 --- a/src/hotspot/share/c1/c1_LIRAssembler.cpp +++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp @@ -485,19 +485,6 @@ void LIR_Assembler::emit_call(LIR_OpJavaCall* op) { if (op->is_method_handle_invoke()) { compilation()->set_has_method_handle_invokes(true); } - -#if defined(IA32) && defined(COMPILER2) - // C2 leave fpu stack dirty clean it - if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) { - int i; - for ( i = 1; i <= 7 ; i++ ) { - ffree(i); - } - if (!op->result_opr()->is_float_kind()) { - ffree(0); - } - } -#endif // IA32 && COMPILER2 } @@ -514,7 +501,7 @@ void LIR_Assembler::emit_op1(LIR_Op1* op) { volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info()); } else { move_op(op->in_opr(), op->result_opr(), op->type(), - op->patch_code(), op->info(), op->pop_fpu_stack(), + op->patch_code(), op->info(), op->move_kind() == lir_move_wide); } break; @@ -717,14 +704,12 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) { case lir_mul: case lir_div: case lir_rem: - assert(op->fpu_pop_count() < 2, ""); arith_op( op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), - op->info(), - op->fpu_pop_count() == 1); + op->info()); break; case lir_logic_and: @@ -769,16 +754,16 @@ void LIR_Assembler::build_frame() { } -void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) { +void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) { if (src->is_register()) { if (dest->is_register()) { assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here"); reg2reg(src, dest); } else if (dest->is_stack()) { assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here"); - reg2stack(src, dest, type, pop_fpu_stack); + reg2stack(src, dest, type); } else if (dest->is_address()) { - reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide); + reg2mem(src, dest, type, patch_code, info, wide); } else { ShouldNotReachHere(); } diff --git a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp index 5b653b74ef5..a4c5fd61d4c 100644 --- a/src/hotspot/share/c1/c1_LIRAssembler.hpp +++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp @@ -166,11 +166,11 @@ class LIR_Assembler: public CompilationResourceObj { void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); void const2stack(LIR_Opr src, LIR_Opr dest); void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide); - void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); + void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type); void reg2reg (LIR_Opr src, LIR_Opr dest); void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, - bool pop_fpu_stack, bool wide); + bool wide); void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, @@ -206,7 +206,7 @@ class LIR_Assembler: public CompilationResourceObj { void emit_profile_type(LIR_OpProfileType* op); void emit_delay(LIR_OpDelay* op); - void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); + void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info); void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr temp, LIR_Opr dest, LIR_Op* op); #ifdef ASSERT @@ -216,7 +216,7 @@ class LIR_Assembler: public CompilationResourceObj { void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); void move_op(LIR_Opr src, LIR_Opr result, BasicType type, - LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide); + LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide); void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp index b0e2ff28c58..57c592f3506 100644 --- a/src/hotspot/share/c1/c1_LinearScan.cpp +++ b/src/hotspot/share/c1/c1_LinearScan.cpp @@ -91,9 +91,6 @@ LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) , _has_call(0) , _interval_in_loop(0) // initialized later with correct length , _scope_value_cache(0) // initialized later with correct length -#ifdef IA32 - , _fpu_stack_allocator(nullptr) -#endif { assert(this->ir() != nullptr, "check if valid"); assert(this->compilation() != nullptr, "check if valid"); @@ -1868,15 +1865,12 @@ void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveRes int reg = interval->assigned_reg(); int regHi = interval->assigned_regHi(); - if ((reg < nof_regs && interval->always_in_memory()) || - (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { + if ((reg < nof_regs && interval->always_in_memory())) { // the interval is split to get a short range that is located on the stack - // in the following two cases: + // in the following case: // * the interval started in memory (e.g. method parameter), but is currently in a register // this is an optimization for exception handling that reduces the number of moves that // are necessary for resolving the states when an exception uses this exception handler - // * the interval would be on the fpu stack at the begin of the exception handler - // this is not allowed because of the complicated fpu stack handling on Intel // range that will be spilled to memory int from_op_id = block->first_lir_instruction_id(); @@ -2665,17 +2659,9 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArrayis_single_fpu()) { -#ifdef IA32 - // the exact location of fpu stack values is only known - // during fpu stack allocation, so the stack allocator object - // must be present - assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); - assert(_fpu_stack_allocator != nullptr, "must be present"); - opr = _fpu_stack_allocator->to_fpu_stack(opr); -#elif defined(AMD64) +#if defined(AMD64) assert(false, "FPU not used on x86-64"); #endif - Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); #ifndef __SOFTFP__ @@ -2778,16 +2764,6 @@ int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArrayto_fpu_stack(opr); - - assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); -#endif #ifdef AMD64 assert(false, "FPU not used on x86-64"); #endif @@ -3021,15 +2997,9 @@ void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { compute_oop_map(iw, visitor, op); // compute debug information - if (!use_fpu_stack_allocation()) { - // compute debug information if fpu stack allocation is not needed. - // when fpu stack allocation is needed, the debug information can not - // be computed here because the exact location of fpu operands is not known - // -> debug information is created inside the fpu stack allocator - int n = visitor.info_count(); - for (int k = 0; k < n; k++) { - compute_debug_info(visitor.info_at(k), op_id); - } + int n = visitor.info_count(); + for (int k = 0; k < n; k++) { + compute_debug_info(visitor.info_at(k), op_id); } } @@ -3126,14 +3096,6 @@ void LinearScan::do_linear_scan() { NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); - { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); - - if (use_fpu_stack_allocation()) { - allocate_fpu_stack(); // Only has effect on Intel - NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); - } - } - #ifndef RISCV // Disable these optimizations on riscv temporarily, because it does not // work when the comparison operands are bound to branches or cmoves. @@ -6007,20 +5969,6 @@ bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { // these moves are exactly equal and can be optimized return false; } - - } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { - assert(op1->as_Op1() != nullptr, "fxch must be LIR_Op1"); - assert(op2->as_Op1() != nullptr, "fxch must be LIR_Op1"); - LIR_Op1* fxch1 = (LIR_Op1*)op1; - LIR_Op1* fxch2 = (LIR_Op1*)op2; - if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { - // equal FPU stack operations can be optimized - return false; - } - - } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { - // equal FPU stack operations can be optimized - return false; } // no optimization possible @@ -6540,7 +6488,6 @@ const char* LinearScanStatistic::counter_name(int counter_idx) { case counter_throw: return "throw"; case counter_unwind: return "unwind"; case counter_typecheck: return "type+null-checks"; - case counter_fpu_stack: return "fpu-stack"; case counter_misc_inst: return "other instructions"; case counter_other_inst: return "misc. instructions"; @@ -6761,10 +6708,6 @@ void LinearScanStatistic::collect(LinearScan* allocator) { case lir_checkcast: case lir_store_check: inc_counter(counter_typecheck); break; - case lir_fpop_raw: - case lir_fxch: - case lir_fld: inc_counter(counter_fpu_stack); break; - case lir_nop: case lir_push: case lir_pop: @@ -6817,7 +6760,6 @@ const char* LinearScanTimers::timer_name(int idx) { case timer_sort_intervals_after: return "Sort Intervals After"; case timer_eliminate_spill_moves: return "Spill optimization"; case timer_assign_reg_num: return "Assign Reg Num"; - case timer_allocate_fpu_stack: return "Allocate FPU Stack"; case timer_optimize_lir: return "Optimize LIR"; default: ShouldNotReachHere(); return ""; } diff --git a/src/hotspot/share/c1/c1_LinearScan.hpp b/src/hotspot/share/c1/c1_LinearScan.hpp index 4e8adef3c7d..7a56f3e92f4 100644 --- a/src/hotspot/share/c1/c1_LinearScan.hpp +++ b/src/hotspot/share/c1/c1_LinearScan.hpp @@ -25,7 +25,6 @@ #ifndef SHARE_C1_C1_LINEARSCAN_HPP #define SHARE_C1_C1_LINEARSCAN_HPP -#include "c1/c1_FpuStackSim.hpp" #include "c1/c1_FrameMap.hpp" #include "c1/c1_IR.hpp" #include "c1/c1_Instruction.hpp" @@ -177,15 +176,6 @@ class LinearScan : public CompilationResourceObj { int num_loops() const { return ir()->num_loops(); } bool is_interval_in_loop(int interval, int loop) const { return _interval_in_loop.at(interval, loop); } - // handling of fpu stack allocation (platform dependent, needed for debug information generation) -#ifdef IA32 - FpuStackAllocator* _fpu_stack_allocator; - bool use_fpu_stack_allocation() const { return UseSSE < 2 && has_fpu_registers(); } -#else - bool use_fpu_stack_allocation() const { return false; } -#endif - - // access to interval list int interval_count() const { return _intervals.length(); } Interval* interval_at(int reg_num) const { return _intervals.at(reg_num); } @@ -357,12 +347,6 @@ class LinearScan : public CompilationResourceObj { void assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw); void assign_reg_num(); - - // Phase 8: fpu stack allocation - // (Used only on x86 when fpu operands are present) - void allocate_fpu_stack(); - - // helper functions for printing state #ifndef PRODUCT static void print_bitmap(BitMap& bitmap); @@ -953,7 +937,6 @@ class LinearScanTimers : public StackObj { timer_sort_intervals_after, timer_eliminate_spill_moves, timer_assign_reg_num, - timer_allocate_fpu_stack, timer_optimize_lir, number_of_timers diff --git a/src/hotspot/share/c1/c1_globals.hpp b/src/hotspot/share/c1/c1_globals.hpp index 72306585355..ec01bc7a790 100644 --- a/src/hotspot/share/c1/c1_globals.hpp +++ b/src/hotspot/share/c1/c1_globals.hpp @@ -280,12 +280,6 @@ "Maximum size of a compiled method.") \ range(0, 1*M) \ \ - develop(bool, TraceFPUStack, false, \ - "Trace emulation of the FPU stack (intel only)") \ - \ - develop(bool, TraceFPURegisterUsage, false, \ - "Trace usage of FPU registers at start of blocks (intel only)") \ - \ develop(intx, InstructionCountCutoff, 37000, \ "If GraphBuilder adds this many instructions, bails out") \ range(0, max_jint) \