From 240830df7eaa04e0056e9585ebdbf6b02e8b747c Mon Sep 17 00:00:00 2001 From: Hao Sun Date: Tue, 17 Jan 2023 02:07:43 +0000 Subject: [PATCH] 8297092: [macos_aarch64] Add support for SHA feature detection Reviewed-by: njian, aph, gziemski --- .../cpu/aarch64/vm_version_aarch64.cpp | 12 +++-- .../bsd_aarch64/vm_version_bsd_aarch64.cpp | 50 ++++++++++++++----- 2 files changed, 46 insertions(+), 16 deletions(-) diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp index d86d22d7fa7..eaa80bc8fea 100644 --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -342,10 +342,14 @@ void VM_Version::initialize() { } if (UseSHA && VM_Version::supports_sha3()) { - // Do not auto-enable UseSHA3Intrinsics until it has been fully tested on hardware - // if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) { - // FLAG_SET_DEFAULT(UseSHA3Intrinsics, true); - // } + // Auto-enable UseSHA3Intrinsics on hardware with performance benefit. + // Note that the evaluation of UseSHA3Intrinsics shows better performance + // on Apple silicon but worse performance on Neoverse V1 and N2. + if (_cpu == CPU_APPLE) { // Apple silicon + if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) { + FLAG_SET_DEFAULT(UseSHA3Intrinsics, true); + } + } } else if (UseSHA3Intrinsics) { warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU."); FLAG_SET_DEFAULT(UseSHA3Intrinsics, false); diff --git a/src/hotspot/os_cpu/bsd_aarch64/vm_version_bsd_aarch64.cpp b/src/hotspot/os_cpu/bsd_aarch64/vm_version_bsd_aarch64.cpp index 45cd77b3ba5..61af3625619 100644 --- a/src/hotspot/os_cpu/bsd_aarch64/vm_version_bsd_aarch64.cpp +++ b/src/hotspot/os_cpu/bsd_aarch64/vm_version_bsd_aarch64.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006, 2022, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2006, 2023, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, 2019, Red Hat Inc. All rights reserved. * Copyright (c) 2021, Azul Systems, Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. @@ -53,20 +53,46 @@ static bool cpu_has(const char* optional) { void VM_Version::get_os_cpu_info() { size_t sysctllen; - // hw.optional.floatingpoint always returns 1, see - // https://github.com/apple/darwin-xnu/blob/master/bsd/kern/kern_mib.c#L416. - // ID_AA64PFR0_EL1 describes AdvSIMD always equals to FP field. - assert(cpu_has("hw.optional.floatingpoint"), "should be"); - assert(cpu_has("hw.optional.neon"), "should be"); + // cpu_has() uses sysctlbyname function to check the existence of CPU + // features. References: Apple developer document [1] and XNU kernel [2]. + // [1] https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics + // [2] https://github.com/apple-oss-distributions/xnu/blob/main/bsd/kern/kern_mib.c + // + // Note that for some features (e.g., LSE, SHA512 and SHA3) there are two + // parameters for sysctlbyname, which are invented at different times. + // Considering backward compatibility, we check both here. + // + // Floating-point and Advance SIMD features are standard in Apple processors + // beginning with M1 and A7, and don't need to be checked [1]. + // 1) hw.optional.floatingpoint always returns 1 [2]. + // 2) ID_AA64PFR0_EL1 describes AdvSIMD always equals to FP field. + // See the Arm ARM, section "ID_AA64PFR0_EL1, AArch64 Processor Feature + // Register 0". _features = CPU_FP | CPU_ASIMD; - // All Apple-darwin Arm processors have AES and PMULL. - _features |= CPU_AES | CPU_PMULL; + // All Apple-darwin Arm processors have AES, PMULL, SHA1 and SHA2. + // See https://github.com/apple-oss-distributions/xnu/blob/main/osfmk/arm/commpage/commpage.c#L412 + assert(cpu_has("hw.optional.arm.FEAT_AES"), "should be"); + assert(cpu_has("hw.optional.arm.FEAT_PMULL"), "should be"); + assert(cpu_has("hw.optional.arm.FEAT_SHA1"), "should be"); + assert(cpu_has("hw.optional.arm.FEAT_SHA256"), "should be"); + _features |= CPU_AES | CPU_PMULL | CPU_SHA1 | CPU_SHA2; - // Only few features are available via sysctl, see line 614 - // https://opensource.apple.com/source/xnu/xnu-6153.141.1/bsd/kern/kern_mib.c.auto.html - if (cpu_has("hw.optional.armv8_crc32")) _features |= CPU_CRC32; - if (cpu_has("hw.optional.armv8_1_atomics")) _features |= CPU_LSE; + if (cpu_has("hw.optional.armv8_crc32")) { + _features |= CPU_CRC32; + } + if (cpu_has("hw.optional.arm.FEAT_LSE") || + cpu_has("hw.optional.armv8_1_atomics")) { + _features |= CPU_LSE; + } + if (cpu_has("hw.optional.arm.FEAT_SHA512") || + cpu_has("hw.optional.armv8_2_sha512")) { + _features |= CPU_SHA512; + } + if (cpu_has("hw.optional.arm.FEAT_SHA3") || + cpu_has("hw.optional.armv8_2_sha3")) { + _features |= CPU_SHA3; + } int cache_line_size; int hw_conf_cache_line[] = { CTL_HW, HW_CACHELINE };