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https://github.com/openjdk/jdk.git
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8353192: C2: Clean up x86 backend after 32-bit x86 removal
Reviewed-by: kvn, epeter
This commit is contained in:
Aleksey Shipilev
parent
9ee5590328
commit
250eb743c1
@ -43,22 +43,8 @@ void C2SafepointPollStub::emit(C2_MacroAssembler& masm) {
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__ bind(entry());
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InternalAddress safepoint_pc(masm.pc() - masm.offset() + _safepoint_offset);
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#ifdef _LP64
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__ lea(rscratch1, safepoint_pc);
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__ movptr(Address(r15_thread, JavaThread::saved_exception_pc_offset()), rscratch1);
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#else
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const Register tmp1 = rcx;
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const Register tmp2 = rdx;
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__ push(tmp1);
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__ push(tmp2);
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__ lea(tmp1, safepoint_pc);
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__ get_thread(tmp2);
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__ movptr(Address(tmp2, JavaThread::saved_exception_pc_offset()), tmp1);
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__ pop(tmp2);
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__ pop(tmp1);
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#endif
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__ jump(callback_addr);
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}
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@ -107,16 +107,6 @@ void C2_MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool
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movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
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}
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#ifndef _LP64
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// If method sets FPU control word do it now
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if (fp_mode_24b) {
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fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
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}
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if (UseSSE >= 2 && VerifyFPU) {
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verify_FPU(0, "FPU stack must be clean on entry");
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}
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#endif
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#ifdef ASSERT
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if (VerifyStackAtCalls) {
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Label L;
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@ -133,7 +123,6 @@ void C2_MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool
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if (!is_stub) {
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BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
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#ifdef _LP64
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// We put the non-hot code of the nmethod entry barrier out-of-line in a stub.
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Label dummy_slow_path;
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Label dummy_continuation;
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@ -147,10 +136,6 @@ void C2_MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool
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continuation = &stub->continuation();
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}
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bs->nmethod_entry_barrier(this, slow_path, continuation);
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#else
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// Don't bother with out-of-line nmethod entry barrier stub for x86_32.
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bs->nmethod_entry_barrier(this, nullptr /* slow_path */, nullptr /* continuation */);
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#endif
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}
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}
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@ -299,7 +284,7 @@ void C2_MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmp
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// Locked by current thread if difference with current SP is less than one page.
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subptr(tmpReg, rsp);
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// Next instruction set ZFlag == 1 (Success) if difference is less then one page.
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andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - (int)os::vm_page_size())) );
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andptr(tmpReg, (int32_t) (7 - (int)os::vm_page_size()) );
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movptr(Address(boxReg, 0), tmpReg);
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}
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jmp(DONE_LABEL);
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@ -307,10 +292,6 @@ void C2_MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmp
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bind(IsInflated);
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// The object is inflated. tmpReg contains pointer to ObjectMonitor* + markWord::monitor_value
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#ifndef _LP64
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// Just take slow path to avoid dealing with 64 bit atomic instructions here.
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orl(boxReg, 1); // set ICC.ZF=0 to indicate failure
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#else
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// Unconditionally set box->_displaced_header = markWord::unused_mark().
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// Without cast to int32_t this style of movptr will destroy r10 which is typically obj.
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movptr(Address(boxReg, 0), checked_cast<int32_t>(markWord::unused_mark().value()));
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@ -329,7 +310,6 @@ void C2_MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmp
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jccb(Assembler::notEqual, NO_COUNT); // If not recursive, ZF = 0 at this point (fail)
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incq(Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
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xorq(rax, rax); // Set ZF = 1 (success) for recursive lock, denoting locking success
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#endif // _LP64
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bind(DONE_LABEL);
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// ZFlag == 1 count in fast path
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@ -338,10 +318,8 @@ void C2_MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmp
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bind(COUNT);
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if (LockingMode == LM_LEGACY) {
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#ifdef _LP64
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// Count monitors in fast path
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increment(Address(thread, JavaThread::held_monitor_count_offset()));
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#endif
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}
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xorl(tmpReg, tmpReg); // Set ZF == 1
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@ -404,11 +382,6 @@ void C2_MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register t
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// It's inflated.
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#ifndef _LP64
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// Just take slow path to avoid dealing with 64 bit atomic instructions here.
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orl(boxReg, 1); // set ICC.ZF=0 to indicate failure
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jmpb(DONE_LABEL);
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#else
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// Despite our balanced locking property we still check that m->_owner == Self
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// as java routines or native JNI code called by this thread might
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// have released the lock.
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@ -462,7 +435,6 @@ void C2_MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register t
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bind (LSuccess);
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testl (boxReg, 0); // set ICC.ZF=1 to indicate success
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jmpb (DONE_LABEL);
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#endif // _LP64
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if (LockingMode == LM_LEGACY) {
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bind (Stacked);
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@ -482,9 +454,7 @@ void C2_MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register t
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if (LockingMode == LM_LEGACY) {
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// Count monitors in fast path
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#ifdef _LP64
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decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
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#endif
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}
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xorl(tmpReg, tmpReg); // Set ZF == 1
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@ -563,11 +533,6 @@ void C2_MacroAssembler::fast_lock_lightweight(Register obj, Register box, Regist
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{ // Handle inflated monitor.
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bind(inflated);
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#ifndef _LP64
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// Just take slow path to avoid dealing with 64 bit atomic instructions here.
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orl(box, 1); // set ICC.ZF=0 to indicate failure
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jmpb(slow_path);
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#else
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const Register monitor = t;
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if (!UseObjectMonitorTable) {
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@ -633,7 +598,6 @@ void C2_MacroAssembler::fast_lock_lightweight(Register obj, Register box, Regist
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increment(recursions_address);
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bind(monitor_locked);
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#endif // _LP64
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}
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bind(locked);
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@ -746,11 +710,6 @@ void C2_MacroAssembler::fast_unlock_lightweight(Register obj, Register reg_rax,
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bind(inflated);
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#ifndef _LP64
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// Just take slow path to avoid dealing with 64 bit atomic instructions here.
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orl(t, 1); // set ICC.ZF=0 to indicate failure
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jmpb(slow_path);
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#else
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if (!UseObjectMonitorTable) {
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assert(mark == monitor, "should be the same here");
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} else {
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@ -800,7 +759,6 @@ void C2_MacroAssembler::fast_unlock_lightweight(Register obj, Register reg_rax,
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// Recursive unlock.
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bind(recursive);
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decrement(recursions_address);
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#endif // _LP64
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}
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bind(unlocked);
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@ -1522,7 +1480,6 @@ void C2_MacroAssembler::vinsert(BasicType typ, XMMRegister dst, XMMRegister src,
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}
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}
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#ifdef _LP64
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void C2_MacroAssembler::vgather8b_masked_offset(BasicType elem_bt,
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XMMRegister dst, Register base,
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Register idx_base,
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@ -1561,7 +1518,6 @@ void C2_MacroAssembler::vgather8b_masked_offset(BasicType elem_bt,
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}
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}
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}
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#endif // _LP64
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void C2_MacroAssembler::vgather8b_offset(BasicType elem_bt, XMMRegister dst,
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Register base, Register idx_base,
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@ -1633,7 +1589,7 @@ void C2_MacroAssembler::vgather_subword(BasicType elem_ty, XMMRegister dst,
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if (mask == noreg) {
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vgather8b_offset(elem_ty, temp_dst, base, idx_base, offset, rtmp, vlen_enc);
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} else {
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LP64_ONLY(vgather8b_masked_offset(elem_ty, temp_dst, base, idx_base, offset, mask, mask_idx, rtmp, vlen_enc));
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vgather8b_masked_offset(elem_ty, temp_dst, base, idx_base, offset, mask, mask_idx, rtmp, vlen_enc);
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}
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// TEMP_PERM_VEC(temp_dst) = PERMUTE TMP_VEC_64(temp_dst) PERM_INDEX(xtmp1)
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vpermd(temp_dst, xtmp1, temp_dst, vlen_enc == Assembler::AVX_512bit ? vlen_enc : Assembler::AVX_256bit);
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@ -2037,7 +1993,6 @@ void C2_MacroAssembler::reduceI(int opcode, int vlen,
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}
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}
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#ifdef _LP64
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void C2_MacroAssembler::reduceL(int opcode, int vlen,
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Register dst, Register src1, XMMRegister src2,
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XMMRegister vtmp1, XMMRegister vtmp2) {
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@ -2049,7 +2004,6 @@ void C2_MacroAssembler::reduceL(int opcode, int vlen,
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default: assert(false, "wrong vector length");
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}
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}
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#endif // _LP64
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void C2_MacroAssembler::reduceF(int opcode, int vlen, XMMRegister dst, XMMRegister src, XMMRegister vtmp1, XMMRegister vtmp2) {
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switch (vlen) {
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@ -2299,7 +2253,6 @@ void C2_MacroAssembler::reduce32S(int opcode, Register dst, Register src1, XMMRe
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reduce16S(opcode, dst, src1, vtmp1, vtmp1, vtmp2);
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}
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#ifdef _LP64
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void C2_MacroAssembler::reduce2L(int opcode, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2) {
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pshufd(vtmp2, src2, 0xE);
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reduce_operation_128(T_LONG, opcode, vtmp2, src2);
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@ -2325,7 +2278,6 @@ void C2_MacroAssembler::genmask(KRegister dst, Register len, Register temp) {
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bzhiq(temp, temp, len);
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kmovql(dst, temp);
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}
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#endif // _LP64
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void C2_MacroAssembler::reduce2F(int opcode, XMMRegister dst, XMMRegister src, XMMRegister vtmp) {
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reduce_operation_128(T_FLOAT, opcode, dst, src);
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@ -2741,7 +2693,6 @@ void C2_MacroAssembler::vpadd(BasicType elem_bt, XMMRegister dst, XMMRegister sr
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}
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}
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#ifdef _LP64
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void C2_MacroAssembler::vpbroadcast(BasicType elem_bt, XMMRegister dst, Register src, int vlen_enc) {
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assert(UseAVX >= 2, "required");
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bool is_bw = ((elem_bt == T_BYTE) || (elem_bt == T_SHORT));
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@ -2770,7 +2721,6 @@ void C2_MacroAssembler::vpbroadcast(BasicType elem_bt, XMMRegister dst, Register
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}
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}
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}
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#endif
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void C2_MacroAssembler::vconvert_b2x(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vlen_enc) {
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switch (to_elem_bt) {
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@ -3698,7 +3648,7 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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XMMRegister vec1, int ae, KRegister mask) {
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ShortBranchVerifier sbv(this);
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Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
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Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
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Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only AVX3
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int stride, stride2, adr_stride, adr_stride1, adr_stride2;
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int stride2x2 = 0x40;
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Address::ScaleFactor scale = Address::no_scale;
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@ -3768,7 +3718,7 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
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Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
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Label COMPARE_TAIL_LONG;
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Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
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Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only AVX3
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int pcmpmask = 0x19;
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if (ae == StrIntrinsicNode::LL) {
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@ -3838,7 +3788,6 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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// In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
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bind(COMPARE_WIDE_VECTORS_LOOP);
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#ifdef _LP64
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if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
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cmpl(cnt2, stride2x2);
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jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
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@ -3862,8 +3811,6 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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vpxor(vec1, vec1);
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jmpb(COMPARE_WIDE_TAIL);
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}//if (VM_Version::supports_avx512vlbw())
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#endif // _LP64
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bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
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if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
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@ -4032,7 +3979,6 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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}
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jmpb(DONE_LABEL);
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#ifdef _LP64
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if (VM_Version::supports_avx512vlbw()) {
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bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
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@ -4058,7 +4004,6 @@ void C2_MacroAssembler::string_compare(Register str1, Register str2,
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subl(result, cnt1);
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jmpb(POP_LABEL);
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}//if (VM_Version::supports_avx512vlbw())
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#endif // _LP64
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// Discard the stored length difference
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bind(POP_LABEL);
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@ -4133,7 +4078,6 @@ void C2_MacroAssembler::count_positives(Register ary1, Register len,
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// check the tail for absense of negatives
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// ~(~0 << len) applied up to two times (for 32-bit scenario)
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#ifdef _LP64
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{
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Register tmp3_aliased = len;
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mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
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@ -4141,33 +4085,7 @@ void C2_MacroAssembler::count_positives(Register ary1, Register len,
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notq(tmp3_aliased);
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kmovql(mask2, tmp3_aliased);
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}
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#else
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Label k_init;
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jmp(k_init);
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// We could not read 64-bits from a general purpose register thus we move
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// data required to compose 64 1's to the instruction stream
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// We emit 64 byte wide series of elements from 0..63 which later on would
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// be used as a compare targets with tail count contained in tmp1 register.
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// Result would be a k register having tmp1 consecutive number or 1
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// counting from least significant bit.
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address tmp = pc();
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emit_int64(0x0706050403020100);
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emit_int64(0x0F0E0D0C0B0A0908);
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emit_int64(0x1716151413121110);
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emit_int64(0x1F1E1D1C1B1A1918);
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emit_int64(0x2726252423222120);
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emit_int64(0x2F2E2D2C2B2A2928);
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emit_int64(0x3736353433323130);
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emit_int64(0x3F3E3D3C3B3A3938);
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bind(k_init);
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lea(len, InternalAddress(tmp));
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// create mask to test for negative byte inside a vector
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evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
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evpcmpgtb(mask2, vec1, Address(len, 0), Assembler::AVX_512bit);
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#endif
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evpcmpgtb(mask1, mask2, vec2, Address(ary1, 0), Assembler::AVX_512bit);
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ktestq(mask1, mask2);
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jcc(Assembler::zero, DONE);
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@ -4414,7 +4332,6 @@ void C2_MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register
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lea(ary2, Address(ary2, limit, Address::times_1));
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negptr(limit);
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#ifdef _LP64
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if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
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Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
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@ -4451,7 +4368,7 @@ void C2_MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register
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bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
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}//if (VM_Version::supports_avx512vlbw())
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#endif //_LP64
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bind(COMPARE_WIDE_VECTORS);
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vmovdqu(vec1, Address(ary1, limit, scaleFactor));
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if (expand_ary2) {
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@ -4618,8 +4535,6 @@ void C2_MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register
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}
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}
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#ifdef _LP64
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static void convertF2I_slowpath(C2_MacroAssembler& masm, C2GeneralStub<Register, XMMRegister, address>& stub) {
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#define __ masm.
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Register dst = stub.data<0>();
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@ -4666,8 +4581,6 @@ void C2_MacroAssembler::convertF2I(BasicType dst_bt, BasicType src_bt, Register
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bind(stub->continuation());
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}
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#endif // _LP64
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void C2_MacroAssembler::evmasked_op(int ideal_opc, BasicType eType, KRegister mask, XMMRegister dst,
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XMMRegister src1, int imm8, bool merge, int vlen_enc) {
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switch(ideal_opc) {
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@ -5327,7 +5240,6 @@ void C2_MacroAssembler::vector_castD2X_evex(BasicType to_elem_bt, XMMRegister ds
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}
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}
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#ifdef _LP64
|
||||
void C2_MacroAssembler::vector_round_double_evex(XMMRegister dst, XMMRegister src,
|
||||
AddressLiteral double_sign_flip, AddressLiteral new_mxcsr, int vec_enc,
|
||||
Register tmp, XMMRegister xtmp1, XMMRegister xtmp2, KRegister ktmp1, KRegister ktmp2) {
|
||||
@ -5379,7 +5291,6 @@ void C2_MacroAssembler::vector_round_float_avx(XMMRegister dst, XMMRegister src,
|
||||
|
||||
ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), tmp /*rscratch*/);
|
||||
}
|
||||
#endif // _LP64
|
||||
|
||||
void C2_MacroAssembler::vector_unsigned_cast(XMMRegister dst, XMMRegister src, int vlen_enc,
|
||||
BasicType from_elem_bt, BasicType to_elem_bt) {
|
||||
@ -5510,7 +5421,6 @@ void C2_MacroAssembler::evpternlog(XMMRegister dst, int func, KRegister mask, XM
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
void C2_MacroAssembler::vector_long_to_maskvec(XMMRegister dst, Register src, Register rtmp1,
|
||||
Register rtmp2, XMMRegister xtmp, int mask_len,
|
||||
int vec_enc) {
|
||||
@ -5768,7 +5678,6 @@ void C2_MacroAssembler::vector_compress_expand(int opcode, XMMRegister dst, XMMR
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void C2_MacroAssembler::vector_signum_evex(int opcode, XMMRegister dst, XMMRegister src, XMMRegister zero, XMMRegister one,
|
||||
KRegister ktmp1, int vec_enc) {
|
||||
@ -5833,10 +5742,8 @@ void C2_MacroAssembler::vector_maskall_operation(KRegister dst, Register src, in
|
||||
|
||||
void C2_MacroAssembler::vbroadcast(BasicType bt, XMMRegister dst, int imm32, Register rtmp, int vec_enc) {
|
||||
int lane_size = type2aelembytes(bt);
|
||||
bool is_LP64 = LP64_ONLY(true) NOT_LP64(false);
|
||||
if ((is_LP64 || lane_size < 8) &&
|
||||
((is_non_subword_integral_type(bt) && VM_Version::supports_avx512vl()) ||
|
||||
(is_subword_type(bt) && VM_Version::supports_avx512vlbw()))) {
|
||||
if ((is_non_subword_integral_type(bt) && VM_Version::supports_avx512vl()) ||
|
||||
(is_subword_type(bt) && VM_Version::supports_avx512vlbw())) {
|
||||
movptr(rtmp, imm32);
|
||||
switch(lane_size) {
|
||||
case 1 : evpbroadcastb(dst, rtmp, vec_enc); break;
|
||||
@ -5848,7 +5755,7 @@ void C2_MacroAssembler::vbroadcast(BasicType bt, XMMRegister dst, int imm32, Reg
|
||||
}
|
||||
} else {
|
||||
movptr(rtmp, imm32);
|
||||
LP64_ONLY(movq(dst, rtmp)) NOT_LP64(movdl(dst, rtmp));
|
||||
movq(dst, rtmp);
|
||||
switch(lane_size) {
|
||||
case 1 : vpbroadcastb(dst, dst, vec_enc); break;
|
||||
case 2 : vpbroadcastw(dst, dst, vec_enc); break;
|
||||
@ -5983,14 +5890,6 @@ void C2_MacroAssembler::vector_popcount_integral_evex(BasicType bt, XMMRegister
|
||||
}
|
||||
}
|
||||
|
||||
#ifndef _LP64
|
||||
void C2_MacroAssembler::vector_maskall_operation32(KRegister dst, Register src, KRegister tmp, int mask_len) {
|
||||
assert(VM_Version::supports_avx512bw(), "");
|
||||
kmovdl(tmp, src);
|
||||
kunpckdql(dst, tmp, tmp);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Bit reversal algorithm first reverses the bits of each byte followed by
|
||||
// a byte level reversal for multi-byte primitive types (short/int/long).
|
||||
// Algorithm performs a lookup table access to get reverse bit sequence
|
||||
@ -6450,7 +6349,6 @@ void C2_MacroAssembler::udivmodI(Register rax, Register divisor, Register rdx, R
|
||||
bind(done);
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
void C2_MacroAssembler::reverseI(Register dst, Register src, XMMRegister xtmp1,
|
||||
XMMRegister xtmp2, Register rtmp) {
|
||||
if(VM_Version::supports_gfni()) {
|
||||
@ -6614,7 +6512,6 @@ void C2_MacroAssembler::udivmodL(Register rax, Register divisor, Register rdx, R
|
||||
subq(rdx, tmp); // remainder
|
||||
bind(done);
|
||||
}
|
||||
#endif
|
||||
|
||||
void C2_MacroAssembler::rearrange_bytes(XMMRegister dst, XMMRegister shuffle, XMMRegister src, XMMRegister xtmp1,
|
||||
XMMRegister xtmp2, XMMRegister xtmp3, Register rtmp, KRegister ktmp,
|
||||
|
||||
@ -130,9 +130,7 @@ public:
|
||||
|
||||
// Covert B2X
|
||||
void vconvert_b2x(BasicType to_elem_bt, XMMRegister dst, XMMRegister src, int vlen_enc);
|
||||
#ifdef _LP64
|
||||
void vpbroadcast(BasicType elem_bt, XMMRegister dst, Register src, int vlen_enc);
|
||||
#endif
|
||||
|
||||
// blend
|
||||
void evpcmp(BasicType typ, KRegister kdmask, KRegister ksmask, XMMRegister src1, XMMRegister src2, int comparison, int vector_len);
|
||||
@ -152,10 +150,8 @@ public:
|
||||
|
||||
// dst = src1 reduce(op, src2) using vtmp as temps
|
||||
void reduceI(int opcode, int vlen, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
#ifdef _LP64
|
||||
void reduceL(int opcode, int vlen, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
void genmask(KRegister dst, Register len, Register temp);
|
||||
#endif // _LP64
|
||||
|
||||
// dst = reduce(op, src2) using vtmp as temps
|
||||
void reduce_fp(int opcode, int vlen,
|
||||
@ -202,11 +198,9 @@ public:
|
||||
void reduce32S(int opcode, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
|
||||
// Long Reduction
|
||||
#ifdef _LP64
|
||||
void reduce2L(int opcode, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
void reduce4L(int opcode, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
void reduce8L(int opcode, Register dst, Register src1, XMMRegister src2, XMMRegister vtmp1, XMMRegister vtmp2);
|
||||
#endif // _LP64
|
||||
|
||||
// Float Reduction
|
||||
void reduce2F (int opcode, XMMRegister dst, XMMRegister src, XMMRegister vtmp);
|
||||
@ -237,7 +231,6 @@ public:
|
||||
void unordered_reduce_operation_256(BasicType typ, int opcode, XMMRegister dst, XMMRegister src1, XMMRegister src2);
|
||||
|
||||
public:
|
||||
#ifdef _LP64
|
||||
void vector_mask_operation_helper(int opc, Register dst, Register tmp, int masklen);
|
||||
|
||||
void vector_mask_operation(int opc, Register dst, KRegister mask, Register tmp, int masklen, int masksize, int vec_enc);
|
||||
@ -246,14 +239,9 @@ public:
|
||||
Register tmp, int masklen, BasicType bt, int vec_enc);
|
||||
void vector_long_to_maskvec(XMMRegister dst, Register src, Register rtmp1,
|
||||
Register rtmp2, XMMRegister xtmp, int mask_len, int vec_enc);
|
||||
#endif
|
||||
|
||||
void vector_maskall_operation(KRegister dst, Register src, int mask_len);
|
||||
|
||||
#ifndef _LP64
|
||||
void vector_maskall_operation32(KRegister dst, Register src, KRegister ktmp, int mask_len);
|
||||
#endif
|
||||
|
||||
void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
|
||||
XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
|
||||
|
||||
@ -313,9 +301,7 @@ public:
|
||||
void arrays_hashcode_elvload(XMMRegister dst, AddressLiteral src, BasicType eltype);
|
||||
void arrays_hashcode_elvcast(XMMRegister dst, BasicType eltype);
|
||||
|
||||
#ifdef _LP64
|
||||
void convertF2I(BasicType dst_bt, BasicType src_bt, Register dst, XMMRegister src);
|
||||
#endif
|
||||
|
||||
void evmasked_op(int ideal_opc, BasicType eType, KRegister mask,
|
||||
XMMRegister dst, XMMRegister src1, XMMRegister src2,
|
||||
@ -390,7 +376,6 @@ public:
|
||||
|
||||
void vector_mask_cast(XMMRegister dst, XMMRegister src, BasicType dst_bt, BasicType src_bt, int vlen);
|
||||
|
||||
#ifdef _LP64
|
||||
void vector_round_double_evex(XMMRegister dst, XMMRegister src, AddressLiteral double_sign_flip, AddressLiteral new_mxcsr, int vec_enc,
|
||||
Register tmp, XMMRegister xtmp1, XMMRegister xtmp2, KRegister ktmp1, KRegister ktmp2);
|
||||
|
||||
@ -403,13 +388,11 @@ public:
|
||||
void vector_compress_expand_avx2(int opcode, XMMRegister dst, XMMRegister src, XMMRegister mask,
|
||||
Register rtmp, Register rscratch, XMMRegister permv, XMMRegister xtmp,
|
||||
BasicType bt, int vec_enc);
|
||||
#endif // _LP64
|
||||
|
||||
void udivI(Register rax, Register divisor, Register rdx);
|
||||
void umodI(Register rax, Register divisor, Register rdx);
|
||||
void udivmodI(Register rax, Register divisor, Register rdx, Register tmp);
|
||||
|
||||
#ifdef _LP64
|
||||
void reverseI(Register dst, Register src, XMMRegister xtmp1,
|
||||
XMMRegister xtmp2, Register rtmp);
|
||||
void reverseL(Register dst, Register src, XMMRegister xtmp1,
|
||||
@ -417,7 +400,6 @@ public:
|
||||
void udivL(Register rax, Register divisor, Register rdx);
|
||||
void umodL(Register rax, Register divisor, Register rdx);
|
||||
void udivmodL(Register rax, Register divisor, Register rdx, Register tmp);
|
||||
#endif
|
||||
|
||||
void evpternlog(XMMRegister dst, int func, KRegister mask, XMMRegister src2, XMMRegister src3,
|
||||
bool merge, BasicType bt, int vlen_enc);
|
||||
@ -511,10 +493,9 @@ public:
|
||||
Register mask, XMMRegister xtmp1, XMMRegister xtmp2, XMMRegister xtmp3, Register rtmp,
|
||||
Register midx, Register length, int vector_len, int vlen_enc);
|
||||
|
||||
#ifdef _LP64
|
||||
void vgather8b_masked_offset(BasicType elem_bt, XMMRegister dst, Register base, Register idx_base,
|
||||
Register offset, Register mask, Register midx, Register rtmp, int vlen_enc);
|
||||
#endif
|
||||
|
||||
void vgather8b_offset(BasicType elem_bt, XMMRegister dst, Register base, Register idx_base,
|
||||
Register offset, Register rtmp, int vlen_enc);
|
||||
|
||||
|
||||
@ -59,53 +59,34 @@
|
||||
static constexpr bool isSimpleConstant64(jlong value) {
|
||||
// Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
|
||||
//return value == (int) value; // Cf. storeImmL and immL32.
|
||||
|
||||
// Probably always true, even if a temp register is required.
|
||||
#ifdef _LP64
|
||||
return true;
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
// No additional cost for CMOVL.
|
||||
static constexpr int long_cmove_cost() { return 0; }
|
||||
#else
|
||||
// Needs 2 CMOV's for longs.
|
||||
static constexpr int long_cmove_cost() { return 1; }
|
||||
#endif
|
||||
|
||||
#ifdef _LP64
|
||||
// No CMOVF/CMOVD with SSE2
|
||||
static int float_cmove_cost() { return ConditionalMoveLimit; }
|
||||
#else
|
||||
// No CMOVF/CMOVD with SSE/SSE2
|
||||
static int float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
|
||||
#endif
|
||||
|
||||
static bool narrow_oop_use_complex_address() {
|
||||
NOT_LP64(ShouldNotCallThis();)
|
||||
assert(UseCompressedOops, "only for compressed oops code");
|
||||
return (LogMinObjAlignmentInBytes <= 3);
|
||||
}
|
||||
|
||||
static bool narrow_klass_use_complex_address() {
|
||||
NOT_LP64(ShouldNotCallThis();)
|
||||
assert(UseCompressedClassPointers, "only for compressed klass code");
|
||||
return (CompressedKlassPointers::shift() <= 3);
|
||||
}
|
||||
|
||||
// Prefer ConN+DecodeN over ConP.
|
||||
static bool const_oop_prefer_decode() {
|
||||
NOT_LP64(ShouldNotCallThis();)
|
||||
// Prefer ConN+DecodeN over ConP.
|
||||
return true;
|
||||
}
|
||||
|
||||
// Prefer ConP over ConNKlass+DecodeNKlass.
|
||||
static bool const_klass_prefer_decode() {
|
||||
NOT_LP64(ShouldNotCallThis();)
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -123,24 +104,12 @@
|
||||
|
||||
// Are floats converted to double when stored to stack during deoptimization?
|
||||
// On x64 it is stored without conversion so we can use normal access.
|
||||
// On x32 it is stored with conversion only when FPU is used for floats.
|
||||
#ifdef _LP64
|
||||
static constexpr bool float_in_double() {
|
||||
return false;
|
||||
}
|
||||
#else
|
||||
static bool float_in_double() {
|
||||
return (UseSSE == 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
// Do ints take an entire long register or just half?
|
||||
#ifdef _LP64
|
||||
static const bool int_in_long = true;
|
||||
#else
|
||||
static const bool int_in_long = false;
|
||||
#endif
|
||||
|
||||
|
||||
// Does the CPU supports vector variable shift instructions?
|
||||
static bool supports_vector_variable_shifts(void) {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -751,12 +751,11 @@ bool ArchDesc::check_usage() {
|
||||
callback.do_form_by_name("sRegL");
|
||||
|
||||
// special generic vector operands only used in Matcher::pd_specialize_generic_vector_operand
|
||||
// x86_32 combine x86.ad and x86_32.ad, the vec*/legVec* can not be cleaned from IA32
|
||||
#if defined(AARCH64)
|
||||
callback.do_form_by_name("vecA");
|
||||
callback.do_form_by_name("vecD");
|
||||
callback.do_form_by_name("vecX");
|
||||
#elif defined(IA32) || defined(AMD64)
|
||||
#elif defined(AMD64)
|
||||
callback.do_form_by_name("vecS");
|
||||
callback.do_form_by_name("vecD");
|
||||
callback.do_form_by_name("vecX");
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user