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8171398: s390x: Make interpreter's math entries consistent with C1 and C2 and support FMA
Reviewed-by: lucy, goetz
This commit is contained in:
Martin Doerr
parent
b06fa0ea3a
commit
27139d7529
@ -790,6 +790,16 @@ class Assembler : public AbstractAssembler {
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#define MDB_ZOPC (unsigned long)(237L << 40 | 28)
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#define MXDB_ZOPC (unsigned long)(237L << 40 | 7)
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// Multiply-Add
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#define MAEBR_ZOPC (unsigned int)(179 << 24 | 14 << 16)
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#define MADBR_ZOPC (unsigned int)(179 << 24 | 30 << 16)
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#define MSEBR_ZOPC (unsigned int)(179 << 24 | 15 << 16)
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#define MSDBR_ZOPC (unsigned int)(179 << 24 | 31 << 16)
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#define MAEB_ZOPC (unsigned long)(237L << 40 | 14)
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#define MADB_ZOPC (unsigned long)(237L << 40 | 30)
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#define MSEB_ZOPC (unsigned long)(237L << 40 | 15)
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#define MSDB_ZOPC (unsigned long)(237L << 40 | 31)
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// Divide
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// RR, signed
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#define DSGFR_ZOPC (unsigned int)(0xb91d << 16)
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@ -2205,6 +2215,20 @@ class Assembler : public AbstractAssembler {
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inline void z_meeb( FloatRegister f1, const Address& a);
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inline void z_mdb( FloatRegister f1, const Address& a);
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// MUL-ADD
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inline void z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; float
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inline void z_madbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; double
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inline void z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; float
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inline void z_msdbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; double
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inline void z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; float
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inline void z_madb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; double
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inline void z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; float
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inline void z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; double
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inline void z_maeb(FloatRegister f1, FloatRegister f3, const Address& a);
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inline void z_madb(FloatRegister f1, FloatRegister f3, const Address& a);
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inline void z_mseb(FloatRegister f1, FloatRegister f3, const Address& a);
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inline void z_msdb(FloatRegister f1, FloatRegister f3, const Address& a);
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// DIV
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inline void z_debr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; float
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inline void z_ddbr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; double
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@ -777,6 +777,23 @@ inline void Assembler::z_meeb( FloatRegister r1, const Address& a)
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inline void Assembler::z_mdb( FloatRegister r1, const Address& a) { z_mdb( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
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//---------------
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// MUL-ADD
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//---------------
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inline void Assembler::z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2) { emit_32( MAEBR_ZOPC | fregt(f1, 16, 32) | freg(f3, 24, 32) | freg(f2, 28, 32) );}
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inline void Assembler::z_madbr(FloatRegister f1, FloatRegister f3, FloatRegister f2) { emit_32( MADBR_ZOPC | fregt(f1, 16, 32) | freg(f3, 24, 32) | freg(f2, 28, 32) );}
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inline void Assembler::z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister f2) { emit_32( MSEBR_ZOPC | fregt(f1, 16, 32) | freg(f3, 24, 32) | freg(f2, 28, 32) );}
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inline void Assembler::z_msdbr(FloatRegister f1, FloatRegister f3, FloatRegister f2) { emit_32( MSDBR_ZOPC | fregt(f1, 16, 32) | freg(f3, 24, 32) | freg(f2, 28, 32) );}
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inline void Assembler::z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2) { emit_48( MAEB_ZOPC | fregt(f1, 32, 48) | freg(f3, 8, 48) | uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48) );}
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inline void Assembler::z_madb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2) { emit_48( MADB_ZOPC | fregt(f1, 32, 48) | freg(f3, 8, 48) | uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48) );}
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inline void Assembler::z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2) { emit_48( MSEB_ZOPC | fregt(f1, 32, 48) | freg(f3, 8, 48) | uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48) );}
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inline void Assembler::z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2) { emit_48( MSDB_ZOPC | fregt(f1, 32, 48) | freg(f3, 8, 48) | uimm12(d2, 20, 48) | reg(x2, 12, 48) | regz(b2, 16, 48) );}
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inline void Assembler::z_maeb(FloatRegister f1, FloatRegister f3, const Address& a) { z_maeb(f1, f3, a.disp(), a.indexOrR0(), a.baseOrR0()); }
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inline void Assembler::z_madb(FloatRegister f1, FloatRegister f3, const Address& a) { z_madb(f1, f3, a.disp(), a.indexOrR0(), a.baseOrR0()); }
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inline void Assembler::z_mseb(FloatRegister f1, FloatRegister f3, const Address& a) { z_mseb(f1, f3, a.disp(), a.indexOrR0(), a.baseOrR0()); }
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inline void Assembler::z_msdb(FloatRegister f1, FloatRegister f3, const Address& a) { z_msdb(f1, f3, a.disp(), a.indexOrR0(), a.baseOrR0()); }
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//---------------
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// DIV
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//---------------
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@ -324,6 +324,22 @@ void LIR_Assembler::emit_op3(LIR_Op3* op) {
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op->result_opr(),
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op->info());
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break;
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case lir_fmad: {
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const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
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opr2 = op->in_opr2()->as_double_reg(),
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opr3 = op->in_opr3()->as_double_reg(),
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res = op->result_opr()->as_double_reg();
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__ z_madbr(opr3, opr1, opr2);
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if (res != opr3) { __ z_ldr(res, opr3); }
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} break;
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case lir_fmaf: {
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const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
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opr2 = op->in_opr2()->as_float_reg(),
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opr3 = op->in_opr3()->as_float_reg(),
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res = op->result_opr()->as_float_reg();
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__ z_maebr(opr3, opr1, opr2);
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if (res != opr3) { __ z_ler(res, opr3); }
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} break;
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default: ShouldNotReachHere(); break;
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}
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}
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@ -1237,7 +1237,28 @@ void LIRGenerator::do_update_CRC32C(Intrinsic* x) {
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}
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void LIRGenerator::do_FmaIntrinsic(Intrinsic* x) {
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fatal("FMA intrinsic is not implemented on this platform");
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assert(x->number_of_arguments() == 3, "wrong type");
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assert(UseFMA, "Needs FMA instructions support.");
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LIRItem value(x->argument_at(0), this);
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LIRItem value1(x->argument_at(1), this);
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LIRItem value2(x->argument_at(2), this);
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value2.set_destroys_register();
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value.load_item();
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value1.load_item();
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value2.load_item();
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LIR_Opr calc_input = value.result();
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LIR_Opr calc_input1 = value1.result();
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LIR_Opr calc_input2 = value2.result();
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LIR_Opr calc_result = rlock_result(x);
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switch (x->id()) {
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case vmIntrinsics::_fmaD: __ fmad(calc_input, calc_input1, calc_input2, calc_result); break;
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case vmIntrinsics::_fmaF: __ fmaf(calc_input, calc_input1, calc_input2, calc_result); break;
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default: ShouldNotReachHere();
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}
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}
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void LIRGenerator::do_vectorizedMismatch(Intrinsic* x) {
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@ -7249,6 +7249,171 @@ instruct mulD_reg_mem(regD dst, memoryRX src)%{
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ins_pipe(pipe_class_dummy);
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%}
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// Multiply-Accumulate
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// src1 * src2 + dst
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instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
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match(Set dst (FmaF dst (Binary src1 src2)));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_REG_COST);
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size(4);
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format %{ "MAEBR $dst, $src1, $src2" %}
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ins_encode %{
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__ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 + dst
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instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
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match(Set dst (FmaD dst (Binary src1 src2)));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_REG_COST);
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size(4);
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format %{ "MADBR $dst, $src1, $src2" %}
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ins_encode %{
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__ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
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match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_REG_COST);
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size(4);
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format %{ "MSEBR $dst, $src1, $src2" %}
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ins_encode %{
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__ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
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match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_REG_COST);
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size(4);
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format %{ "MSDBR $dst, $src1, $src2" %}
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ins_encode %{
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__ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 + dst
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instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
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match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MAEB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
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Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 + dst
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instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
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match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MADB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
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Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
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match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MSEB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
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Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
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match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MSDB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
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Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 + dst
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instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
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match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MAEB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
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Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 + dst
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instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
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match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
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// CC unchanged by MUL-ADD.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MADB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
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Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
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match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MSEB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
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Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// src1 * src2 - dst
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instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
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match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
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// CC unchanged by MUL-SUB.
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ins_cost(ALU_MEMORY_COST);
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size(6);
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format %{ "MSDB $dst, $src1, $src2" %}
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ins_encode %{
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__ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
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Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
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%}
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ins_pipe(pipe_class_dummy);
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%}
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// DIV
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// Div float single precision
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@ -2038,15 +2038,15 @@ class StubGenerator: public StubCodeGenerator {
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generate_push_parmBlk(keylen, fCode, parmBlk, key, cv, true);
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// Prepare other registers for instruction.
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// __ z_lgr(src, from); // Not needed, registers are the same.
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// __ z_lgr(src, from); // Not needed, registers are the same.
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__ z_lgr(dst, to);
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__ z_lgr(srclen, msglen);
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__ z_llgfr(srclen, msglen); // We pass the offsets as ints, not as longs as required.
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__ kmc(dst, src); // Decipher the message.
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__ kmc(dst, src); // Decipher the message.
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generate_pop_parmBlk(keylen, parmBlk, key, cv);
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__ z_lgr(Z_RET, msglen);
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__ z_llgfr(Z_RET, msglen); // We pass the offsets as ints, not as longs as required.
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__ z_br(Z_R14);
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return __ addr_at(start_off);
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@ -1297,36 +1297,96 @@ void TemplateInterpreterGenerator::generate_fixed_frame(bool native_call) {
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// Math function, frame manager must set up an interpreter state, etc.
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address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::MethodKind kind) {
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if (!InlineIntrinsics) { return NULL; } // Generate a vanilla entry.
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// Decide what to do: Use same platform specific instructions and runtime calls as compilers.
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bool use_instruction = false;
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address runtime_entry = NULL;
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int num_args = 1;
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bool double_precision = true;
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// Only support absolute value and square root.
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if (kind != Interpreter::java_lang_math_abs && kind != Interpreter::java_lang_math_sqrt) {
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return NULL;
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// s390 specific:
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switch (kind) {
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case Interpreter::java_lang_math_sqrt:
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case Interpreter::java_lang_math_abs: use_instruction = true; break;
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case Interpreter::java_lang_math_fmaF:
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case Interpreter::java_lang_math_fmaD: use_instruction = UseFMA; break;
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default: break; // Fall back to runtime call.
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}
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BLOCK_COMMENT("math_entry {");
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switch (kind) {
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case Interpreter::java_lang_math_sin : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dsin); break;
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case Interpreter::java_lang_math_cos : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dcos); break;
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case Interpreter::java_lang_math_tan : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dtan); break;
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case Interpreter::java_lang_math_abs : /* run interpreted */ break;
|
||||
case Interpreter::java_lang_math_sqrt : /* runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dsqrt); not available */ break;
|
||||
case Interpreter::java_lang_math_log : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dlog); break;
|
||||
case Interpreter::java_lang_math_log10: runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dlog10); break;
|
||||
case Interpreter::java_lang_math_pow : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dpow); num_args = 2; break;
|
||||
case Interpreter::java_lang_math_exp : runtime_entry = CAST_FROM_FN_PTR(address, SharedRuntime::dexp); break;
|
||||
case Interpreter::java_lang_math_fmaF : /* run interpreted */ num_args = 3; double_precision = false; break;
|
||||
case Interpreter::java_lang_math_fmaD : /* run interpreted */ num_args = 3; break;
|
||||
default: ShouldNotReachHere();
|
||||
}
|
||||
|
||||
address math_entry = __ pc();
|
||||
// Use normal entry if neither instruction nor runtime call is used.
|
||||
if (!use_instruction && runtime_entry == NULL) return NULL;
|
||||
|
||||
if (kind == Interpreter::java_lang_math_abs) {
|
||||
// Load operand from stack.
|
||||
__ mem2freg_opt(Z_FRET, Address(Z_esp, Interpreter::stackElementSize));
|
||||
__ z_lpdbr(Z_FRET);
|
||||
address entry = __ pc();
|
||||
|
||||
if (use_instruction) {
|
||||
switch (kind) {
|
||||
case Interpreter::java_lang_math_sqrt:
|
||||
// Can use memory operand directly.
|
||||
__ z_sqdb(Z_FRET, Interpreter::stackElementSize, Z_esp);
|
||||
break;
|
||||
case Interpreter::java_lang_math_abs:
|
||||
// Load operand from stack.
|
||||
__ mem2freg_opt(Z_FRET, Address(Z_esp, Interpreter::stackElementSize));
|
||||
__ z_lpdbr(Z_FRET);
|
||||
break;
|
||||
case Interpreter::java_lang_math_fmaF:
|
||||
__ mem2freg_opt(Z_FRET, Address(Z_esp, Interpreter::stackElementSize)); // result reg = arg3
|
||||
__ mem2freg_opt(Z_FARG2, Address(Z_esp, 3 * Interpreter::stackElementSize)); // arg1
|
||||
__ z_maeb(Z_FRET, Z_FARG2, Address(Z_esp, 2 * Interpreter::stackElementSize));
|
||||
break;
|
||||
case Interpreter::java_lang_math_fmaD:
|
||||
__ mem2freg_opt(Z_FRET, Address(Z_esp, Interpreter::stackElementSize)); // result reg = arg3
|
||||
__ mem2freg_opt(Z_FARG2, Address(Z_esp, 5 * Interpreter::stackElementSize)); // arg1
|
||||
__ z_madb(Z_FRET, Z_FARG2, Address(Z_esp, 3 * Interpreter::stackElementSize));
|
||||
break;
|
||||
default: ShouldNotReachHere();
|
||||
}
|
||||
} else {
|
||||
// sqrt
|
||||
// Can use memory operand directly.
|
||||
__ z_sqdb(Z_FRET, Interpreter::stackElementSize, Z_esp);
|
||||
// Load arguments
|
||||
assert(num_args <= 4, "passed in registers");
|
||||
if (double_precision) {
|
||||
int offset = (2 * num_args - 1) * Interpreter::stackElementSize;
|
||||
for (int i = 0; i < num_args; ++i) {
|
||||
__ mem2freg_opt(as_FloatRegister(Z_FARG1->encoding() + 2 * i), Address(Z_esp, offset));
|
||||
offset -= 2 * Interpreter::stackElementSize;
|
||||
}
|
||||
} else {
|
||||
int offset = num_args * Interpreter::stackElementSize;
|
||||
for (int i = 0; i < num_args; ++i) {
|
||||
__ mem2freg_opt(as_FloatRegister(Z_FARG1->encoding() + 2 * i), Address(Z_esp, offset));
|
||||
offset -= Interpreter::stackElementSize;
|
||||
}
|
||||
}
|
||||
// Call runtime
|
||||
__ save_return_pc(); // Save Z_R14.
|
||||
__ push_frame_abi160(0); // Without new frame the RT call could overwrite the saved Z_R14.
|
||||
|
||||
__ call_VM_leaf(runtime_entry);
|
||||
|
||||
__ pop_frame();
|
||||
__ restore_return_pc(); // Restore Z_R14.
|
||||
}
|
||||
|
||||
// Restore caller sp for c2i case.
|
||||
// Pop c2i arguments (if any) off when we return.
|
||||
__ resize_frame_absolute(Z_R10, Z_R0, true); // Cut the stack back to where the caller started.
|
||||
|
||||
// We are done, return.
|
||||
__ z_br(Z_R14);
|
||||
|
||||
BLOCK_COMMENT("} math_entry");
|
||||
|
||||
return math_entry;
|
||||
return entry;
|
||||
}
|
||||
|
||||
// Interpreter stub for calling a native method. (asm interpreter).
|
||||
|
||||
@ -155,9 +155,8 @@ void VM_Version::initialize() {
|
||||
FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
|
||||
}
|
||||
|
||||
if (UseFMA) {
|
||||
warning("FMA instructions are not available on this CPU");
|
||||
FLAG_SET_DEFAULT(UseFMA, false);
|
||||
if (FLAG_IS_DEFAULT(UseFMA)) {
|
||||
FLAG_SET_DEFAULT(UseFMA, true);
|
||||
}
|
||||
|
||||
// On z/Architecture, we take UseSHA as the general switch to enable/disable the SHA intrinsics.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user