diff --git a/src/hotspot/cpu/ppc/icache_ppc.cpp b/src/hotspot/cpu/ppc/icache_ppc.cpp index 05ad3c7a30d..f3d51bad18c 100644 --- a/src/hotspot/cpu/ppc/icache_ppc.cpp +++ b/src/hotspot/cpu/ppc/icache_ppc.cpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 SAP SE. All rights reserved. + * Copyright (c) 2000, 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2026 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -24,6 +24,7 @@ */ #include "runtime/icache.hpp" +#include "runtime/vm_version.hpp" // Use inline assembler to implement icache flush. int ICache::ppc64_flush_icache(address start, int lines, int magic) { @@ -67,6 +68,9 @@ int ICache::ppc64_flush_icache(address start, int lines, int magic) { void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) { + guarantee(VM_Version::get_icache_line_size() >= ICache::line_size, + "processors with smaller cache line size are no longer supported"); + *flush_icache_stub = (ICache::flush_icache_stub_t)ICache::ppc64_flush_icache; // First call to flush itself. diff --git a/src/hotspot/cpu/ppc/icache_ppc.hpp b/src/hotspot/cpu/ppc/icache_ppc.hpp index d348cad1c72..024f706182a 100644 --- a/src/hotspot/cpu/ppc/icache_ppc.hpp +++ b/src/hotspot/cpu/ppc/icache_ppc.hpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 2002, 2023, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2013 SAP SE. All rights reserved. + * Copyright (c) 2002, 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2026 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -35,9 +35,8 @@ class ICache : public AbstractICache { public: enum { - // Actually, cache line size is 64, but keeping it as it is to be - // on the safe side on ALL PPC64 implementations. - log2_line_size = 5, + // Cache line size is 128 on all supported PPC64 implementations. + log2_line_size = 7, line_size = 1 << log2_line_size }; diff --git a/src/hotspot/cpu/ppc/vm_version_ppc.cpp b/src/hotspot/cpu/ppc/vm_version_ppc.cpp index 75feb389298..e471f5a6e4f 100644 --- a/src/hotspot/cpu/ppc/vm_version_ppc.cpp +++ b/src/hotspot/cpu/ppc/vm_version_ppc.cpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2025 SAP SE. All rights reserved. + * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2026 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -475,19 +475,12 @@ void VM_Version::print_features() { void VM_Version::determine_features() { #if defined(ABI_ELFv2) - // 1 InstWord per call for the blr instruction. - const int code_size = (num_features+1+2*1)*BytesPerInstWord; + const int code_size = (num_features + 1 /*blr*/) * BytesPerInstWord; #else - // 7 InstWords for each call (function descriptor + blr instruction). - const int code_size = (num_features+1+2*7)*BytesPerInstWord; + const int code_size = (num_features + 1 /*blr*/ + 6 /* fd */) * BytesPerInstWord; #endif int features = 0; - // create test area - enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). - char test_area[BUFFER_SIZE]; - char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; - // Allocate space for the code. ResourceMark rm; CodeBuffer cb("detect_cpu_features", code_size, 0); @@ -497,20 +490,13 @@ void VM_Version::determine_features() { _features = VM_Version::all_features_m; // Emit code. - void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); + void (*test)() = (void(*)())(void *)a->function_entry(); uint32_t *code = (uint32_t *)a->pc(); - // Keep R3_ARG1 unmodified, it contains &field (see below). - // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). a->mfdscr(R0); a->darn(R7); a->brw(R5, R6); a->blr(); - // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. - void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); - a->dcbz(R3_ARG1); // R3_ARG1 = addr - a->blr(); - uint32_t *code_end = (uint32_t *)a->pc(); a->flush(); _features = VM_Version::unknown_m; @@ -522,18 +508,9 @@ void VM_Version::determine_features() { Disassembler::decode((u_char*)code, (u_char*)code_end, tty); } - // Measure cache line size. - memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. - (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. - int count = 0; // count zeroed bytes - for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; - guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); - _L1_data_cache_line_size = count; - // Execute code. Illegal instructions will be replaced by 0 in the signal handler. VM_Version::_is_determine_features_test_running = true; - // We must align the first argument to 16 bytes because of the lqarx check. - (*test)(align_up((address)mid_of_test_area, 16), 0); + (*test)(); VM_Version::_is_determine_features_test_running = false; // determine which instructions are legal. @@ -550,6 +527,10 @@ void VM_Version::determine_features() { } _features = features; + + _L1_data_cache_line_size = VM_Version::get_dcache_line_size(); + assert(_L1_data_cache_line_size >= DEFAULT_CACHE_LINE_SIZE, + "processors with smaller cache line size are no longer supported"); } // Power 8: Configure Data Stream Control Register. diff --git a/src/hotspot/cpu/ppc/vm_version_ppc.hpp b/src/hotspot/cpu/ppc/vm_version_ppc.hpp index 11dce83bed0..0f4eb3593a3 100644 --- a/src/hotspot/cpu/ppc/vm_version_ppc.hpp +++ b/src/hotspot/cpu/ppc/vm_version_ppc.hpp @@ -1,6 +1,6 @@ /* - * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2025 SAP SE. All rights reserved. + * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2012, 2026 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it @@ -81,6 +81,9 @@ public: static uint64_t _dscr_val; static void initialize_cpu_information(void); + + static int get_dcache_line_size(); + static int get_icache_line_size(); }; #endif // CPU_PPC_VM_VERSION_PPC_HPP diff --git a/src/hotspot/os_cpu/aix_ppc/vm_version_aix_ppc.cpp b/src/hotspot/os_cpu/aix_ppc/vm_version_aix_ppc.cpp new file mode 100644 index 00000000000..8cc8b715201 --- /dev/null +++ b/src/hotspot/os_cpu/aix_ppc/vm_version_aix_ppc.cpp @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2026 SAP SE. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "runtime/vm_version.hpp" + +#include + +int VM_Version::get_dcache_line_size() { + return _system_configuration.dcache_line; +} + +int VM_Version::get_icache_line_size() { + return _system_configuration.icache_line; +} diff --git a/src/hotspot/os_cpu/linux_ppc/vm_version_linux_ppc.cpp b/src/hotspot/os_cpu/linux_ppc/vm_version_linux_ppc.cpp new file mode 100644 index 00000000000..d64340edf5c --- /dev/null +++ b/src/hotspot/os_cpu/linux_ppc/vm_version_linux_ppc.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2026, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2026 SAP SE. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "runtime/vm_version.hpp" + +#include + +int VM_Version::get_dcache_line_size() { + // This should work on all modern linux versions: + int size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); + // It may fail with very old linux / glibc versions. We use DEFAULT_CACHE_LINE_SIZE in this case. + // That is the correct value for all currently supported processors. + return (size <= 0) ? DEFAULT_CACHE_LINE_SIZE : size; +} + +int VM_Version::get_icache_line_size() { + // This should work on all modern linux versions: + int size = sysconf(_SC_LEVEL1_ICACHE_LINESIZE); + // It may fail with very old linux / glibc versions. We use DEFAULT_CACHE_LINE_SIZE in this case. + // That is the correct value for all currently supported processors. + return (size <= 0) ? DEFAULT_CACHE_LINE_SIZE : size; +}