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https://github.com/openjdk/jdk.git
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8288478: AArch64: Clean up whitespace in assembler_aarch64.hpp
Reviewed-by: shade
This commit is contained in:
Andrew Haley
parent
ce5024f66f
commit
2cf7c01759
@ -768,7 +768,7 @@ public:
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INSN(andw, 0b000, true);
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INSN(orrw, 0b001, true);
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INSN(eorw, 0b010, true);
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INSN(andr, 0b100, false);
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INSN(andr, 0b100, false);
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INSN(orr, 0b101, false);
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INSN(eor, 0b110, false);
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@ -794,15 +794,15 @@ public:
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starti; \
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f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
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f(imm, 20, 5); \
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zrf(Rd, 0); \
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zrf(Rd, 0); \
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}
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INSN(movnw, 0b000);
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INSN(movzw, 0b010);
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INSN(movkw, 0b011);
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INSN(movn, 0b100);
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INSN(movz, 0b110);
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INSN(movk, 0b111);
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INSN(movn, 0b100);
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INSN(movz, 0b110);
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INSN(movk, 0b111);
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#undef INSN
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@ -1104,12 +1104,12 @@ public:
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rf(RM, 0);
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}
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#define INSN(NAME, opc) \
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void NAME(Register RN) { \
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branch_reg(opc, 0, 0, RN, r0); \
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#define INSN(NAME, opc) \
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void NAME(Register RN) { \
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branch_reg(opc, 0, 0, RN, r0); \
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}
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INSN(br, 0b0000);
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INSN(br, 0b0000);
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INSN(blr, 0b0001);
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INSN(ret, 0b0010);
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@ -1117,9 +1117,9 @@ public:
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#undef INSN
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#define INSN(NAME, opc) \
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void NAME() { \
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branch_reg(opc, 0, 0, dummy_reg, r0); \
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#define INSN(NAME, opc) \
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void NAME() { \
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branch_reg(opc, 0, 0, dummy_reg, r0); \
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}
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INSN(eret, 0b0100);
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@ -1208,44 +1208,46 @@ public:
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}
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// bytes
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INSN3(stxrb, byte, 0b000, 0);
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INSN3(stxrb, byte, 0b000, 0);
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INSN3(stlxrb, byte, 0b000, 1);
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INSN2(ldxrb, byte, 0b010, 0);
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INSN2(ldxrb, byte, 0b010, 0);
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INSN2(ldaxrb, byte, 0b010, 1);
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INSN2(stlrb, byte, 0b100, 1);
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INSN2(ldarb, byte, 0b110, 1);
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INSN2(stlrb, byte, 0b100, 1);
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INSN2(ldarb, byte, 0b110, 1);
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// halfwords
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INSN3(stxrh, halfword, 0b000, 0);
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INSN3(stxrh, halfword, 0b000, 0);
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INSN3(stlxrh, halfword, 0b000, 1);
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INSN2(ldxrh, halfword, 0b010, 0);
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INSN2(ldxrh, halfword, 0b010, 0);
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INSN2(ldaxrh, halfword, 0b010, 1);
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INSN2(stlrh, halfword, 0b100, 1);
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INSN2(ldarh, halfword, 0b110, 1);
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INSN2(stlrh, halfword, 0b100, 1);
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INSN2(ldarh, halfword, 0b110, 1);
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// words
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INSN3(stxrw, word, 0b000, 0);
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INSN3(stxrw, word, 0b000, 0);
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INSN3(stlxrw, word, 0b000, 1);
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INSN4(stxpw, word, 0b001, 0);
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INSN4(stxpw, word, 0b001, 0);
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INSN4(stlxpw, word, 0b001, 1);
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INSN2(ldxrw, word, 0b010, 0);
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INSN2(ldxrw, word, 0b010, 0);
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INSN2(ldaxrw, word, 0b010, 1);
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INSN_FOO(ldxpw, word, 0b011, 0);
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INSN2(stlrw, word, 0b100, 1);
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INSN2(ldarw, word, 0b110, 1);
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// pairs of words
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INSN_FOO(ldxpw, word, 0b011, 0);
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INSN_FOO(ldaxpw, word, 0b011, 1);
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INSN2(stlrw, word, 0b100, 1);
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INSN2(ldarw, word, 0b110, 1);
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// xwords
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INSN3(stxr, xword, 0b000, 0);
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INSN3(stxr, xword, 0b000, 0);
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INSN3(stlxr, xword, 0b000, 1);
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INSN4(stxp, xword, 0b001, 0);
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INSN4(stxp, xword, 0b001, 0);
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INSN4(stlxp, xword, 0b001, 1);
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INSN2(ldxr, xword, 0b010, 0);
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INSN2(ldxr, xword, 0b010, 0);
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INSN2(ldaxr, xword, 0b010, 1);
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INSN_FOO(ldxp, xword, 0b011, 0);
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INSN2(stlr, xword, 0b100, 1);
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INSN2(ldar, xword, 0b110, 1);
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// pairs of xwords
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INSN_FOO(ldxp, xword, 0b011, 0);
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INSN_FOO(ldaxp, xword, 0b011, 1);
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INSN2(stlr, xword, 0b100, 1);
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INSN2(ldar, xword, 0b110, 1);
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#undef INSN2
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#undef INSN3
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@ -1271,10 +1273,10 @@ public:
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assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \
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lse_cas(Rs, Rt, Rn, sz, a, r, true); \
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}
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INSN(cas, false, false)
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INSN(casa, true, false)
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INSN(casl, false, true)
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INSN(casal, true, true)
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INSN(cas, false, false)
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INSN(casa, true, false)
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INSN(casl, false, true)
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INSN(casal, true, true)
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#undef INSN
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// CASP
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@ -1286,10 +1288,10 @@ public:
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Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \
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lse_cas(Rs, Rt, Rn, sz, a, r, false); \
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}
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INSN(casp, false, false)
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INSN(caspa, true, false)
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INSN(caspl, false, true)
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INSN(caspal, true, true)
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INSN(casp, false, false)
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INSN(caspa, true, false)
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INSN(caspl, false, true)
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INSN(caspal, true, true)
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#undef INSN
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// 8.1 Atomic operations
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@ -1415,17 +1417,17 @@ public:
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ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
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}
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INSN(stpw, 0b00, 0b101, 0, 0, false);
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INSN(ldpw, 0b00, 0b101, 0, 1, false);
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INSN(stpw, 0b00, 0b101, 0, 0, false);
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INSN(ldpw, 0b00, 0b101, 0, 1, false);
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INSN(ldpsw, 0b01, 0b101, 0, 1, false);
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INSN(stp, 0b10, 0b101, 0, 0, false);
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INSN(ldp, 0b10, 0b101, 0, 1, false);
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INSN(stp, 0b10, 0b101, 0, 0, false);
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INSN(ldp, 0b10, 0b101, 0, 1, false);
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// Load/store no-allocate pair (offset)
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INSN(stnpw, 0b00, 0b101, 0, 0, true);
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INSN(ldnpw, 0b00, 0b101, 0, 1, true);
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INSN(stnp, 0b10, 0b101, 0, 0, true);
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INSN(ldnp, 0b10, 0b101, 0, 1, true);
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INSN(stnp, 0b10, 0b101, 0, 0, true);
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INSN(ldnp, 0b10, 0b101, 0, 1, true);
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#undef INSN
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@ -1475,21 +1477,21 @@ public:
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ld_st2(Rt, adr, size, op); \
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} \
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INSN(str, 0b11, 0b00);
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INSN(str, 0b11, 0b00);
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INSN(strw, 0b10, 0b00);
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INSN(strb, 0b00, 0b00);
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INSN(strh, 0b01, 0b00);
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INSN(ldr, 0b11, 0b01);
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INSN(ldr, 0b11, 0b01);
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INSN(ldrw, 0b10, 0b01);
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INSN(ldrb, 0b00, 0b01);
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INSN(ldrh, 0b01, 0b01);
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INSN(ldrsb, 0b00, 0b10);
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INSN(ldrsb, 0b00, 0b10);
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INSN(ldrsbw, 0b00, 0b11);
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INSN(ldrsh, 0b01, 0b10);
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INSN(ldrsh, 0b01, 0b10);
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INSN(ldrshw, 0b01, 0b11);
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INSN(ldrsw, 0b10, 0b10);
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INSN(ldrsw, 0b10, 0b10);
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#undef INSN
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@ -1569,13 +1571,13 @@ public:
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op_shifted_reg(current_insn, 0b01010, kind, shift, size, op); \
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}
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INSN(andr, 1, 0b00, 0);
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INSN(orr, 1, 0b01, 0);
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INSN(eor, 1, 0b10, 0);
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INSN(ands, 1, 0b11, 0);
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INSN(andw, 0, 0b00, 0);
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INSN(orrw, 0, 0b01, 0);
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INSN(eorw, 0, 0b10, 0);
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INSN(andr, 1, 0b00, 0);
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INSN(orr, 1, 0b01, 0);
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INSN(eor, 1, 0b10, 0);
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INSN(ands, 1, 0b11, 0);
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INSN(andw, 0, 0b00, 0);
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INSN(orrw, 0, 0b01, 0);
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INSN(eorw, 0, 0b10, 0);
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INSN(andsw, 0, 0b11, 0);
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#undef INSN
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@ -1597,13 +1599,13 @@ public:
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assert(false, " can't be used with immediate operand"); \
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}
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INSN(bic, 1, 0b00, 1);
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INSN(orn, 1, 0b01, 1);
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INSN(eon, 1, 0b10, 1);
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INSN(bics, 1, 0b11, 1);
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INSN(bicw, 0, 0b00, 1);
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INSN(ornw, 0, 0b01, 1);
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INSN(eonw, 0, 0b10, 1);
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INSN(bic, 1, 0b00, 1);
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INSN(orn, 1, 0b01, 1);
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INSN(eon, 1, 0b10, 1);
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INSN(bics, 1, 0b11, 1);
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INSN(bicw, 0, 0b00, 1);
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INSN(ornw, 0, 0b01, 1);
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INSN(eonw, 0, 0b10, 1);
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INSN(bicsw, 0, 0b11, 1);
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#undef INSN
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@ -1636,13 +1638,13 @@ void mvnw(Register Rd, Register Rm,
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op_shifted_reg(current_insn, 0b01011, kind, shift, size, op); \
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}
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INSN(add, 1, 0b000);
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INSN(sub, 1, 0b10);
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INSN(add, 1, 0b000);
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INSN(sub, 1, 0b10);
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INSN(addw, 0, 0b000);
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INSN(subw, 0, 0b10);
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INSN(adds, 1, 0b001);
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INSN(subs, 1, 0b11);
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INSN(adds, 1, 0b001);
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INSN(subs, 1, 0b11);
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INSN(addsw, 0, 0b001);
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INSN(subsw, 0, 0b11);
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@ -1667,8 +1669,8 @@ void mvnw(Register Rd, Register Rm,
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INSN(addw, 0b000);
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INSN(subw, 0b010);
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INSN(add, 0b100);
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INSN(sub, 0b110);
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INSN(add, 0b100);
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INSN(sub, 0b110);
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#undef INSN
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@ -1682,8 +1684,8 @@ void mvnw(Register Rd, Register Rm,
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INSN(addsw, 0b001);
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INSN(subsw, 0b011);
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INSN(adds, 0b101);
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INSN(subs, 0b111);
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INSN(adds, 0b101);
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INSN(subs, 0b111);
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#undef INSN
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@ -1722,14 +1724,14 @@ void mvnw(Register Rd, Register Rm,
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add_sub_carry(op, Rd, Rn, Rm); \
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}
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INSN(adcw, 0b000);
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INSN(adcw, 0b000);
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INSN(adcsw, 0b001);
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INSN(sbcw, 0b010);
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INSN(sbcw, 0b010);
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INSN(sbcsw, 0b011);
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INSN(adc, 0b100);
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INSN(adcs, 0b101);
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INSN(sbc,0b110);
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INSN(sbcs, 0b111);
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INSN(adc, 0b100);
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INSN(adcs, 0b101);
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INSN(sbc, 0b110);
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INSN(sbcs, 0b111);
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#undef INSN
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@ -1782,14 +1784,14 @@ void mvnw(Register Rd, Register Rm,
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conditional_select(op, op2, Rd, Rn, Rm, cond); \
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}
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INSN(cselw, 0b000, 0b00);
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INSN(cselw, 0b000, 0b00);
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INSN(csincw, 0b000, 0b01);
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INSN(csinvw, 0b010, 0b00);
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INSN(csnegw, 0b010, 0b01);
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INSN(csel, 0b100, 0b00);
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INSN(csinc, 0b100, 0b01);
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INSN(csinv, 0b110, 0b00);
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INSN(csneg, 0b110, 0b01);
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INSN(csel, 0b100, 0b00);
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INSN(csinc, 0b100, 0b01);
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INSN(csinv, 0b110, 0b00);
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INSN(csneg, 0b110, 0b01);
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#undef INSN
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@ -1855,7 +1857,7 @@ void mvnw(Register Rd, Register Rm,
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#undef INSN
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// (2 sources)
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// Data-processing (2 source)
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#define INSN(NAME, op29, opcode) \
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void NAME(Register Rd, Register Rn, Register Rm) { \
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starti; \
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@ -1879,7 +1881,7 @@ void mvnw(Register Rd, Register Rm,
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#undef INSN
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// (3 sources)
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// Data-processing (3 source)
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void data_processing(unsigned op54, unsigned op31, unsigned o0,
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Register Rd, Register Rn, Register Rm,
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Register Ra) {
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@ -1894,10 +1896,10 @@ void mvnw(Register Rd, Register Rm,
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data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
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}
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INSN(maddw, 0b000, 0b000, 0);
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INSN(msubw, 0b000, 0b000, 1);
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INSN(madd, 0b100, 0b000, 0);
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INSN(msub, 0b100, 0b000, 1);
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INSN(maddw, 0b000, 0b000, 0);
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INSN(msubw, 0b000, 0b000, 1);
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INSN(madd, 0b100, 0b000, 0);
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INSN(msub, 0b100, 0b000, 1);
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INSN(smaddl, 0b100, 0b001, 0);
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INSN(smsubl, 0b100, 0b001, 1);
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INSN(umaddl, 0b100, 0b101, 0);
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@ -1930,17 +1932,17 @@ void mvnw(Register Rd, Register Rm,
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data_processing(op31, type, opcode, Vd, Vn); \
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}
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INSN(fmovs, 0b000, 0b00, 0b000000);
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INSN(fabss, 0b000, 0b00, 0b000001);
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INSN(fnegs, 0b000, 0b00, 0b000010);
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INSN(fmovs, 0b000, 0b00, 0b000000);
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INSN(fabss, 0b000, 0b00, 0b000001);
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INSN(fnegs, 0b000, 0b00, 0b000010);
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INSN(fsqrts, 0b000, 0b00, 0b000011);
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INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
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INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
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INSN(fmovd, 0b000, 0b01, 0b000000);
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INSN(fabsd, 0b000, 0b01, 0b000001);
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INSN(fnegd, 0b000, 0b01, 0b000010);
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INSN(fmovd, 0b000, 0b01, 0b000000);
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INSN(fabsd, 0b000, 0b01, 0b000001);
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INSN(fnegd, 0b000, 0b01, 0b000010);
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INSN(fsqrtd, 0b000, 0b01, 0b000011);
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INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
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INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
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private:
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void _fcvt_narrow_extend(FloatRegister Vd, SIMD_Arrangement Ta,
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@ -2020,15 +2022,15 @@ public:
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data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
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}
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INSN(fmadds, 0b000, 0b00, 0, 0);
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INSN(fmsubs, 0b000, 0b00, 0, 1);
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INSN(fmadds, 0b000, 0b00, 0, 0);
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INSN(fmsubs, 0b000, 0b00, 0, 1);
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INSN(fnmadds, 0b000, 0b00, 1, 0);
|
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INSN(fnmsubs, 0b000, 0b00, 1, 1);
|
||||
|
||||
INSN(fmaddd, 0b000, 0b01, 0, 0);
|
||||
INSN(fmsubd, 0b000, 0b01, 0, 1);
|
||||
INSN(fmaddd, 0b000, 0b01, 0, 0);
|
||||
INSN(fmsubd, 0b000, 0b01, 0, 1);
|
||||
INSN(fnmaddd, 0b000, 0b01, 1, 0);
|
||||
INSN(fnmsub, 0b000, 0b01, 1, 1);
|
||||
INSN(fnmsub, 0b000, 0b01, 1, 1);
|
||||
|
||||
#undef INSN
|
||||
|
||||
@ -2058,7 +2060,7 @@ public:
|
||||
|
||||
#undef INSN
|
||||
|
||||
// Floating-point<->integer conversions
|
||||
// Conversion between floating-point and integer
|
||||
void float_int_convert(unsigned sflag, unsigned ftype,
|
||||
unsigned rmode, unsigned opcode,
|
||||
Register Rd, Register Rn) {
|
||||
@ -2096,9 +2098,9 @@ public:
|
||||
|
||||
#undef INSN
|
||||
|
||||
#define INSN(NAME, sflag, type, rmode, opcode) \
|
||||
#define INSN(NAME, sflag, type, rmode, opcode) \
|
||||
void NAME(FloatRegister Vd, Register Rn) { \
|
||||
float_int_convert(sflag, type, rmode, opcode, as_Register(Vd), Rn); \
|
||||
float_int_convert(sflag, type, rmode, opcode, as_Register(Vd), Rn); \
|
||||
}
|
||||
|
||||
INSN(fmovs, 0b0, 0b00, 0b00, 0b111);
|
||||
@ -2228,6 +2230,8 @@ public:
|
||||
movi(Vn, T1D, 0);
|
||||
}
|
||||
|
||||
// Floating-point data-processing (1 source)
|
||||
|
||||
// Floating-point rounding
|
||||
// type: half-precision = 11
|
||||
// single = 00
|
||||
@ -2415,6 +2419,7 @@ public:
|
||||
|
||||
#undef INSN
|
||||
|
||||
// Advanced SIMD three different
|
||||
#define INSN(NAME, opc, opc2, acceptT2D) \
|
||||
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
|
||||
guarantee(T != T1Q && T != T1D, "incorrect arrangement"); \
|
||||
@ -2656,9 +2661,9 @@ public:
|
||||
f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
|
||||
}
|
||||
|
||||
INSN(aese, 0b0100111000101000010010);
|
||||
INSN(aesd, 0b0100111000101000010110);
|
||||
INSN(aesmc, 0b0100111000101000011010);
|
||||
INSN(aese, 0b0100111000101000010010);
|
||||
INSN(aesd, 0b0100111000101000010110);
|
||||
INSN(aesmc, 0b0100111000101000011010);
|
||||
INSN(aesimc, 0b0100111000101000011110);
|
||||
|
||||
#undef INSN
|
||||
@ -3114,25 +3119,25 @@ public:
|
||||
sve_predicate_reg_insn(op1, op2, Zdn_or_Zd_or_Vd, T, Pg, Znm_or_Vn); \
|
||||
}
|
||||
|
||||
INSN(sve_abs, 0b00000100, 0b010110101); // vector abs, unary
|
||||
INSN(sve_add, 0b00000100, 0b000000000); // vector add
|
||||
INSN(sve_and, 0b00000100, 0b011010000); // vector and
|
||||
INSN(sve_andv, 0b00000100, 0b011010001); // bitwise and reduction to scalar
|
||||
INSN(sve_asr, 0b00000100, 0b010000100); // vector arithmetic shift right
|
||||
INSN(sve_bic, 0b00000100, 0b011011000); // vector bitwise clear
|
||||
INSN(sve_clz, 0b00000100, 0b011001101); // vector count leading zero bits
|
||||
INSN(sve_cnt, 0b00000100, 0b011010101); // count non-zero bits
|
||||
INSN(sve_cpy, 0b00000101, 0b100000100); // copy scalar to each active vector element
|
||||
INSN(sve_eor, 0b00000100, 0b011001000); // vector eor
|
||||
INSN(sve_eorv, 0b00000100, 0b011001001); // bitwise xor reduction to scalar
|
||||
INSN(sve_lsl, 0b00000100, 0b010011100); // vector logical shift left
|
||||
INSN(sve_lsr, 0b00000100, 0b010001100); // vector logical shift right
|
||||
INSN(sve_mul, 0b00000100, 0b010000000); // vector mul
|
||||
INSN(sve_neg, 0b00000100, 0b010111101); // vector neg, unary
|
||||
INSN(sve_not, 0b00000100, 0b011110101); // bitwise invert vector, unary
|
||||
INSN(sve_orr, 0b00000100, 0b011000000); // vector or
|
||||
INSN(sve_orv, 0b00000100, 0b011000001); // bitwise or reduction to scalar
|
||||
INSN(sve_smax, 0b00000100, 0b001000000); // signed maximum vectors
|
||||
INSN(sve_abs, 0b00000100, 0b010110101); // vector abs, unary
|
||||
INSN(sve_add, 0b00000100, 0b000000000); // vector add
|
||||
INSN(sve_and, 0b00000100, 0b011010000); // vector and
|
||||
INSN(sve_andv, 0b00000100, 0b011010001); // bitwise and reduction to scalar
|
||||
INSN(sve_asr, 0b00000100, 0b010000100); // vector arithmetic shift right
|
||||
INSN(sve_bic, 0b00000100, 0b011011000); // vector bitwise clear
|
||||
INSN(sve_clz, 0b00000100, 0b011001101); // vector count leading zero bits
|
||||
INSN(sve_cnt, 0b00000100, 0b011010101); // count non-zero bits
|
||||
INSN(sve_cpy, 0b00000101, 0b100000100); // copy scalar to each active vector element
|
||||
INSN(sve_eor, 0b00000100, 0b011001000); // vector eor
|
||||
INSN(sve_eorv, 0b00000100, 0b011001001); // bitwise xor reduction to scalar
|
||||
INSN(sve_lsl, 0b00000100, 0b010011100); // vector logical shift left
|
||||
INSN(sve_lsr, 0b00000100, 0b010001100); // vector logical shift right
|
||||
INSN(sve_mul, 0b00000100, 0b010000000); // vector mul
|
||||
INSN(sve_neg, 0b00000100, 0b010111101); // vector neg, unary
|
||||
INSN(sve_not, 0b00000100, 0b011110101); // bitwise invert vector, unary
|
||||
INSN(sve_orr, 0b00000100, 0b011000000); // vector or
|
||||
INSN(sve_orv, 0b00000100, 0b011000001); // bitwise or reduction to scalar
|
||||
INSN(sve_smax, 0b00000100, 0b001000000); // signed maximum vectors
|
||||
INSN(sve_smaxv, 0b00000100, 0b001000001); // signed maximum reduction to scalar
|
||||
INSN(sve_smin, 0b00000100, 0b001010000); // signed minimum vectors
|
||||
INSN(sve_sminv, 0b00000100, 0b001010001); // signed minimum reduction to scalar
|
||||
@ -3147,22 +3152,22 @@ public:
|
||||
sve_predicate_reg_insn(op1, op2, Zd_or_Zdn_or_Vd, T, Pg, Zn_or_Zm); \
|
||||
}
|
||||
|
||||
INSN(sve_fabs, 0b00000100, 0b011100101);
|
||||
INSN(sve_fadd, 0b01100101, 0b000000100);
|
||||
INSN(sve_fadda, 0b01100101, 0b011000001); // add strictly-ordered reduction to scalar Vd
|
||||
INSN(sve_fdiv, 0b01100101, 0b001101100);
|
||||
INSN(sve_fmax, 0b01100101, 0b000110100); // floating-point maximum
|
||||
INSN(sve_fmaxv, 0b01100101, 0b000110001); // floating-point maximum recursive reduction to scalar
|
||||
INSN(sve_fmin, 0b01100101, 0b000111100); // floating-point minimum
|
||||
INSN(sve_fminv, 0b01100101, 0b000111001); // floating-point minimum recursive reduction to scalar
|
||||
INSN(sve_fmul, 0b01100101, 0b000010100);
|
||||
INSN(sve_fneg, 0b00000100, 0b011101101);
|
||||
INSN(sve_frintm, 0b01100101, 0b000010101); // floating-point round to integral value, toward minus infinity
|
||||
INSN(sve_frintn, 0b01100101, 0b000000101); // floating-point round to integral value, nearest with ties to even
|
||||
INSN(sve_frinta, 0b01100101, 0b000100101); // floating-point round to integral value, nearest with ties to away
|
||||
INSN(sve_frintp, 0b01100101, 0b000001101); // floating-point round to integral value, toward plus infinity
|
||||
INSN(sve_fsqrt, 0b01100101, 0b001101101);
|
||||
INSN(sve_fsub, 0b01100101, 0b000001100);
|
||||
INSN(sve_fabs, 0b00000100, 0b011100101);
|
||||
INSN(sve_fadd, 0b01100101, 0b000000100);
|
||||
INSN(sve_fadda, 0b01100101, 0b011000001); // add strictly-ordered reduction to scalar Vd
|
||||
INSN(sve_fdiv, 0b01100101, 0b001101100);
|
||||
INSN(sve_fmax, 0b01100101, 0b000110100); // floating-point maximum
|
||||
INSN(sve_fmaxv, 0b01100101, 0b000110001); // floating-point maximum recursive reduction to scalar
|
||||
INSN(sve_fmin, 0b01100101, 0b000111100); // floating-point minimum
|
||||
INSN(sve_fminv, 0b01100101, 0b000111001); // floating-point minimum recursive reduction to scalar
|
||||
INSN(sve_fmul, 0b01100101, 0b000010100);
|
||||
INSN(sve_fneg, 0b00000100, 0b011101101);
|
||||
INSN(sve_frintm, 0b01100101, 0b000010101); // floating-point round to integral value, toward minus infinity
|
||||
INSN(sve_frintn, 0b01100101, 0b000000101); // floating-point round to integral value, nearest with ties to even
|
||||
INSN(sve_frinta, 0b01100101, 0b000100101); // floating-point round to integral value, nearest with ties to away
|
||||
INSN(sve_frintp, 0b01100101, 0b000001101); // floating-point round to integral value, toward plus infinity
|
||||
INSN(sve_fsqrt, 0b01100101, 0b001101101);
|
||||
INSN(sve_fsub, 0b01100101, 0b000001100);
|
||||
#undef INSN
|
||||
|
||||
// SVE multiple-add/sub - predicated
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user