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8366076: arm32: Fix register allocation for vector instructions

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Arm32 has 32 double-precision floating point registers, the first 16 of
which coincide with the 32 single-precision floating point registers.
Some vector-operation nodes were implemented in terms of scalar
instructions, which only really works for the first 16 doubles. This
commit addresses that.
This commit is contained in:
MaxVerevkin 2025-08-27 13:16:19 +03:00 committed by Max Verevkin
parent 88c3979367
commit 2faabeedfa
1 changed files with 26 additions and 6 deletions
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32
src/hotspot/cpu/arm/arm.ad
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@ -2282,6 +2282,16 @@ operand flagsRegF() %{
operand vecD() %{
constraint(ALLOC_IN_RC(actual_dflt_reg));
match(VecD);
match(vecD_low);
format %{ %}
interface(REG_INTER);
%}
operand vecD_low() %{
constraint(ALLOC_IN_RC(dflt_low_reg));
match(VecD);
match(vecD);
format %{ %}
interface(REG_INTER);
@ -2290,6 +2300,16 @@ operand vecD() %{
operand vecX() %{
constraint(ALLOC_IN_RC(vectorx_reg));
match(VecX);
match(vecX_low);
format %{ %}
interface(REG_INTER);
%}
operand vecX_low() %{
constraint(ALLOC_IN_RC(dflt_low_reg));
match(VecX);
match(vecX);
format %{ %}
interface(REG_INTER);
@ -9894,7 +9914,7 @@ instruct vadd2F_reg(vecD dst, vecD src1, vecD src2) %{
ins_pipe( faddD_reg_reg ); // FIXME
%}
instruct vadd2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
instruct vadd2F_reg_vfp(vecD_low dst, vecD_low src1, vecD_low src2) %{
predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
match(Set dst (AddVF src1 src2));
ins_cost(DEFAULT_COST*2); // FIXME
@ -9925,7 +9945,7 @@ instruct vadd4F_reg_simd(vecX dst, vecX src1, vecX src2) %{
ins_pipe( faddD_reg_reg ); // FIXME
%}
instruct vadd4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
instruct vadd4F_reg_vfp(vecX_low dst, vecX_low src1, vecX_low src2) %{
predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
match(Set dst (AddVF src1 src2));
size(4*4);
@ -10091,7 +10111,7 @@ instruct vsub2F_reg(vecD dst, vecD src1, vecD src2) %{
ins_pipe( faddF_reg_reg ); // FIXME
%}
instruct vsub2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
instruct vsub2F_reg_vfp(vecD_low dst, vecD_low src1, vecD_low src2) %{
predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
match(Set dst (SubVF src1 src2));
size(4*2);
@ -10128,7 +10148,7 @@ instruct vsub4F_reg(vecX dst, vecX src1, vecX src2) %{
ins_pipe( faddF_reg_reg ); // FIXME
%}
instruct vsub4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
instruct vsub4F_reg_vfp(vecX_low dst, vecX_low src1, vecX_low src2) %{
predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
match(Set dst (SubVF src1 src2));
size(4*4);
@ -10247,7 +10267,7 @@ instruct vmul2F_reg(vecD dst, vecD src1, vecD src2) %{
ins_pipe( fmulF_reg_reg ); // FIXME
%}
instruct vmul2F_reg_vfp(vecD dst, vecD src1, vecD src2) %{
instruct vmul2F_reg_vfp(vecD_low dst, vecD_low src1, vecD_low src2) %{
predicate(n->as_Vector()->length() == 2 && !VM_Version::simd_math_is_compliant());
match(Set dst (MulVF src1 src2));
size(4*2);
@ -10277,7 +10297,7 @@ instruct vmul4F_reg(vecX dst, vecX src1, vecX src2) %{
ins_pipe( fmulF_reg_reg ); // FIXME
%}
instruct vmul4F_reg_vfp(vecX dst, vecX src1, vecX src2) %{
instruct vmul4F_reg_vfp(vecX_low dst, vecX_low src1, vecX_low src2) %{
predicate(n->as_Vector()->length() == 4 && !VM_Version::simd_math_is_compliant());
match(Set dst (MulVF src1 src2));
size(4*4);