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8059592: Recent bugfixes in ppc64 port
Reviewed-by: kvn
This commit is contained in:
Goetz Lindenmaier
parent
d124a839ce
commit
3263a62bb4
@ -67,7 +67,6 @@ MAPFILE = $(GAMMADIR)/make/aix/makefiles/mapfile-vers-debug
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# not justified.
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LFLAGS_QIPA=
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G_SUFFIX = _g
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VERSION = optimized
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SYSDEFS += -DASSERT -DFASTDEBUG
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PICFLAGS = DEFAULT
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@ -268,8 +268,35 @@ class Assembler : public AbstractAssembler {
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ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
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MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT),
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MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT),
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// Special purpose registers
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MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
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MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
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MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
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MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
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MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
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MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
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MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
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MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
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MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
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MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
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MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT),
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MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT),
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MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT),
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MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT),
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MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT),
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MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT),
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MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT),
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MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT),
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MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT),
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MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT),
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MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT),
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MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
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MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
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@ -291,9 +318,6 @@ class Assembler : public AbstractAssembler {
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// CTR-related opcodes
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BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
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MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
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MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
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LWZ_OPCODE = (32u << OPCODE_SHIFT),
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LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
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@ -585,6 +609,37 @@ class Assembler : public AbstractAssembler {
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MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
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MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
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// AES (introduced with Power 8)
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VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
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VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
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VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
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VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
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VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
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// SHA (introduced with Power 8)
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VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
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VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
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// Vector Binary Polynomial Multiplication (introduced with Power 8)
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VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
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VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
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VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
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VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
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// Vector Permute and Xor (introduced with Power 8)
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VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
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// Transactional Memory instructions (introduced with Power 8)
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TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
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TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
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TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
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TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
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TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
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TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
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TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
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TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
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TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
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// Icache and dcache related instructions
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DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
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DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
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@ -1420,6 +1475,25 @@ class Assembler : public AbstractAssembler {
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inline void mcrf( ConditionRegister crd, ConditionRegister cra);
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inline void mtcr( Register s);
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// Special purpose registers
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// Exception Register
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inline void mtxer(Register s1);
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inline void mfxer(Register d);
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// Vector Register Save Register
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inline void mtvrsave(Register s1);
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inline void mfvrsave(Register d);
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// Timebase
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inline void mftb(Register d);
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// Introduced with Power 8:
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// Data Stream Control Register
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inline void mtdscr(Register s1);
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inline void mfdscr(Register d );
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// Transactional Memory Registers
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inline void mftfhar(Register d);
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inline void mftfiar(Register d);
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inline void mftexasr(Register d);
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inline void mftexasru(Register d);
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// PPC 1, section 2.4.1 Branch Instructions
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inline void b( address a, relocInfo::relocType rt = relocInfo::none);
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inline void b( Label& L);
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@ -1860,6 +1934,39 @@ class Assembler : public AbstractAssembler {
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inline void mtvscr( VectorRegister b);
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inline void mfvscr( VectorRegister d);
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// AES (introduced with Power 8)
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inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vsbox( VectorRegister d, VectorRegister a);
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// SHA (introduced with Power 8)
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// Not yet implemented.
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// Vector Binary Polynomial Multiplication (introduced with Power 8)
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inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
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// Vector Permute and Xor (introduced with Power 8)
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inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
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// Transactional Memory instructions (introduced with Power 8)
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inline void tbegin_(); // R=0
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inline void tbeginrot_(); // R=1 Rollback-Only Transaction
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inline void tend_(); // A=0
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inline void tendall_(); // A=1
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inline void tabort_(Register a);
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inline void tabortwc_(int t, Register a, Register b);
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inline void tabortwci_(int t, Register a, int si);
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inline void tabortdc_(int t, Register a, Register b);
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inline void tabortdci_(int t, Register a, int si);
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inline void tsuspend_(); // tsr with L=0
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inline void tresume_(); // tsr with L=1
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inline void tcheck(int f);
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// The following encoders use r0 as second operand. These instructions
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// read r0 as '0'.
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inline void lwzx( Register d, Register s2);
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@ -312,6 +312,25 @@ inline void Assembler::mcrf( ConditionRegister crd, ConditionRegister cra)
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{ emit_int32(MCRF_OPCODE | bf(crd) | bfa(cra)); }
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inline void Assembler::mtcr( Register s) { Assembler::mtcrf(0xff, s); }
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// Special purpose registers
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// Exception Register
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inline void Assembler::mtxer(Register s1) { emit_int32(MTXER_OPCODE | rs(s1)); }
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inline void Assembler::mfxer(Register d ) { emit_int32(MFXER_OPCODE | rt(d)); }
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// Vector Register Save Register
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inline void Assembler::mtvrsave(Register s1) { emit_int32(MTVRSAVE_OPCODE | rs(s1)); }
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inline void Assembler::mfvrsave(Register d ) { emit_int32(MFVRSAVE_OPCODE | rt(d)); }
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// Timebase
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inline void Assembler::mftb(Register d ) { emit_int32(MFTB_OPCODE | rt(d)); }
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// Introduced with Power 8:
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// Data Stream Control Register
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inline void Assembler::mtdscr(Register s1) { emit_int32(MTDSCR_OPCODE | rs(s1)); }
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inline void Assembler::mfdscr(Register d ) { emit_int32(MFDSCR_OPCODE | rt(d)); }
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// Transactional Memory Registers
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inline void Assembler::mftfhar(Register d ) { emit_int32(MFTFHAR_OPCODE | rt(d)); }
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inline void Assembler::mftfiar(Register d ) { emit_int32(MFTFIAR_OPCODE | rt(d)); }
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inline void Assembler::mftexasr(Register d ) { emit_int32(MFTEXASR_OPCODE | rt(d)); }
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inline void Assembler::mftexasru(Register d ) { emit_int32(MFTEXASRU_OPCODE | rt(d)); }
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// SAP JVM 2006-02-13 PPC branch instruction.
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// PPC 1, section 2.4.1 Branch Instructions
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inline void Assembler::b( address a, relocInfo::relocType rt) { emit_data(BXX_OPCODE| li(disp( intptr_t(a), intptr_t(pc()))) |aa(0)|lk(0), rt); }
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@ -735,6 +754,39 @@ inline void Assembler::vsrah( VectorRegister d, VectorRegister a, VectorRegist
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inline void Assembler::mtvscr( VectorRegister b) { emit_int32( MTVSCR_OPCODE | vrb(b)); }
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inline void Assembler::mfvscr( VectorRegister d) { emit_int32( MFVSCR_OPCODE | vrt(d)); }
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// AES (introduced with Power 8)
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inline void Assembler::vcipher( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHER_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VCIPHERLAST_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vncipher( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHER_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNCIPHERLAST_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vsbox( VectorRegister d, VectorRegister a) { emit_int32( VSBOX_OPCODE | vrt(d) | vra(a) ); }
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// SHA (introduced with Power 8)
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// Not yet implemented.
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// Vector Binary Polynomial Multiplication (introduced with Power 8)
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inline void Assembler::vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMH_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VPMSUMW_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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// Vector Permute and Xor (introduced with Power 8)
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inline void Assembler::vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c) { emit_int32( VPMSUMW_OPCODE | vrt(d) | vra(a) | vrb(b) | vrc(c)); }
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// Transactional Memory instructions (introduced with Power 8)
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inline void Assembler::tbegin_() { emit_int32( TBEGIN_OPCODE | rc(1)); }
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inline void Assembler::tbeginrot_() { emit_int32( TBEGIN_OPCODE | /*R=1*/ 1u << (31-10) | rc(1)); }
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inline void Assembler::tend_() { emit_int32( TEND_OPCODE | rc(1)); }
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inline void Assembler::tendall_() { emit_int32( TEND_OPCODE | /*A=1*/ 1u << (31-6) | rc(1)); }
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inline void Assembler::tabort_(Register a) { emit_int32( TABORT_OPCODE | ra(a) | rc(1)); }
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inline void Assembler::tabortwc_(int t, Register a, Register b) { emit_int32( TABORTWC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
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inline void Assembler::tabortwci_(int t, Register a, int si) { emit_int32( TABORTWCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
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inline void Assembler::tabortdc_(int t, Register a, Register b) { emit_int32( TABORTDC_OPCODE | to(t) | ra(a) | rb(b) | rc(1)); }
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inline void Assembler::tabortdci_(int t, Register a, int si) { emit_int32( TABORTDCI_OPCODE | to(t) | ra(a) | sh1620(si) | rc(1)); }
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inline void Assembler::tsuspend_() { emit_int32( TSR_OPCODE | rc(1)); }
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inline void Assembler::tresume_() { emit_int32( TSR_OPCODE | /*L=1*/ 1u << (31-10) | rc(1)); }
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inline void Assembler::tcheck(int f) { emit_int32( TCHECK_OPCODE | bf(f)); }
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// ra0 version
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inline void Assembler::lwzx( Register d, Register s2) { emit_int32( LWZX_OPCODE | rt(d) | rb(s2));}
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inline void Assembler::lwz( Register d, int si16 ) { emit_int32( LWZ_OPCODE | rt(d) | d1(si16));}
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@ -37,6 +37,8 @@ const int StackAlignmentInBytes = 16;
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// signatures accordingly.
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const bool CCallingConventionRequiresIntsAsLongs = true;
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#define SUPPORTS_NATIVE_CX8
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// The PPC CPUs are NOT multiple-copy-atomic.
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#define CPU_NOT_MULTIPLE_COPY_ATOMIC
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@ -25,7 +25,6 @@
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#include "precompiled.hpp"
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#include "asm/assembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "interp_masm_ppc_64.hpp"
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#include "interpreter/interpreterRuntime.hpp"
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@ -24,7 +24,6 @@
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*/
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#include "precompiled.hpp"
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#include "asm/assembler.hpp"
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#include "asm/macroAssembler.inline.hpp"
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#include "interpreter/bytecodeHistogram.hpp"
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#include "interpreter/interpreter.hpp"
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@ -2366,7 +2366,7 @@ void MacroAssembler::g1_write_barrier_post(Register Rstore_addr, Register Rnew_v
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#endif // INCLUDE_ALL_GCS
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// Values for last_Java_pc, and last_Java_sp must comply to the rules
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// in frame_ppc64.hpp.
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// in frame_ppc.hpp.
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void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc) {
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// Always set last_Java_pc and flags first because once last_Java_sp
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// is visible has_last_Java_frame is true and users will look at the
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@ -2493,6 +2493,7 @@ int MacroAssembler::instr_size_for_decode_klass_not_null() {
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}
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void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
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assert(dst != R0, "Dst reg may not be R0, as R0 is used here.");
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if (src == noreg) src = dst;
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Register shifted_src = src;
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if (Universe::narrow_klass_shift() != 0 ||
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@ -2527,14 +2528,11 @@ void MacroAssembler::load_klass_with_trap_null_check(Register dst, Register src)
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void MacroAssembler::reinit_heapbase(Register d, Register tmp) {
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if (Universe::heap() != NULL) {
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if (Universe::narrow_oop_base() == NULL) {
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Assembler::xorr(R30, R30, R30);
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} else {
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load_const(R30, Universe::narrow_ptrs_base(), tmp);
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}
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load_const_optimized(R30, Universe::narrow_ptrs_base(), tmp);
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} else {
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load_const(R30, Universe::narrow_ptrs_base_addr(), tmp);
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ld(R30, 0, R30);
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// Heap not yet allocated. Load indirectly.
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int simm16_offset = load_const_optimized(R30, Universe::narrow_ptrs_base_addr(), tmp, true);
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ld(R30, simm16_offset, R30);
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}
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}
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@ -1249,6 +1249,7 @@ EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address en
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// Emit the trampoline stub which will be related to the branch-and-link below.
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CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
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if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
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__ relocate(rtype);
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}
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@ -1410,7 +1411,7 @@ void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
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while (bang_offset <= bang_end) {
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// Need at least one stack bang at end of shadow zone.
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// Again I had to copy code, this time from assembler_ppc64.cpp,
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// Again I had to copy code, this time from assembler_ppc.cpp,
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// bang_stack_with_offset - see there for comments.
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// Stack grows down, caller passes positive offset.
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@ -2000,7 +2001,7 @@ void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
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// Inline_cache contains a klass.
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Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
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Register receiver_klass = R0; // tmp
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Register receiver_klass = R12_scratch2; // tmp
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assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
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assert(R11_scratch1 == R11, "need prologue scratch register");
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@ -3484,6 +3485,7 @@ encode %{
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// Emit the trampoline stub which will be related to the branch-and-link below.
|
||||
CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
|
||||
if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
|
||||
__ relocate(_optimized_virtual ?
|
||||
relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
|
||||
}
|
||||
@ -3527,6 +3529,7 @@ encode %{
|
||||
|
||||
// Emit the trampoline stub which will be related to the branch-and-link below.
|
||||
CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
|
||||
if (ra_->C->env()->failing()) { return; } // Code cache may be full.
|
||||
assert(_optimized_virtual, "methodHandle call should be a virtual call");
|
||||
__ relocate(relocInfo::opt_virtual_call_type);
|
||||
}
|
||||
@ -3577,9 +3580,7 @@ encode %{
|
||||
const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
|
||||
const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
|
||||
CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
|
||||
|
||||
if (ra_->C->env()->failing())
|
||||
return;
|
||||
if (ra_->C->env()->failing()) { return; } // Code cache may be full.
|
||||
|
||||
// Build relocation at call site with ic position as data.
|
||||
assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
|
||||
@ -5638,19 +5639,6 @@ instruct loadNKlass(iRegNdst dst, memory mem) %{
|
||||
ins_pipe(pipe_class_memory);
|
||||
%}
|
||||
|
||||
//// Load compressed klass and decode it if narrow_klass_shift == 0.
|
||||
//// TODO: will narrow_klass_shift ever be 0?
|
||||
//instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{
|
||||
// match(Set dst (DecodeNKlass (LoadNKlass mem)));
|
||||
// predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*);
|
||||
// ins_cost(MEMORY_REF_COST);
|
||||
//
|
||||
// format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %}
|
||||
// size(4);
|
||||
// ins_encode( enc_lwz(dst, mem) );
|
||||
// ins_pipe(pipe_class_memory);
|
||||
//%}
|
||||
|
||||
// Load Klass Pointer
|
||||
instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
|
||||
match(Set dst (LoadKlass mem));
|
||||
@ -6070,11 +6058,15 @@ instruct loadConN_Ex(iRegNdst dst, immN src) %{
|
||||
%}
|
||||
%}
|
||||
|
||||
instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
|
||||
// We have seen a safepoint between the hi and lo parts, and this node was handled
|
||||
// as an oop. Therefore this needs a match rule so that build_oop_map knows this is
|
||||
// not a narrow oop.
|
||||
instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
|
||||
match(Set dst src);
|
||||
effect(DEF dst, USE src);
|
||||
ins_cost(DEFAULT_COST);
|
||||
|
||||
format %{ "LIS $dst, $src \t// narrow oop hi" %}
|
||||
format %{ "LIS $dst, $src \t// narrow klass hi" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_addis);
|
||||
@ -6084,6 +6076,21 @@ instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// As loadConNKlass_hi this must be recognized as narrow klass, not oop!
|
||||
instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
|
||||
match(Set dst src1);
|
||||
effect(TEMP src2);
|
||||
ins_cost(DEFAULT_COST);
|
||||
|
||||
format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
|
||||
__ clrldi($dst$$Register, $src2$$Register, 0x20);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// This needs a match rule so that build_oop_map knows this is
|
||||
// not a narrow oop.
|
||||
instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
|
||||
@ -6091,10 +6098,10 @@ instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
|
||||
effect(TEMP src2);
|
||||
ins_cost(DEFAULT_COST);
|
||||
|
||||
format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %}
|
||||
format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_addi);
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_ori);
|
||||
intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
|
||||
assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
|
||||
int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
|
||||
@ -6125,10 +6132,11 @@ instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
|
||||
MachNode *m2 = m1;
|
||||
if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
|
||||
// Value might be 1-extended. Mask out these bits.
|
||||
m2 = new clearMs32bNode();
|
||||
m2 = new loadConNKlass_maskNode();
|
||||
m2->add_req(NULL, m1);
|
||||
m2->_opnds[0] = op_dst;
|
||||
m2->_opnds[1] = op_dst;
|
||||
m2->_opnds[1] = op_src;
|
||||
m2->_opnds[2] = op_dst;
|
||||
ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
|
||||
nodes->push(m2);
|
||||
}
|
||||
@ -6973,7 +6981,7 @@ instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
|
||||
__ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
|
||||
__ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
@ -24,7 +24,6 @@
|
||||
*/
|
||||
|
||||
#include "precompiled.hpp"
|
||||
#include "asm/assembler.hpp"
|
||||
#include "asm/macroAssembler.inline.hpp"
|
||||
#include "interpreter/interpreter.hpp"
|
||||
#include "nativeInst_ppc.hpp"
|
||||
@ -39,9 +38,6 @@
|
||||
#include "runtime/stubCodeGenerator.hpp"
|
||||
#include "runtime/stubRoutines.hpp"
|
||||
#include "utilities/top.hpp"
|
||||
#ifdef COMPILER2
|
||||
#include "opto/runtime.hpp"
|
||||
#endif
|
||||
#include "runtime/thread.inline.hpp"
|
||||
|
||||
#define __ _masm->
|
||||
@ -216,7 +212,7 @@ class StubGenerator: public StubCodeGenerator {
|
||||
{
|
||||
BLOCK_COMMENT("Call frame manager or native entry.");
|
||||
// Call frame manager or native entry.
|
||||
Register r_new_arg_entry = R14; // PPC_state;
|
||||
Register r_new_arg_entry = R14;
|
||||
assert_different_registers(r_new_arg_entry, r_top_of_arguments_addr,
|
||||
r_arg_method, r_arg_thread);
|
||||
|
||||
|
||||
@ -353,7 +353,6 @@ void TemplateTable::ldc(bool wide) {
|
||||
__ sldi(Rscratch1, Rscratch1, LogBytesPerWord);
|
||||
__ cmpdi(CCR0, Rscratch2, JVM_CONSTANT_Integer);
|
||||
__ bne(CCR0, notInt);
|
||||
__ isync(); // Order load of constant wrt. tags.
|
||||
__ lwax(R17_tos, Rcpool, Rscratch1);
|
||||
__ push(itos);
|
||||
__ b(exit);
|
||||
@ -365,7 +364,6 @@ void TemplateTable::ldc(bool wide) {
|
||||
__ cmpdi(CCR0, Rscratch2, JVM_CONSTANT_Float);
|
||||
__ asm_assert_eq("unexpected type", 0x8765);
|
||||
#endif
|
||||
__ isync(); // Order load of constant wrt. tags.
|
||||
__ lfsx(F15_ftos, Rcpool, Rscratch1);
|
||||
__ push(ftos);
|
||||
|
||||
@ -424,13 +422,11 @@ void TemplateTable::ldc2_w() {
|
||||
// Check out Conversions.java for an example.
|
||||
// Also ConstantPool::header_size() is 20, which makes it very difficult
|
||||
// to double-align double on the constant pool. SG, 11/7/97
|
||||
__ isync(); // Order load of constant wrt. tags.
|
||||
__ lfdx(F15_ftos, Rcpool, Rindex);
|
||||
__ push(dtos);
|
||||
__ b(Lexit);
|
||||
|
||||
__ bind(Llong);
|
||||
__ isync(); // Order load of constant wrt. tags.
|
||||
__ ldx(R17_tos, Rcpool, Rindex);
|
||||
__ push(ltos);
|
||||
|
||||
|
||||
@ -47,4 +47,4 @@ inline void Prefetch::write(void *loc, intx interval) {
|
||||
);
|
||||
}
|
||||
|
||||
#endif // OS_CPU_LINUX_PPC_VM_PREFETCH_LINUX_OJDKPPC_HPP
|
||||
#endif // OS_CPU_LINUX_PPC_VM_PREFETCH_LINUX_PPC_INLINE_HPP
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user