From 43b337eb438f230dbca903b56e0809fc36fcd71d Mon Sep 17 00:00:00 2001
From: Amit Kumar <amitkumar@openjdk.org>
Date: Wed, 4 Dec 2024 03:44:41 +0000
Subject: [PATCH] 8344304: [s390x] ubsan: negation of -2147483648 cannot be
 represented in type 'int'

Reviewed-by: lucy, dlong
---
 src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp |  8 +++--
 src/hotspot/cpu/s390/macroAssembler_s390.cpp  | 33 ++++++++++++++++++-
 src/hotspot/cpu/s390/macroAssembler_s390.hpp  |  4 ++-
 3 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
index dee64d3db26..bb0494dc478 100644
--- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
+++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
@@ -1532,8 +1532,12 @@ void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr
       // cpu register - constant
       jint c = right->as_constant_ptr()->as_jint();
       switch (code) {
-        case lir_add: __ z_agfi(lreg, c);  break;
-        case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
+        case lir_add:
+                      __ add2reg_32(lreg, c);
+                      break;
+        case lir_sub:
+                      __ add2reg_32(lreg, java_negate(c));
+                      break;
         case lir_mul: __ z_msfi(lreg, c);  break;
         default: ShouldNotReachHere();
       }
diff --git a/src/hotspot/cpu/s390/macroAssembler_s390.cpp b/src/hotspot/cpu/s390/macroAssembler_s390.cpp
index aacfb894c72..c297c66b02b 100644
--- a/src/hotspot/cpu/s390/macroAssembler_s390.cpp
+++ b/src/hotspot/cpu/s390/macroAssembler_s390.cpp
@@ -657,7 +657,7 @@ void MacroAssembler::add2reg(Register r1, int64_t imm, Register r2) {
         z_aghik(r1, r2, imm);
         return;
       }
-      z_lgr(r1, r2);
+      lgr_if_needed(r1, r2);
       z_aghi(r1, imm);
       return;
     }
@@ -681,6 +681,37 @@ void MacroAssembler::add2reg(Register r1, int64_t imm, Register r2) {
   z_agfi(r1, imm);
 }
 
+void MacroAssembler::add2reg_32(Register r1, int64_t imm, Register r2) {
+  assert(Immediate::is_simm32(imm), "probably an implicit conversion went wrong");
+
+  if (r2 == noreg) { r2 = r1; }
+
+  // Handle special case imm == 0.
+  if (imm == 0) {
+    lr_if_needed(r1, r2);
+    // Nothing else to do.
+    return;
+  }
+
+  if (Immediate::is_simm16(imm)) {
+    if (r1 == r2){
+      z_ahi(r1, imm);
+      return;
+    }
+    if (VM_Version::has_DistinctOpnds()) {
+      z_ahik(r1, r2, imm);
+      return;
+    }
+    lr_if_needed(r1, r2);
+    z_ahi(r1, imm);
+    return;
+  }
+
+  // imm is simm32
+  lr_if_needed(r1, r2);
+  z_afi(r1, imm);
+}
+
 // Generic operation r := b + x + d
 //
 // Addition of several operands with address generation semantics - sort of:
diff --git a/src/hotspot/cpu/s390/macroAssembler_s390.hpp b/src/hotspot/cpu/s390/macroAssembler_s390.hpp
index 91703fac994..15968812818 100644
--- a/src/hotspot/cpu/s390/macroAssembler_s390.hpp
+++ b/src/hotspot/cpu/s390/macroAssembler_s390.hpp
@@ -156,7 +156,9 @@ class MacroAssembler: public Assembler {
   unsigned int mul_reg64_const16(Register rval, Register work, int cval);
 
   // Generic operation r1 := r2 + imm.
-  void add2reg(Register r1, int64_t imm, Register r2 = noreg);
+  void add2reg   (Register r1, int64_t imm, Register r2 = noreg);
+  void add2reg_32(Register r1, int64_t imm, Register r2 = noreg);
+
   // Generic operation r := b + x + d.
   void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);