8376113: PPC64: Implement special MachNodes for floating point Min / Max

This commit is contained in:
David Linus Briemann 2026-01-22 12:43:46 +01:00
parent 3033e6f421
commit 495c3d4cd2
3 changed files with 57 additions and 0 deletions

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@ -596,6 +596,9 @@ class Assembler : public AbstractAssembler {
XVMAXSP_OPCODE = (60u << OPCODE_SHIFT | 192u << 3),
XVMAXDP_OPCODE = (60u << OPCODE_SHIFT | 224u << 3),
XSMINJDP_OPCODE = (60u << OPCODE_SHIFT | 152u << 3),
XSMAXJDP_OPCODE = (60u << OPCODE_SHIFT | 144u << 3),
// Deliver A Random Number (introduced with POWER9)
DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1),
@ -2449,6 +2452,9 @@ class Assembler : public AbstractAssembler {
inline void xvrdpim( VectorSRegister d, VectorSRegister b);
inline void xvrdpip( VectorSRegister d, VectorSRegister b);
inline void xsminjdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); // Requires Power 9
inline void xsmaxjdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); // Requires Power 9
// The following functions do not match exactly the Java.math semantics.
inline void xvminsp( VectorSRegister d, VectorSRegister a, VectorSRegister b);
inline void xvmindp( VectorSRegister d, VectorSRegister a, VectorSRegister b);

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@ -908,6 +908,9 @@ inline void Assembler::xvrdpic( VectorSRegister d, VectorSRegister b)
inline void Assembler::xvrdpim( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIM_OPCODE | vsrt(d) | vsrb(b)); }
inline void Assembler::xvrdpip( VectorSRegister d, VectorSRegister b) { emit_int32( XVRDPIP_OPCODE | vsrt(d) | vsrb(b)); }
inline void Assembler::xsminjdp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XSMINJDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xsmaxjdp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XSMAXJDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvminsp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMINSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvmindp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMINDP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
inline void Assembler::xvmaxsp(VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XVMAXSP_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }

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@ -12261,6 +12261,54 @@ instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegC
ins_pipe(pipe_class_default);
%}
instruct minF(regF dst, regF src1, regF src2) %{
match(Set dst (MinF src1 src2));
predicate(PowerArchitecturePPC64 >= 9);
ins_cost(DEFAULT_COST);
size(4);
ins_encode %{
__ xsminjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
%}
ins_pipe(pipe_class_default);
%}
instruct minD(regD dst, regD src1, regD src2) %{
match(Set dst (MinD src1 src2));
predicate(PowerArchitecturePPC64 >= 9);
ins_cost(DEFAULT_COST);
size(4);
ins_encode %{
__ xsminjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
%}
ins_pipe(pipe_class_default);
%}
instruct maxF(regF dst, regF src1, regF src2) %{
match(Set dst (MaxF src1 src2));
predicate(PowerArchitecturePPC64 >= 9);
ins_cost(DEFAULT_COST);
size(4);
ins_encode %{
__ xsmaxjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
%}
ins_pipe(pipe_class_default);
%}
instruct maxD(regD dst, regD src1, regD src2) %{
match(Set dst (MaxD src1 src2));
predicate(PowerArchitecturePPC64 >= 9);
ins_cost(DEFAULT_COST);
size(4);
ins_encode %{
__ xsmaxjdp($dst$$FloatRegister->to_vsr(), $src1$$FloatRegister->to_vsr(), $src2$$FloatRegister->to_vsr());
%}
ins_pipe(pipe_class_default);
%}
//---------- Population Count Instructions ------------------------------------
instruct popCountI(iRegIdst dst, iRegIsrc src) %{