diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp index d1669cd3737..3c12a60f788 100644 --- a/src/hotspot/cpu/riscv/assembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp @@ -1230,13 +1230,19 @@ enum VectorMask { INSN(viota_m, 0b1010111, 0b010, 0b10000, 0b010100); // Vector Single-Width Floating-Point/Integer Type-Convert Instructions - INSN(vfcvt_xu_f_v, 0b1010111, 0b001, 0b00000, 0b010010); - INSN(vfcvt_x_f_v, 0b1010111, 0b001, 0b00001, 0b010010); - INSN(vfcvt_f_xu_v, 0b1010111, 0b001, 0b00010, 0b010010); - INSN(vfcvt_f_x_v, 0b1010111, 0b001, 0b00011, 0b010010); - INSN(vfcvt_rtz_xu_f_v, 0b1010111, 0b001, 0b00110, 0b010010); + INSN(vfcvt_f_x_v, 0b1010111, 0b001, 0b00011, 0b010010); INSN(vfcvt_rtz_x_f_v, 0b1010111, 0b001, 0b00111, 0b010010); + // Vector Widening Floating-Point/Integer Type-Convert Instructions + INSN(vfwcvt_f_x_v, 0b1010111, 0b001, 0b01011, 0b010010); + INSN(vfwcvt_f_f_v, 0b1010111, 0b001, 0b01100, 0b010010); + INSN(vfwcvt_rtz_x_f_v, 0b1010111, 0b001, 0b01111, 0b010010); + + // Vector Narrowing Floating-Point/Integer Type-Convert Instructions + INSN(vfncvt_f_x_w, 0b1010111, 0b001, 0b10011, 0b010010); + INSN(vfncvt_f_f_w, 0b1010111, 0b001, 0b10100, 0b010010); + INSN(vfncvt_rtz_x_f_w, 0b1010111, 0b001, 0b10111, 0b010010); + // Vector Floating-Point Instruction INSN(vfsqrt_v, 0b1010111, 0b001, 0b00000, 0b010011); INSN(vfclass_v, 0b1010111, 0b001, 0b10000, 0b010011); @@ -1431,6 +1437,9 @@ enum VectorMask { INSN(vsub_vv, 0b1010111, 0b000, 0b000010); INSN(vadd_vv, 0b1010111, 0b000, 0b000000); + // Vector Register Gather Instructions + INSN(vrgather_vv, 0b1010111, 0b000, 0b001100); + #undef INSN diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp index 01d99db782c..09ee1bc1c3d 100644 --- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp @@ -1617,10 +1617,10 @@ void C2_MacroAssembler::string_indexof_char_v(Register str1, Register cnt1, // Set dst to NaN if any NaN input. void C2_MacroAssembler::minmax_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, - bool is_double, bool is_min, int length_in_bytes) { + bool is_double, bool is_min, int vector_length) { assert_different_registers(dst, src1, src2); - rvv_vsetvli(is_double ? T_DOUBLE : T_FLOAT, length_in_bytes); + vsetvli_helper(is_double ? T_DOUBLE : T_FLOAT, vector_length); is_min ? vfmin_vv(dst, src1, src2) : vfmax_vv(dst, src1, src2); @@ -1635,11 +1635,11 @@ void C2_MacroAssembler::minmax_fp_v(VectorRegister dst, VectorRegister src1, Vec void C2_MacroAssembler::reduce_minmax_fp_v(FloatRegister dst, FloatRegister src1, VectorRegister src2, VectorRegister tmp1, VectorRegister tmp2, - bool is_double, bool is_min, int length_in_bytes) { + bool is_double, bool is_min, int vector_length) { assert_different_registers(src2, tmp1, tmp2); Label L_done, L_NaN; - rvv_vsetvli(is_double ? T_DOUBLE : T_FLOAT, length_in_bytes); + vsetvli_helper(is_double ? T_DOUBLE : T_FLOAT, vector_length); vfmv_s_f(tmp2, src1); is_min ? vfredmin_vs(tmp1, src2, tmp2) @@ -1670,12 +1670,12 @@ bool C2_MacroAssembler::in_scratch_emit_size() { return MacroAssembler::in_scratch_emit_size(); } -void C2_MacroAssembler::rvv_reduce_integral(Register dst, VectorRegister tmp, - Register src1, VectorRegister src2, - BasicType bt, int opc, int length_in_bytes) { +void C2_MacroAssembler::reduce_integral_v(Register dst, VectorRegister tmp, + Register src1, VectorRegister src2, + BasicType bt, int opc, int vector_length) { assert(bt == T_BYTE || bt == T_SHORT || bt == T_INT || bt == T_LONG, "unsupported element type"); - rvv_vsetvli(bt, length_in_bytes); + vsetvli_helper(bt, vector_length); vmv_s_x(tmp, src1); @@ -1707,27 +1707,24 @@ void C2_MacroAssembler::rvv_reduce_integral(Register dst, VectorRegister tmp, } // Set vl and vtype for full and partial vector operations. -// (vlmul = m1, vma = mu, vta = tu, vill = false) -void C2_MacroAssembler::rvv_vsetvli(BasicType bt, int length_in_bytes, Register tmp) { +// (vma = mu, vta = tu, vill = false) +void C2_MacroAssembler::vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul, Register tmp) { Assembler::SEW sew = Assembler::elemtype_to_sew(bt); - if (length_in_bytes == MaxVectorSize) { - vsetvli(tmp, x0, sew); + if (vector_length <= 31) { + vsetivli(tmp, vector_length, sew, vlmul); + } else if (vector_length == (MaxVectorSize / type2aelembytes(bt))) { + vsetvli(tmp, x0, sew, vlmul); } else { - int num_elements = length_in_bytes / type2aelembytes(bt); - if (num_elements <= 31) { - vsetivli(tmp, num_elements, sew); - } else { - mv(tmp, num_elements); - vsetvli(tmp, tmp, sew); - } + mv(tmp, vector_length); + vsetvli(tmp, tmp, sew, vlmul); } } -void C2_MacroAssembler::compare_integral_v(VectorRegister vd, BasicType bt, int length_in_bytes, +void C2_MacroAssembler::compare_integral_v(VectorRegister vd, BasicType bt, int vector_length, VectorRegister src1, VectorRegister src2, int cond, VectorMask vm) { assert(is_integral_type(bt), "unsupported element type"); assert(vm == Assembler::v0_t ? vd != v0 : true, "should be different registers"); - rvv_vsetvli(bt, length_in_bytes); + vsetvli_helper(bt, vector_length); vmclr_m(vd); switch (cond) { case BoolTest::eq: vmseq_vv(vd, src1, src2, vm); break; @@ -1742,15 +1739,15 @@ void C2_MacroAssembler::compare_integral_v(VectorRegister vd, BasicType bt, int } } -void C2_MacroAssembler::compare_floating_point_v(VectorRegister vd, BasicType bt, int length_in_bytes, +void C2_MacroAssembler::compare_floating_point_v(VectorRegister vd, BasicType bt, int vector_length, VectorRegister src1, VectorRegister src2, VectorRegister tmp1, VectorRegister tmp2, VectorRegister vmask, int cond, VectorMask vm) { assert(is_floating_point_type(bt), "unsupported element type"); assert(vd != v0, "should be different registers"); assert(vm == Assembler::v0_t ? vmask != v0 : true, "vmask should not be v0"); - rvv_vsetvli(bt, length_in_bytes); - // Check vector elements of src1 and src2 for quiet or signaling NaN. + vsetvli_helper(bt, vector_length); + // Check vector elements of src1 and src2 for quiet and signaling NaN. vfclass_v(tmp1, src1); vfclass_v(tmp2, src2); vsrl_vi(tmp1, tmp1, 8); @@ -1782,4 +1779,91 @@ void C2_MacroAssembler::compare_floating_point_v(VectorRegister vd, BasicType bt assert(false, "unsupported compare condition"); ShouldNotReachHere(); } -} \ No newline at end of file +} + +void C2_MacroAssembler::integer_extend_v(VectorRegister dst, BasicType dst_bt, int vector_length, + VectorRegister src, BasicType src_bt) { + assert(type2aelembytes(dst_bt) > type2aelembytes(src_bt) && type2aelembytes(dst_bt) <= 8 && type2aelembytes(src_bt) <= 4, "invalid element size"); + assert(dst_bt != T_FLOAT && dst_bt != T_DOUBLE && src_bt != T_FLOAT && src_bt != T_DOUBLE, "unsupported element type"); + // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#52-vector-operands + // The destination EEW is greater than the source EEW, the source EMUL is at least 1, + // and the overlap is in the highest-numbered part of the destination register group. + // Since LMUL=1, vd and vs cannot be the same. + assert_different_registers(dst, src); + + vsetvli_helper(dst_bt, vector_length); + if (src_bt == T_BYTE) { + switch (dst_bt) { + case T_SHORT: + vsext_vf2(dst, src); + break; + case T_INT: + vsext_vf4(dst, src); + break; + case T_LONG: + vsext_vf8(dst, src); + break; + default: + ShouldNotReachHere(); + } + } else if (src_bt == T_SHORT) { + if (dst_bt == T_INT) { + vsext_vf2(dst, src); + } else { + vsext_vf4(dst, src); + } + } else if (src_bt == T_INT) { + vsext_vf2(dst, src); + } +} + +// Vector narrow from src to dst with specified element sizes. +// High part of dst vector will be filled with zero. +void C2_MacroAssembler::integer_narrow_v(VectorRegister dst, BasicType dst_bt, int vector_length, + VectorRegister src, BasicType src_bt) { + assert(type2aelembytes(dst_bt) < type2aelembytes(src_bt) && type2aelembytes(dst_bt) <= 4 && type2aelembytes(src_bt) <= 8, "invalid element size"); + assert(dst_bt != T_FLOAT && dst_bt != T_DOUBLE && src_bt != T_FLOAT && src_bt != T_DOUBLE, "unsupported element type"); + mv(t0, vector_length); + if (src_bt == T_LONG) { + // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#117-vector-narrowing-integer-right-shift-instructions + // Future extensions might add support for versions that narrow to a destination that is 1/4 the width of the source. + // So we can currently only scale down by 1/2 the width at a time. + vsetvli(t0, t0, Assembler::e32, Assembler::mf2); + vncvt_x_x_w(dst, src); + if (dst_bt == T_SHORT || dst_bt == T_BYTE) { + vsetvli(t0, t0, Assembler::e16, Assembler::mf2); + vncvt_x_x_w(dst, dst); + if (dst_bt == T_BYTE) { + vsetvli(t0, t0, Assembler::e8, Assembler::mf2); + vncvt_x_x_w(dst, dst); + } + } + } else if (src_bt == T_INT) { + // T_SHORT + vsetvli(t0, t0, Assembler::e16, Assembler::mf2); + vncvt_x_x_w(dst, src); + if (dst_bt == T_BYTE) { + vsetvli(t0, t0, Assembler::e8, Assembler::mf2); + vncvt_x_x_w(dst, dst); + } + } else if (src_bt == T_SHORT) { + vsetvli(t0, t0, Assembler::e8, Assembler::mf2); + vncvt_x_x_w(dst, src); + } +} + +#define VFCVT_SAFE(VFLOATCVT) \ +void C2_MacroAssembler::VFLOATCVT##_safe(VectorRegister dst, VectorRegister src) { \ + assert_different_registers(dst, src); \ + vfclass_v(v0, src); \ + vxor_vv(dst, dst, dst); \ + vsrl_vi(v0, v0, 8); \ + vmseq_vx(v0, v0, zr); \ + VFLOATCVT(dst, src, Assembler::v0_t); \ +} + +VFCVT_SAFE(vfcvt_rtz_x_f_v); +VFCVT_SAFE(vfwcvt_rtz_x_f_v); +VFCVT_SAFE(vfncvt_rtz_x_f_w); + +#undef VFCVT_SAFE \ No newline at end of file diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp index 30aac05f40b..71e3af91964 100644 --- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp @@ -187,23 +187,23 @@ void minmax_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, - bool is_double, bool is_min, int length_in_bytes); + bool is_double, bool is_min, int vector_length); void reduce_minmax_fp_v(FloatRegister dst, FloatRegister src1, VectorRegister src2, VectorRegister tmp1, VectorRegister tmp2, - bool is_double, bool is_min, int length_in_bytes); + bool is_double, bool is_min, int vector_length); - void rvv_reduce_integral(Register dst, VectorRegister tmp, - Register src1, VectorRegister src2, - BasicType bt, int opc, int length_in_bytes); + void reduce_integral_v(Register dst, VectorRegister tmp, + Register src1, VectorRegister src2, + BasicType bt, int opc, int vector_length); - void rvv_vsetvli(BasicType bt, int length_in_bytes, Register tmp = t0); + void vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul = Assembler::m1, Register tmp = t0); - void compare_integral_v(VectorRegister dst, BasicType bt, int length_in_bytes, + void compare_integral_v(VectorRegister dst, BasicType bt, int vector_length, VectorRegister src1, VectorRegister src2, int cond, VectorMask vm = Assembler::unmasked); - void compare_floating_point_v(VectorRegister dst, BasicType bt, int length_in_bytes, + void compare_floating_point_v(VectorRegister dst, BasicType bt, int vector_length, VectorRegister src1, VectorRegister src2, VectorRegister tmp1, VectorRegister tmp2, VectorRegister vmask, int cond, VectorMask vm = Assembler::unmasked); @@ -211,13 +211,13 @@ // we assume each predicate register is one-eighth of the size of // scalable vector register, one mask bit per vector byte. void spill_vmask(VectorRegister v, int offset){ - rvv_vsetvli(T_BYTE, MaxVectorSize >> 3); + vsetvli_helper(T_BYTE, MaxVectorSize >> 3); add(t0, sp, offset); vse8_v(v, t0); } void unspill_vmask(VectorRegister v, int offset){ - rvv_vsetvli(T_BYTE, MaxVectorSize >> 3); + vsetvli_helper(T_BYTE, MaxVectorSize >> 3); add(t0, sp, offset); vle8_v(v, t0); } @@ -230,4 +230,14 @@ } } + void integer_extend_v(VectorRegister dst, BasicType dst_bt, int vector_length, + VectorRegister src, BasicType src_bt); + + void integer_narrow_v(VectorRegister dst, BasicType dst_bt, int vector_length, + VectorRegister src, BasicType src_bt); + + void vfcvt_rtz_x_f_v_safe(VectorRegister dst, VectorRegister src); + void vfwcvt_rtz_x_f_v_safe(VectorRegister dst, VectorRegister src); + void vfncvt_rtz_x_f_w_safe(VectorRegister dst, VectorRegister src); + #endif // CPU_RISCV_C2_MACROASSEMBLER_RISCV_HPP diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad index 88dd95a1b8a..8662710b97e 100644 --- a/src/hotspot/cpu/riscv/riscv.ad +++ b/src/hotspot/cpu/riscv/riscv.ad @@ -1944,6 +1944,7 @@ const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, Bas case Op_URShiftVI: case Op_URShiftVL: case Op_VectorBlend: + case Op_VectorReinterpret: break; case Op_LoadVector: opcode = Op_LoadVectorMasked; @@ -2030,7 +2031,10 @@ const int Matcher::min_vector_size(const BasicType bt) { int max_size = max_vector_size(bt); // Limit the min vector size to 8 bytes. int size = 8 / type2aelembytes(bt); - if (bt == T_BOOLEAN) { + if (bt == T_BYTE) { + // To support vector api shuffle/rearrange. + size = 4; + } else if (bt == T_BOOLEAN) { // To support vector api load/store mask. size = 2; } diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 240baa1b577..bf631034e25 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -36,9 +36,9 @@ source %{ static void loadStore(C2_MacroAssembler masm, bool is_store, VectorRegister reg, BasicType bt, Register base, - int length_in_bytes, Assembler::VectorMask vm = Assembler::unmasked) { + int vector_length, Assembler::VectorMask vm = Assembler::unmasked) { Assembler::SEW sew = Assembler::elemtype_to_sew(bt); - masm.rvv_vsetvli(bt, length_in_bytes); + masm.vsetvli_helper(bt, vector_length); if (is_store) { masm.vsex_v(reg, base, sew, vm); @@ -70,17 +70,7 @@ source %{ // Vector API specific case Op_LoadVectorGather: case Op_StoreVectorScatter: - case Op_VectorCast: - case Op_VectorCastB2X: - case Op_VectorCastD2X: - case Op_VectorCastF2X: - case Op_VectorCastI2X: - case Op_VectorCastL2X: - case Op_VectorCastS2X: case Op_VectorInsert: - case Op_VectorLoadShuffle: - case Op_VectorRearrange: - case Op_VectorReinterpret: case Op_VectorTest: case Op_PopCountVI: case Op_PopCountVL: @@ -106,7 +96,7 @@ instruct loadV(vReg dst, vmemA mem) %{ ins_encode %{ VectorRegister dst_reg = as_VectorRegister($dst$$reg); loadStore(C2_MacroAssembler(&cbuf), false, dst_reg, - Matcher::vector_element_basic_type(this), as_Register($mem$$base), Matcher::vector_length_in_bytes(this)); + Matcher::vector_element_basic_type(this), as_Register($mem$$base), Matcher::vector_length(this)); %} ins_pipe(pipe_slow); %} @@ -118,7 +108,7 @@ instruct storeV(vReg src, vmemA mem) %{ ins_encode %{ VectorRegister src_reg = as_VectorRegister($src$$reg); loadStore(C2_MacroAssembler(&cbuf), true, src_reg, - Matcher::vector_element_basic_type(this, $src), as_Register($mem$$base), Matcher::vector_length_in_bytes(this, $src)); + Matcher::vector_element_basic_type(this, $src), as_Register($mem$$base), Matcher::vector_length(this, $src)); %} ins_pipe(pipe_slow); %} @@ -129,7 +119,7 @@ instruct vloadmask(vRegMask dst, vReg src) %{ match(Set dst (VectorLoadMask src)); format %{ "vloadmask $dst, $src" %} ins_encode %{ - __ rvv_vsetvli(T_BOOLEAN, Matcher::vector_length(this)); + __ vsetvli_helper(T_BOOLEAN, Matcher::vector_length(this)); __ vmsne_vx(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), zr); %} ins_pipe(pipe_slow); @@ -139,7 +129,7 @@ instruct vloadmask_masked(vRegMask dst, vReg src, vRegMask_V0 v0) %{ match(Set dst (VectorLoadMask src v0)); format %{ "vloadmask_masked $dst, $src, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_BOOLEAN, Matcher::vector_length(this)); + __ vsetvli_helper(T_BOOLEAN, Matcher::vector_length(this)); __ vmsne_vx(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), zr, Assembler::v0_t); %} ins_pipe(pipe_slow); @@ -150,9 +140,10 @@ instruct vloadmask_masked(vRegMask dst, vReg src, vRegMask_V0 v0) %{ instruct vstoremask(vReg dst, vRegMask_V0 v0, immI size) %{ match(Set dst (VectorStoreMask v0 size)); format %{ "vstoremask $dst, V0" %} + format %{ "vstoremask $dst, V0 # elem size is $size byte[s]" %} ins_encode %{ - __ rvv_vsetvli(T_BOOLEAN, Matcher::vector_length(this)); - __ vmv_v_x(as_VectorRegister($dst$$reg), zr); + __ vsetvli_helper(T_BOOLEAN, Matcher::vector_length(this)); + __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); __ vmerge_vim(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), 1); %} ins_pipe(pipe_slow); @@ -169,8 +160,8 @@ instruct vmaskcmp(vRegMask dst, vReg src1, vReg src2, immI cond) %{ format %{ "vmaskcmp $dst, $src1, $src2, $cond" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - __ compare_integral_v(as_VectorRegister($dst$$reg), bt, length_in_bytes, as_VectorRegister($src1$$reg), + uint vector_length = Matcher::vector_length(this); + __ compare_integral_v(as_VectorRegister($dst$$reg), bt, vector_length, as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), (int)($cond$$constant)); %} ins_pipe(pipe_slow); @@ -186,8 +177,8 @@ instruct vmaskcmp_masked(vRegMask dst, vReg src1, vReg src2, immI cond, vRegMask format %{ "vmaskcmp_masked $dst, $src1, $src2, $cond, $v0" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - __ compare_integral_v(as_VectorRegister($dst$$reg), bt, length_in_bytes, as_VectorRegister($src1$$reg), + uint vector_length = Matcher::vector_length(this); + __ compare_integral_v(as_VectorRegister($dst$$reg), bt, vector_length, as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), (int)($cond$$constant), Assembler::v0_t); %} ins_pipe(pipe_slow); @@ -203,8 +194,8 @@ instruct vmaskcmp_fp(vRegMask dst, vReg src1, vReg src2, immI cond, vRegMask_V0 format %{ "vmaskcmp_fp $dst, $src1, $src2, $cond\t# KILL $tmp1, $tmp2" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - __ compare_floating_point_v(as_VectorRegister($dst$$reg), bt, length_in_bytes, + uint vector_length = Matcher::vector_length(this); + __ compare_floating_point_v(as_VectorRegister($dst$$reg), bt, vector_length, as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), as_VectorRegister($v0$$reg), (int)($cond$$constant)); @@ -220,8 +211,8 @@ instruct vmaskcmp_fp_masked(vRegMask dst, vReg src1, vReg src2, immI cond, vRegM format %{ "vmaskcmp_fp_masked $dst, $src1, $src2, $cond, $vmask\t# KILL $tmp1, $tmp2, $v0" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - uint length_in_bytes = Matcher::vector_length_in_bytes(this); - __ compare_floating_point_v(as_VectorRegister($dst$$reg), bt, length_in_bytes, + uint vector_length = Matcher::vector_length(this); + __ compare_floating_point_v(as_VectorRegister($dst$$reg), bt, vector_length, as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), as_VectorRegister($vmask$$reg), (int)($cond$$constant), Assembler::v0_t); @@ -238,7 +229,7 @@ instruct vabsB(vReg dst, vReg src, vReg tmp) %{ format %{ "vrsub.vi $tmp, 0, $src\t#@vabsB\n\t" "vmax.vv $dst, $tmp, $src" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vrsub_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg), 0); __ vmax_vv(as_VectorRegister($dst$$reg), as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg)); %} @@ -252,7 +243,7 @@ instruct vabsS(vReg dst, vReg src, vReg tmp) %{ format %{ "vrsub.vi $tmp, 0, $src\t#@vabsS\n\t" "vmax.vv $dst, $tmp, $src" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vrsub_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg), 0); __ vmax_vv(as_VectorRegister($dst$$reg), as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg)); %} @@ -266,7 +257,7 @@ instruct vabsI(vReg dst, vReg src, vReg tmp) %{ format %{ "vrsub.vi $tmp, 0, $src\t#@vabsI\n\t" "vmax.vv $dst, $tmp, $src" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vrsub_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg), 0); __ vmax_vv(as_VectorRegister($dst$$reg), as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg)); %} @@ -280,7 +271,7 @@ instruct vabsL(vReg dst, vReg src, vReg tmp) %{ format %{ "vrsub.vi $tmp, 0, $src\t#@vabsL\n\t" "vmax.vv $dst, $tmp, $src" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vrsub_vi(as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg), 0); __ vmax_vv(as_VectorRegister($dst$$reg), as_VectorRegister($tmp$$reg), as_VectorRegister($src$$reg)); %} @@ -292,7 +283,7 @@ instruct vabsF(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsgnjx.vv $dst, $src, $src, vm\t#@vabsF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfsgnjx_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -303,7 +294,7 @@ instruct vabsD(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsgnjx.vv $dst, $src, $src, vm\t#@vabsD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfsgnjx_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -316,7 +307,7 @@ instruct vaddB(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vadd.vv $dst, $src1, $src2\t#@vaddB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -329,7 +320,7 @@ instruct vaddS(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vadd.vv $dst, $src1, $src2\t#@vaddS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -342,7 +333,7 @@ instruct vaddI(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vadd.vv $dst, $src1, $src2\t#@vaddI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -355,7 +346,7 @@ instruct vaddL(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vadd.vv $dst, $src1, $src2\t#@vaddL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -368,7 +359,7 @@ instruct vaddF(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfadd.vv $dst, $src1, $src2\t#@vaddF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -381,7 +372,7 @@ instruct vaddD(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfadd.vv $dst, $src1, $src2\t#@vaddD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfadd_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -400,7 +391,7 @@ instruct vadd_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vadd.vv $dst_src1, $src2, $v0\t#@vadd_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vadd_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); @@ -415,7 +406,7 @@ instruct vadd_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vfadd.vv $dst_src1, $src2, $v0\t#@vadd_fp_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vfadd_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); @@ -431,7 +422,7 @@ instruct vand(vReg dst, vReg src1, vReg src2) %{ format %{ "vand.vv $dst, $src1, $src2\t#@vand" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vand_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -447,7 +438,7 @@ instruct vor(vReg dst, vReg src1, vReg src2) %{ format %{ "vor.vv $dst, $src1, $src2\t#@vor" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -463,7 +454,7 @@ instruct vxor(vReg dst, vReg src1, vReg src2) %{ format %{ "vxor.vv $dst, $src1, $src2\t#@vxor" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -478,7 +469,7 @@ instruct vdivF(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfdiv.vv $dst, $src1, $src2\t#@vdivF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfdiv_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -491,7 +482,7 @@ instruct vdivD(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfdiv.vv $dst, $src1, $src2\t#@vdivD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfdiv_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -508,7 +499,7 @@ instruct vdiv_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vfdiv.vv $dst_src1, $src2, $v0\t#@vdiv_fp_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vfdiv_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); @@ -526,7 +517,7 @@ instruct vmax(vReg dst, vReg src1, vReg src2) %{ format %{ "vmax.vv $dst, $src1, $src2\t#@vmax" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmax_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -541,7 +532,7 @@ instruct vmin(vReg dst, vReg src1, vReg src2) %{ format %{ "vmin.vv $dst, $src1, $src2\t#@vmin" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmin_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -559,7 +550,7 @@ instruct vmaxF(vReg dst, vReg src1, vReg src2) %{ ins_encode %{ __ minmax_fp_v(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), - false /* is_double */, false /* is_min */, Matcher::vector_length_in_bytes(this)); + false /* is_double */, false /* is_min */, Matcher::vector_length(this)); %} ins_pipe(pipe_slow); %} @@ -573,7 +564,7 @@ instruct vmaxD(vReg dst, vReg src1, vReg src2) %{ ins_encode %{ __ minmax_fp_v(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), - true /* is_double */, false /* is_min */, Matcher::vector_length_in_bytes(this)); + true /* is_double */, false /* is_min */, Matcher::vector_length(this)); %} ins_pipe(pipe_slow); %} @@ -587,7 +578,7 @@ instruct vminF(vReg dst, vReg src1, vReg src2) %{ ins_encode %{ __ minmax_fp_v(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), - false /* is_double */, true /* is_min */, Matcher::vector_length_in_bytes(this)); + false /* is_double */, true /* is_min */, Matcher::vector_length(this)); %} ins_pipe(pipe_slow); %} @@ -601,7 +592,7 @@ instruct vminD(vReg dst, vReg src1, vReg src2) %{ ins_encode %{ __ minmax_fp_v(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg), - true /* is_double */, true /* is_min */, Matcher::vector_length_in_bytes(this)); + true /* is_double */, true /* is_min */, Matcher::vector_length(this)); %} ins_pipe(pipe_slow); %} @@ -615,7 +606,7 @@ instruct vfmlaF(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfmacc.vv $dst_src1, $src2, $src3\t#@vfmlaF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -629,7 +620,7 @@ instruct vfmlaD(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfmacc.vv $dst_src1, $src2, $src3\t#@vfmlaD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -647,7 +638,7 @@ instruct vfmlsF(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfnmsac.vv $dst_src1, $src2, $src3\t#@vfmlsF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -663,7 +654,7 @@ instruct vfmlsD(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfnmsac.vv $dst_src1, $src2, $src3\t#@vfmlsD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -681,7 +672,7 @@ instruct vfnmlaF(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfnmacc.vv $dst_src1, $src2, $src3\t#@vfnmlaF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfnmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -697,7 +688,7 @@ instruct vfnmlaD(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfnmacc.vv $dst_src1, $src2, $src3\t#@vfnmlaD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfnmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -713,7 +704,7 @@ instruct vfnmlsF(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfmsac.vv $dst_src1, $src2, $src3\t#@vfnmlsF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -727,7 +718,7 @@ instruct vfnmlsD(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vfmsac.vv $dst_src1, $src2, $src3\t#@vfnmlsD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -742,7 +733,7 @@ instruct vmlaB(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vmacc.vv $dst_src1, src2, src3\t#@vmlaB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -755,7 +746,7 @@ instruct vmlaS(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vmacc.vv $dst_src1, src2, src3\t#@vmlaS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -768,7 +759,7 @@ instruct vmlaI(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vmacc.vv $dst_src1, src2, src3\t#@vmlaI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -781,7 +772,7 @@ instruct vmlaL(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vmacc.vv $dst_src1, src2, src3\t#@vmlaL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vmacc_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -796,7 +787,7 @@ instruct vmlsB(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vnmsac.vv $dst_src1, src2, src3\t#@vmlsB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -809,7 +800,7 @@ instruct vmlsS(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vnmsac.vv $dst_src1, src2, src3\t#@vmlsS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -822,7 +813,7 @@ instruct vmlsI(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vnmsac.vv $dst_src1, src2, src3\t#@vmlsI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -835,7 +826,7 @@ instruct vmlsL(vReg dst_src1, vReg src2, vReg src3) %{ ins_cost(VEC_COST); format %{ "vnmsac.vv $dst_src1, src2, src3\t#@vmlsL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vnmsac_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($src3$$reg)); %} @@ -849,7 +840,7 @@ instruct vmulB(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vmul.vv $dst, $src1, $src2\t#@vmulB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -861,7 +852,7 @@ instruct vmulS(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vmul.vv $dst, $src1, $src2\t#@vmulS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -873,7 +864,7 @@ instruct vmulI(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vmul.vv $dst, $src1, $src2\t#@vmulI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -885,7 +876,7 @@ instruct vmulL(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vmul.vv $dst, $src1, $src2\t#@vmulL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -897,7 +888,7 @@ instruct vmulF(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfmul.vv $dst, $src1, $src2\t#@vmulF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -909,7 +900,7 @@ instruct vmulD(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfmul.vv $dst, $src1, $src2\t#@vmulD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfmul_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -927,7 +918,7 @@ instruct vmul_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vmul.vv $dst_src1, $src2, $v0\t#@vmul_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmul_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); %} @@ -941,7 +932,7 @@ instruct vmul_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vmul.vv $dst_src1, $src2, $v0\t#@vmul_fp_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vfmul_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); %} @@ -956,7 +947,7 @@ instruct vnegI(vReg dst, vReg src) %{ format %{ "vrsub.vx $dst, $src, $src\t#@vnegI" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -967,7 +958,7 @@ instruct vnegL(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vrsub.vx $dst, $src, $src\t#@vnegL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -980,7 +971,7 @@ instruct vnegF(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsgnjn.vv $dst, $src, $src\t#@vnegF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -991,7 +982,7 @@ instruct vnegD(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsgnjn.vv $dst, $src, $src\t#@vnegD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfneg_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -1011,9 +1002,9 @@ instruct reduce_andI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1028,9 +1019,9 @@ instruct reduce_andL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1049,9 +1040,9 @@ instruct reduce_orI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1066,9 +1057,9 @@ instruct reduce_orL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1087,9 +1078,9 @@ instruct reduce_xorI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1104,9 +1095,9 @@ instruct reduce_xorL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1125,9 +1116,9 @@ instruct reduce_addI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1142,9 +1133,9 @@ instruct reduce_addL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ "vmv.x.s $dst, $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1157,7 +1148,7 @@ instruct reduce_addF(fRegF src1_dst, vReg src2, vReg tmp) %{ "vfredosum.vs $tmp, $src2, $tmp\n\t" "vfmv.f.s $src1_dst, $tmp" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this, $src2)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this, $src2)); __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister); __ vfredosum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg)); @@ -1174,7 +1165,7 @@ instruct reduce_addD(fRegD src1_dst, vReg src2, vReg tmp) %{ "vfredosum.vs $tmp, $src2, $tmp\n\t" "vfmv.f.s $src1_dst, $tmp" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this, $src2)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this, $src2)); __ vfmv_s_f(as_VectorRegister($tmp$$reg), $src1_dst$$FloatRegister); __ vfredosum_vs(as_VectorRegister($tmp$$reg), as_VectorRegister($src2$$reg), as_VectorRegister($tmp$$reg)); @@ -1195,9 +1186,9 @@ instruct vreduce_maxI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ format %{ "vreduce_maxI $dst, $src1, $src2\t# KILL $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1210,9 +1201,9 @@ instruct vreduce_maxL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ format %{ "vreduce_maxL $dst, $src1, $src2\t# KILL $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1229,9 +1220,9 @@ instruct vreduce_minI(iRegINoSp dst, iRegIorL2I src1, vReg src2, vReg tmp) %{ format %{ "vreduce_minI $dst, $src1, $src2\t# KILL $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1244,9 +1235,9 @@ instruct vreduce_minL(iRegLNoSp dst, iRegL src1, vReg src2, vReg tmp) %{ format %{ "vreduce_minL $dst, $src1, $src2\t# KILL $tmp" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this, $src2); - __ rvv_reduce_integral($dst$$Register, as_VectorRegister($tmp$$reg), - $src1$$Register, as_VectorRegister($src2$$reg), bt, - this->ideal_Opcode(), Matcher::vector_length_in_bytes(this, $src2)); + __ reduce_integral_v($dst$$Register, as_VectorRegister($tmp$$reg), + $src1$$Register, as_VectorRegister($src2$$reg), bt, + this->ideal_Opcode(), Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1263,7 +1254,7 @@ instruct vreduce_maxF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{ __ reduce_minmax_fp_v($dst$$FloatRegister, $src1$$FloatRegister, as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), - false /* is_double */, false /* is_min */, Matcher::vector_length_in_bytes(this, $src2)); + false /* is_double */, false /* is_min */, Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1278,7 +1269,7 @@ instruct vreduce_maxD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{ __ reduce_minmax_fp_v($dst$$FloatRegister, $src1$$FloatRegister, as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), - true /* is_double */, false /* is_min */, Matcher::vector_length_in_bytes(this, $src2)); + true /* is_double */, false /* is_min */, Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1295,7 +1286,7 @@ instruct vreduce_minF(fRegF dst, fRegF src1, vReg src2, vReg tmp1, vReg tmp2) %{ __ reduce_minmax_fp_v($dst$$FloatRegister, $src1$$FloatRegister, as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), - false /* is_double */, true /* is_min */, Matcher::vector_length_in_bytes(this, $src2)); + false /* is_double */, true /* is_min */, Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1310,35 +1301,7 @@ instruct vreduce_minD(fRegD dst, fRegD src1, vReg src2, vReg tmp1, vReg tmp2) %{ __ reduce_minmax_fp_v($dst$$FloatRegister, $src1$$FloatRegister, as_VectorRegister($src2$$reg), as_VectorRegister($tmp1$$reg), as_VectorRegister($tmp2$$reg), - true /* is_double */, true /* is_min */, Matcher::vector_length_in_bytes(this, $src2)); - %} - ins_pipe(pipe_slow); -%} - -// vector Math.rint, floor, ceil - -instruct vroundD(vReg dst, vReg src, immI rmode) %{ - predicate(Matcher::vector_element_basic_type(n) == T_DOUBLE); - match(Set dst (RoundDoubleModeV src rmode)); - format %{ "vroundD $dst, $src, $rmode" %} - ins_encode %{ - switch ($rmode$$constant) { - case RoundDoubleModeNode::rmode_rint: - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); - __ vfcvt_rtz_x_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); - break; - case RoundDoubleModeNode::rmode_floor: - __ csrwi(CSR_FRM, C2_MacroAssembler::rdn); - __ vfcvt_rtz_x_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); - break; - case RoundDoubleModeNode::rmode_ceil: - __ csrwi(CSR_FRM, C2_MacroAssembler::rup); - __ vfcvt_rtz_x_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); - break; - default: - ShouldNotReachHere(); - break; - } + true /* is_double */, true /* is_min */, Matcher::vector_length(this, $src2)); %} ins_pipe(pipe_slow); %} @@ -1350,7 +1313,7 @@ instruct replicateB(vReg dst, iRegIorL2I src) %{ ins_cost(VEC_COST); format %{ "vmv.v.x $dst, $src\t#@replicateB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); %} ins_pipe(pipe_slow); @@ -1361,7 +1324,7 @@ instruct replicateS(vReg dst, iRegIorL2I src) %{ ins_cost(VEC_COST); format %{ "vmv.v.x $dst, $src\t#@replicateS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); %} ins_pipe(pipe_slow); @@ -1372,7 +1335,7 @@ instruct replicateI(vReg dst, iRegIorL2I src) %{ ins_cost(VEC_COST); format %{ "vmv.v.x $dst, $src\t#@replicateI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); %} ins_pipe(pipe_slow); @@ -1383,7 +1346,7 @@ instruct replicateL(vReg dst, iRegL src) %{ ins_cost(VEC_COST); format %{ "vmv.v.x $dst, $src\t#@replicateL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); %} ins_pipe(pipe_slow); @@ -1394,7 +1357,7 @@ instruct replicateB_imm5(vReg dst, immI5 con) %{ ins_cost(VEC_COST); format %{ "vmv.v.i $dst, $con\t#@replicateB_imm5" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vmv_v_i(as_VectorRegister($dst$$reg), $con$$constant); %} ins_pipe(pipe_slow); @@ -1405,7 +1368,7 @@ instruct replicateS_imm5(vReg dst, immI5 con) %{ ins_cost(VEC_COST); format %{ "vmv.v.i $dst, $con\t#@replicateS_imm5" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vmv_v_i(as_VectorRegister($dst$$reg), $con$$constant); %} ins_pipe(pipe_slow); @@ -1416,7 +1379,7 @@ instruct replicateI_imm5(vReg dst, immI5 con) %{ ins_cost(VEC_COST); format %{ "vmv.v.i $dst, $con\t#@replicateI_imm5" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vmv_v_i(as_VectorRegister($dst$$reg), $con$$constant); %} ins_pipe(pipe_slow); @@ -1427,7 +1390,7 @@ instruct replicateL_imm5(vReg dst, immL5 con) %{ ins_cost(VEC_COST); format %{ "vmv.v.i $dst, $con\t#@replicateL_imm5" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vmv_v_i(as_VectorRegister($dst$$reg), $con$$constant); %} ins_pipe(pipe_slow); @@ -1438,7 +1401,7 @@ instruct replicateF(vReg dst, fRegF src) %{ ins_cost(VEC_COST); format %{ "vfmv.v.f $dst, $src\t#@replicateF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfmv_v_f(as_VectorRegister($dst$$reg), $src$$FloatRegister); %} ins_pipe(pipe_slow); @@ -1449,7 +1412,7 @@ instruct replicateD(vReg dst, fRegD src) %{ ins_cost(VEC_COST); format %{ "vfmv.v.f $dst, $src\t#@replicateD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfmv_v_f(as_VectorRegister($dst$$reg), $src$$FloatRegister); %} ins_pipe(pipe_slow); @@ -1463,7 +1426,7 @@ instruct vasrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vasrB $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); // if shift > BitsPerByte - 1, clear the low BitsPerByte - 1 bits __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); __ vsra_vi(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1482,7 +1445,7 @@ instruct vasrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vasrS $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); // if shift > BitsPerShort - 1, clear the low BitsPerShort - 1 bits __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); __ vsra_vi(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1500,7 +1463,7 @@ instruct vasrI(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vasrI $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsra_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1512,7 +1475,7 @@ instruct vasrL(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vasrL $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsra_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1525,7 +1488,7 @@ instruct vasrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vasrB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); // if shift > BitsPerByte - 1, clear the low BitsPerByte - 1 bits __ vmerge_vim(as_VectorRegister($shift$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); @@ -1543,7 +1506,7 @@ instruct vasrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vasrS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); // if shift > BitsPerShort - 1, clear the low BitsPerShort - 1 bits __ vmerge_vim(as_VectorRegister($shift$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); @@ -1561,7 +1524,7 @@ instruct vasrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vasrI_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsra_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1574,7 +1537,7 @@ instruct vasrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vasrL_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsra_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1587,7 +1550,7 @@ instruct vlslB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vlslB $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); // if shift > BitsPerByte - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1606,7 +1569,7 @@ instruct vlslS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vlslS $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); // if shift > BitsPerShort - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1624,7 +1587,7 @@ instruct vlslI(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vlslI $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsll_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1636,7 +1599,7 @@ instruct vlslL(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vlslL $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsll_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1649,7 +1612,7 @@ instruct vlslB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vlslB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); // if shift > BitsPerByte - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); __ vmand_mm(as_VectorRegister($v0$$reg), as_VectorRegister($v0$$reg), @@ -1670,7 +1633,7 @@ instruct vlslS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vlslS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); // if shift > BitsPerShort - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); __ vmand_mm(as_VectorRegister($v0$$reg), as_VectorRegister($v0$$reg), @@ -1691,7 +1654,7 @@ instruct vlslI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vlslI_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsll_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1704,7 +1667,7 @@ instruct vlslL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vlslL_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsll_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1717,7 +1680,7 @@ instruct vlsrB(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vlsrB $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); // if shift > BitsPerByte - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1736,7 +1699,7 @@ instruct vlsrS(vReg dst, vReg src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst, TEMP v0); format %{ "vlsrS $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); // if shift > BitsPerShort - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), @@ -1754,7 +1717,7 @@ instruct vlsrI(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vlsrI $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsrl_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1766,7 +1729,7 @@ instruct vlsrL(vReg dst, vReg src, vReg shift) %{ ins_cost(VEC_COST); format %{ "vlsrL $dst, $src, $shift" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsrl_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shift$$reg)); %} @@ -1779,7 +1742,7 @@ instruct vlsrB_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vlsrB_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); // if shift > BitsPerByte - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerByte - 1); __ vmand_mm(as_VectorRegister($v0$$reg), as_VectorRegister($v0$$reg), @@ -1800,7 +1763,7 @@ instruct vlsrS_masked(vReg dst_src, vReg shift, vRegMask vmask, vRegMask_V0 v0) effect(TEMP_DEF dst_src, TEMP v0); format %{ "vlsrS_masked $dst_src, $dst_src, $shift, $vmask\t# KILL $v0" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); // if shift > BitsPerShort - 1, clear the element __ vmsgtu_vi(as_VectorRegister($v0$$reg), as_VectorRegister($shift$$reg), BitsPerShort - 1); __ vmand_mm(as_VectorRegister($v0$$reg), as_VectorRegister($v0$$reg), @@ -1821,7 +1784,7 @@ instruct vlsrI_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vlsrI_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsrl_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1834,7 +1797,7 @@ instruct vlsrL_masked(vReg dst_src, vReg shift, vRegMask_V0 v0) %{ effect(TEMP_DEF dst_src); format %{ "vlsrL_masked $dst_src, $dst_src, $shift, $v0" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsrl_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), as_VectorRegister($shift$$reg), Assembler::v0_t); %} @@ -1847,7 +1810,7 @@ instruct vasrB_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsra.vi $dst, $src, $shift\t#@vasrB_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1865,7 +1828,7 @@ instruct vasrS_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsra.vi $dst, $src, $shift\t#@vasrS_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1883,7 +1846,7 @@ instruct vasrI_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vasrI_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1901,7 +1864,7 @@ instruct vasrL_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vasrL_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1918,7 +1881,7 @@ instruct vlsrB_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrB_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1940,7 +1903,7 @@ instruct vlsrS_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrS_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1962,7 +1925,7 @@ instruct vlsrI_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrI_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1980,7 +1943,7 @@ instruct vlsrL_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsrl.vi $dst, $src, $shift\t#@vlsrL_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); if (con == 0) { __ vor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -1997,7 +1960,7 @@ instruct vlslB_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsll.vi $dst, $src, $shift\t#@vlslB_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); if (con >= BitsPerByte) { __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -2014,7 +1977,7 @@ instruct vlslS_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsll.vi $dst, $src, $shift\t#@vlslS_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); if (con >= BitsPerShort) { __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); @@ -2031,7 +1994,7 @@ instruct vlslI_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsll.vi $dst, $src, $shift\t#@vlslI_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsll_vi(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), con); %} ins_pipe(pipe_slow); @@ -2044,56 +2007,21 @@ instruct vlslL_imm(vReg dst, vReg src, immI shift) %{ format %{ "vsll.vi $dst, $src, $shift\t#@vlslL_imm" %} ins_encode %{ uint32_t con = (unsigned)$shift$$constant & 0x1f; - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsll_vi(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), con); %} ins_pipe(pipe_slow); %} -instruct vshiftcntB(vReg dst, iRegIorL2I cnt) %{ - predicate(Matcher::vector_element_basic_type(n) == T_BYTE); - match(Set dst (LShiftCntV cnt)); - match(Set dst (RShiftCntV cnt)); - format %{ "vmv.v.x $dst, $cnt\t#@vshiftcntB" %} - ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); - __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($cnt$$reg)); - %} - ins_pipe(pipe_slow); -%} +// vector shift count -instruct vshiftcntS(vReg dst, iRegIorL2I cnt) %{ - predicate(Matcher::vector_element_basic_type(n) == T_SHORT || - Matcher::vector_element_basic_type(n) == T_CHAR); +instruct vshiftcnt(vReg dst, iRegIorL2I cnt) %{ match(Set dst (LShiftCntV cnt)); match(Set dst (RShiftCntV cnt)); - format %{ "vmv.v.x $dst, $cnt\t#@vshiftcntS" %} + format %{ "vshiftcnt $dst, $cnt" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); - __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($cnt$$reg)); - %} - ins_pipe(pipe_slow); -%} - -instruct vshiftcntI(vReg dst, iRegIorL2I cnt) %{ - predicate(Matcher::vector_element_basic_type(n) == T_INT); - match(Set dst (LShiftCntV cnt)); - match(Set dst (RShiftCntV cnt)); - format %{ "vmv.v.x $dst, $cnt\t#@vshiftcntI" %} - ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); - __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($cnt$$reg)); - %} - ins_pipe(pipe_slow); -%} - -instruct vshiftcntL(vReg dst, iRegIorL2I cnt) %{ - predicate(Matcher::vector_element_basic_type(n) == T_LONG); - match(Set dst (LShiftCntV cnt)); - match(Set dst (RShiftCntV cnt)); - format %{ "vmv.v.x $dst, $cnt\t#@vshiftcntL" %} - ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + BasicType bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($cnt$$reg)); %} ins_pipe(pipe_slow); @@ -2106,7 +2034,7 @@ instruct vsqrtF(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsqrt.v $dst, $src\t#@vsqrtF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfsqrt_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -2117,7 +2045,7 @@ instruct vsqrtD(vReg dst, vReg src) %{ ins_cost(VEC_COST); format %{ "vfsqrt.v $dst, $src\t#@vsqrtD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfsqrt_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -2130,7 +2058,7 @@ instruct vsubB(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vsub.vv $dst, $src1, $src2\t#@vsubB" %} ins_encode %{ - __ rvv_vsetvli(T_BYTE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this)); __ vsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2142,7 +2070,7 @@ instruct vsubS(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vsub.vv $dst, $src1, $src2\t#@vsubS" %} ins_encode %{ - __ rvv_vsetvli(T_SHORT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this)); __ vsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2154,7 +2082,7 @@ instruct vsubI(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vsub.vv $dst, $src1, $src2\t#@vsubI" %} ins_encode %{ - __ rvv_vsetvli(T_INT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_INT, Matcher::vector_length(this)); __ vsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2166,7 +2094,7 @@ instruct vsubL(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vsub.vv $dst, $src1, $src2\t#@vsubL" %} ins_encode %{ - __ rvv_vsetvli(T_LONG, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); __ vsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2178,7 +2106,7 @@ instruct vsubF(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfsub.vv $dst, $src1, $src2\t@vsubF" %} ins_encode %{ - __ rvv_vsetvli(T_FLOAT, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); __ vfsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2190,7 +2118,7 @@ instruct vsubD(vReg dst, vReg src1, vReg src2) %{ ins_cost(VEC_COST); format %{ "vfsub.vv $dst, $src1, $src2\t#@vsubD" %} ins_encode %{ - __ rvv_vsetvli(T_DOUBLE, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); __ vfsub_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} @@ -2208,7 +2136,7 @@ instruct vsub_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vsub.vv $dst_src1, $src2, $v0\t#@vsub_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vsub_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); %} @@ -2222,7 +2150,7 @@ instruct vsub_fp_masked(vReg dst_src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vfsub.vv $dst_src1, $src2, $v0\t#@vsub_fp_masked" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vfsub_vv(as_VectorRegister($dst_src1$$reg), as_VectorRegister($dst_src1$$reg), as_VectorRegister($src2$$reg), Assembler::v0_t); %} @@ -2496,9 +2424,10 @@ instruct vloadcon(vReg dst, immI0 src) %{ format %{ "vloadcon $dst\t# generate iota indices" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vid_v(as_VectorRegister($dst$$reg)); if (is_floating_point_type(bt)) { + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); } %} @@ -2534,7 +2463,7 @@ instruct vmask_gen_imm(vRegMask dst, immL con) %{ format %{ "vmask_gen_imm $dst, $con" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, (uint)($con$$constant)); + __ vsetvli_helper(bt, (uint)($con$$constant)); __ vmset_m(as_VectorRegister($dst$$reg)); %} ins_pipe(pipe_slow); @@ -2545,7 +2474,7 @@ instruct vmaskAll_immI(vRegMask dst, immI src) %{ format %{ "vmaskAll_immI $dst, $src" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); int con = (int)$src$$constant; if (con == 0) { __ vmclr_m(as_VectorRegister($dst$$reg)); @@ -2562,7 +2491,7 @@ instruct vmaskAllI(vRegMask dst, iRegI src) %{ format %{ "vmaskAllI $dst, $src" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); __ vmsne_vx(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), zr); %} @@ -2574,7 +2503,7 @@ instruct vmaskAll_immL(vRegMask dst, immL src) %{ format %{ "vmaskAll_immL $dst, $src" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); long con = (long)$src$$constant; if (con == 0) { __ vmclr_m(as_VectorRegister($dst$$reg)); @@ -2591,7 +2520,7 @@ instruct vmaskAllL(vRegMask dst, iRegL src) %{ format %{ "vmaskAllL $dst, $src" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmv_v_x(as_VectorRegister($dst$$reg), as_Register($src$$reg)); __ vmsne_vx(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), zr); %} @@ -2607,7 +2536,7 @@ instruct vmask_and(vRegMask dst, vRegMask src1, vRegMask src2) %{ format %{ "vmask_and $dst, $src1, $src2" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmand_mm(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -2620,7 +2549,7 @@ instruct vmask_or(vRegMask dst, vRegMask src1, vRegMask src2) %{ format %{ "vmask_or $dst, $src1, $src2" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmor_mm(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -2633,7 +2562,7 @@ instruct vmask_xor(vRegMask dst, vRegMask src1, vRegMask src2) %{ format %{ "vmask_xor $dst, $src1, $src2" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmxor_mm(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); @@ -2658,7 +2587,7 @@ instruct loadV_masked(vReg dst, vmemA mem, vRegMask_V0 v0) %{ VectorRegister dst_reg = as_VectorRegister($dst$$reg); loadStore(C2_MacroAssembler(&cbuf), false, dst_reg, Matcher::vector_element_basic_type(this), as_Register($mem$$base), - Matcher::vector_length_in_bytes(this), Assembler::v0_t); + Matcher::vector_length(this), Assembler::v0_t); %} ins_pipe(pipe_slow); %} @@ -2670,7 +2599,7 @@ instruct storeV_masked(vReg src, vmemA mem, vRegMask_V0 v0) %{ VectorRegister src_reg = as_VectorRegister($src$$reg); loadStore(C2_MacroAssembler(&cbuf), true, src_reg, Matcher::vector_element_basic_type(this, $src), as_Register($mem$$base), - Matcher::vector_length_in_bytes(this, $src), Assembler::v0_t); + Matcher::vector_length(this, $src), Assembler::v0_t); %} ins_pipe(pipe_slow); %} @@ -2682,9 +2611,347 @@ instruct vblend(vReg dst, vReg src1, vReg src2, vRegMask_V0 v0) %{ format %{ "vmerge_vvm $dst, $src1, $src2, v0\t#@vector blend" %} ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); - __ rvv_vsetvli(bt, Matcher::vector_length_in_bytes(this)); + __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vmerge_vvm(as_VectorRegister($dst$$reg), as_VectorRegister($src1$$reg), as_VectorRegister($src2$$reg)); %} ins_pipe(pipe_slow); +%} + +// ------------------------------ Vector cast ---------------------------------- + +// VectorCastB2X + +instruct vcvtBtoX(vReg dst, vReg src) %{ + match(Set dst (VectorCastB2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtBtoX $dst, $src" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + if (is_floating_point_type(bt)) { + __ integer_extend_v(as_VectorRegister($dst$$reg), bt == T_FLOAT ? T_INT : T_LONG, + Matcher::vector_length(this), as_VectorRegister($src$$reg), T_BYTE); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); + } else { + __ integer_extend_v(as_VectorRegister($dst$$reg), bt, + Matcher::vector_length(this), as_VectorRegister($src$$reg), T_BYTE); + } + %} + ins_pipe(pipe_slow); +%} + +// VectorCastS2X + +instruct vcvtStoB(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_BYTE); + match(Set dst (VectorCastS2X src)); + format %{ "vcvtStoB $dst, $src" %} + ins_encode %{ + __ integer_narrow_v(as_VectorRegister($dst$$reg), T_BYTE, Matcher::vector_length(this), + as_VectorRegister($src$$reg), T_SHORT); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtStoX_extend(vReg dst, vReg src) %{ + predicate((Matcher::vector_element_basic_type(n) == T_INT || + Matcher::vector_element_basic_type(n) == T_LONG)); + match(Set dst (VectorCastS2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtStoX_extend $dst, $src" %} + ins_encode %{ + __ integer_extend_v(as_VectorRegister($dst$$reg), Matcher::vector_element_basic_type(this), + Matcher::vector_length(this), as_VectorRegister($src$$reg), T_SHORT); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtStoX_fp_extend(vReg dst, vReg src) %{ + predicate((Matcher::vector_element_basic_type(n) == T_FLOAT || + Matcher::vector_element_basic_type(n) == T_DOUBLE)); + match(Set dst (VectorCastS2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtStoX_fp_extend $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this), Assembler::mf2); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfwcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + if (Matcher::vector_element_basic_type(this) == T_DOUBLE) { + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); + __ vfwcvt_f_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); + } + %} + ins_pipe(pipe_slow); +%} + +// VectorCastI2X + +instruct vcvtItoX_narrow(vReg dst, vReg src) %{ + predicate((Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT)); + match(Set dst (VectorCastI2X src)); + format %{ "vcvtItoX_narrow $dst, $src" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + __ integer_narrow_v(as_VectorRegister($dst$$reg), bt, Matcher::vector_length(this), + as_VectorRegister($src$$reg), T_INT); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtItoL(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_LONG); + match(Set dst (VectorCastI2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtItoL $dst, $src" %} + ins_encode %{ + __ integer_extend_v(as_VectorRegister($dst$$reg), T_LONG, + Matcher::vector_length(this), as_VectorRegister($src$$reg), T_INT); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtItoF(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_FLOAT); + match(Set dst (VectorCastI2X src)); + format %{ "vcvtItoF $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtItoD(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_DOUBLE); + match(Set dst (VectorCastI2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtItoD $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_INT, Matcher::vector_length(this), Assembler::mf2); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfwcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +// VectorCastL2X + +instruct vcvtLtoI(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_INT || + Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT); + match(Set dst (VectorCastL2X src)); + format %{ "vcvtLtoI $dst, $src" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + __ integer_narrow_v(as_VectorRegister($dst$$reg), bt, Matcher::vector_length(this), + as_VectorRegister($src$$reg), T_LONG); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtLtoF(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_FLOAT); + match(Set dst (VectorCastL2X src)); + format %{ "vcvtLtoF $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfncvt_f_x_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtLtoD(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_DOUBLE); + match(Set dst (VectorCastL2X src)); + format %{ "vcvtLtoD $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +// VectorCastF2X + +instruct vcvtFtoX_narrow(vReg dst, vReg src, vRegMask_V0 v0) %{ + predicate(Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT); + match(Set dst (VectorCastF2X src)); + effect(TEMP_DEF dst, TEMP v0); + format %{ "vcvtFtoX_narrow $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_SHORT, Matcher::vector_length(this), Assembler::mf2); + __ vfncvt_rtz_x_f_w_safe(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + if (Matcher::vector_element_basic_type(this) == T_BYTE) { + __ vsetvli_helper(T_BYTE, Matcher::vector_length(this), Assembler::mf2); + __ vncvt_x_x_w(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); + } + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtFtoI(vReg dst, vReg src, vRegMask_V0 v0) %{ + predicate(Matcher::vector_element_basic_type(n) == T_INT); + match(Set dst (VectorCastF2X src)); + effect(TEMP_DEF dst, TEMP v0); + format %{ "vcvtFtoI $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); + __ vfcvt_rtz_x_f_v_safe(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtFtoL(vReg dst, vReg src, vRegMask_V0 v0) %{ + predicate(Matcher::vector_element_basic_type(n) == T_LONG); + match(Set dst (VectorCastF2X src)); + effect(TEMP_DEF dst, TEMP v0); + format %{ "vcvtFtoL $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); + __ vfwcvt_rtz_x_f_v_safe(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtFtoD(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_DOUBLE); + match(Set dst (VectorCastF2X src)); + effect(TEMP_DEF dst); + format %{ "vcvtFtoD $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfwcvt_f_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +// VectorCastD2X + +instruct vcvtDtoX_narrow(vReg dst, vReg src, vRegMask_V0 v0) %{ + predicate(Matcher::vector_element_basic_type(n) == T_BYTE || + Matcher::vector_element_basic_type(n) == T_SHORT || + Matcher::vector_element_basic_type(n) == T_INT); + match(Set dst (VectorCastD2X src)); + effect(TEMP_DEF dst, TEMP v0); + format %{ "vcvtDtoX_narrow $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_INT, Matcher::vector_length(this), Assembler::mf2); + __ vfncvt_rtz_x_f_w_safe(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + BasicType bt = Matcher::vector_element_basic_type(this); + if (bt == T_BYTE || bt == T_SHORT) { + __ integer_narrow_v(as_VectorRegister($dst$$reg), bt, Matcher::vector_length(this), + as_VectorRegister($dst$$reg), T_INT); + } + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtDtoL(vReg dst, vReg src, vRegMask_V0 v0) %{ + predicate(Matcher::vector_element_basic_type(n) == T_LONG); + match(Set dst (VectorCastD2X src)); + effect(TEMP_DEF dst, TEMP v0); + format %{ "vcvtDtoL $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_LONG, Matcher::vector_length(this)); + __ vfcvt_rtz_x_f_v_safe(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +instruct vcvtDtoF(vReg dst, vReg src) %{ + predicate(Matcher::vector_element_basic_type(n) == T_FLOAT); + match(Set dst (VectorCastD2X src)); + format %{ "vcvtDtoF $dst, $src" %} + ins_encode %{ + __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); + __ csrwi(CSR_FRM, C2_MacroAssembler::rne); + __ vfncvt_f_f_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +// vector reinterpret + +instruct reinterpret(vReg dst_src) %{ + predicate(Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1))); + match(Set dst_src (VectorReinterpret dst_src)); + ins_cost(0); + format %{ "# reinterpret $dst_src\t# do nothing" %} + ins_encode %{ + // empty + %} + ins_pipe(pipe_class_empty); +%} + +instruct reinterpretResize(vReg dst, vReg src) %{ + predicate(Matcher::vector_length_in_bytes(n) != Matcher::vector_length_in_bytes(n->in(1))); + match(Set dst (VectorReinterpret src)); + effect(TEMP_DEF dst); + format %{ "reinterpretResize $dst, $src" %} + ins_encode %{ + uint length_in_bytes_src = Matcher::vector_length_in_bytes(this, $src); + uint length_in_bytes_dst = Matcher::vector_length_in_bytes(this); + uint length_in_bytes_resize = length_in_bytes_src < length_in_bytes_dst ? + length_in_bytes_src : length_in_bytes_dst; + assert(length_in_bytes_src <= MaxVectorSize && length_in_bytes_dst <= MaxVectorSize, + "invalid vector length"); + BasicType bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(bt, Matcher::vector_length(this)); + __ vxor_vv(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); + __ vsetvli_helper(T_BYTE, length_in_bytes_resize); + __ vmv_v_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); + %} + ins_pipe(pipe_slow); +%} + +// vector mask reinterpret + +instruct vmask_reinterpret_same_esize(vRegMask dst_src) %{ + predicate(Matcher::vector_length(n) == Matcher::vector_length(n->in(1)) && + Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1))); + match(Set dst_src (VectorReinterpret dst_src)); + ins_cost(0); + format %{ "vmask_reinterpret_same_esize $dst_src\t# do nothing" %} + ins_encode(/* empty encoding */); + ins_pipe(pipe_class_empty); +%} + +instruct vmask_reinterpret_diff_esize(vRegMask dst, vRegMask_V0 src, vReg tmp) %{ + predicate(Matcher::vector_length(n) != Matcher::vector_length(n->in(1)) && + Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1))); + match(Set dst (VectorReinterpret src)); + effect(TEMP tmp); + format %{ "vmask_reinterpret_diff_esize $dst, $src\t# KILL $tmp" %} + ins_encode %{ + BasicType from_bt = Matcher::vector_element_basic_type(this, $src); + __ vsetvli_helper(from_bt, Matcher::vector_length(this, $src)); + __ vxor_vv(as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg)); + __ vmerge_vim(as_VectorRegister($tmp$$reg), as_VectorRegister($tmp$$reg), -1); + BasicType to_bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(to_bt, Matcher::vector_length(this)); + __ vmseq_vi(as_VectorRegister($dst$$reg), as_VectorRegister($tmp$$reg), -1); + %} + ins_pipe(pipe_slow); +%} + +// ------------------------------ Vector rearrange ----------------------------- + +instruct rearrange(vReg dst, vReg src, vReg shuffle) %{ + match(Set dst (VectorRearrange src shuffle)); + effect(TEMP_DEF dst); + format %{ "rearrange $dst, $src, $shuffle" %} + ins_encode %{ + BasicType bt = Matcher::vector_element_basic_type(this); + __ vsetvli_helper(bt, Matcher::vector_length(this)); + __ vrgather_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($shuffle$$reg)); + %} + ins_pipe(pipe_slow); %} \ No newline at end of file