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8185786: AArch64: disable some address reshapings

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LoadS/LoadUS's address reshapings are disabled on Arm Cortex-A family for performance.

Reviewed-by: adinn, aph
This commit is contained in:
Zhongwei Yao 2017-08-16 14:48:41 +08:00 committed by Ningsheng Jian
parent 61a9f88ca7
commit 4ac33c1c1f
2 changed files with 24 additions and 4 deletions
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17
hotspot/src/cpu/aarch64/vm/aarch64.ad
View File

@ -3806,15 +3806,24 @@ void Compile::reshape_address(AddPNode* addp) {
// Any use that can't embed the address computation?
for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
Node* u = addp->fast_out(i);
if (!u->is_Mem() || u->is_LoadVector() || u->is_StoreVector() || u->Opcode() == Op_StoreCM) {
if (!u->is_Mem()) {
return;
}
if (u->is_LoadVector() || u->is_StoreVector() || u->Opcode() == Op_StoreCM) {
return;
}
if (addp2->in(AddPNode::Offset)->Opcode() != Op_ConvI2L) {
int scale = 1 << addp2->in(AddPNode::Offset)->in(2)->get_int();
if (VM_Version::expensive_load(u->as_Mem()->memory_size(), scale)) {
return;
}
}
}
Node* off = addp->in(AddPNode::Offset);
Node* addr2 = addp2->in(AddPNode::Address);
Node* base = addp->in(AddPNode::Base);
Node* new_addr = NULL;
// Check whether the graph already has the new AddP we need
// before we create one (no GVN available here).
@ -3828,7 +3837,7 @@ void Compile::reshape_address(AddPNode* addp) {
break;
}
}
if (new_addr == NULL) {
new_addr = new AddPNode(base, addr2, off);
}

11
hotspot/src/cpu/aarch64/vm/vm_version_aarch64.hpp
View File

@ -56,6 +56,17 @@ public:
static void assert_is_initialized() {
}
static bool expensive_load(int ld_size, int scale) {
if (cpu_family() == CPU_ARM) {
// Half-word load with index shift by 1 (aka scale is 2) has
// extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
if (ld_size == 2 && scale == 2) {
return true;
}
}
return false;
}
enum Family {
CPU_ARM = 'A',
CPU_BROADCOM = 'B',