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8296435: RISC-V: Small refactoring for increment/decrement

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Reviewed-by: fyang
This commit is contained in:
Feilong Jiang 2022-11-08 01:12:35 +00:00 committed by Fei Yang
parent 47d2c7b4cf
commit 4c80dff2ca
3 changed files with 36 additions and 42 deletions
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56
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
View File

@ -3271,60 +3271,60 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
return stub_start_addr;
}
Address MacroAssembler::add_memory_helper(const Address dst) {
Address MacroAssembler::add_memory_helper(const Address dst, Register tmp) {
switch (dst.getMode()) {
case Address::base_plus_offset:
// This is the expected mode, although we allow all the other
// forms below.
return form_address(t1, dst.base(), dst.offset());
return form_address(tmp, dst.base(), dst.offset());
default:
la(t1, dst);
return Address(t1);
la(tmp, dst);
return Address(tmp);
}
}
void MacroAssembler::increment(const Address dst, int64_t value) {
void MacroAssembler::increment(const Address dst, int64_t value, Register tmp1, Register tmp2) {
assert(((dst.getMode() == Address::base_plus_offset &&
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
"invalid value and address mode combination");
Address adr = add_memory_helper(dst);
assert(!adr.uses(t0), "invalid dst for address increment");
ld(t0, adr);
add(t0, t0, value, t1);
sd(t0, adr);
Address adr = add_memory_helper(dst, tmp2);
assert(!adr.uses(tmp1), "invalid dst for address increment");
ld(tmp1, adr);
add(tmp1, tmp1, value, tmp2);
sd(tmp1, adr);
}
void MacroAssembler::incrementw(const Address dst, int32_t value) {
void MacroAssembler::incrementw(const Address dst, int32_t value, Register tmp1, Register tmp2) {
assert(((dst.getMode() == Address::base_plus_offset &&
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
"invalid value and address mode combination");
Address adr = add_memory_helper(dst);
assert(!adr.uses(t0), "invalid dst for address increment");
lwu(t0, adr);
addw(t0, t0, value, t1);
sw(t0, adr);
Address adr = add_memory_helper(dst, tmp2);
assert(!adr.uses(tmp1), "invalid dst for address increment");
lwu(tmp1, adr);
addw(tmp1, tmp1, value, tmp2);
sw(tmp1, adr);
}
void MacroAssembler::decrement(const Address dst, int64_t value) {
void MacroAssembler::decrement(const Address dst, int64_t value, Register tmp1, Register tmp2) {
assert(((dst.getMode() == Address::base_plus_offset &&
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
"invalid value and address mode combination");
Address adr = add_memory_helper(dst);
assert(!adr.uses(t0), "invalid dst for address decrement");
ld(t0, adr);
sub(t0, t0, value, t1);
sd(t0, adr);
Address adr = add_memory_helper(dst, tmp2);
assert(!adr.uses(tmp1), "invalid dst for address decrement");
ld(tmp1, adr);
sub(tmp1, tmp1, value, tmp2);
sd(tmp1, adr);
}
void MacroAssembler::decrementw(const Address dst, int32_t value) {
void MacroAssembler::decrementw(const Address dst, int32_t value, Register tmp1, Register tmp2) {
assert(((dst.getMode() == Address::base_plus_offset &&
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
"invalid value and address mode combination");
Address adr = add_memory_helper(dst);
assert(!adr.uses(t0), "invalid dst for address decrement");
lwu(t0, adr);
subw(t0, t0, value, t1);
sw(t0, adr);
Address adr = add_memory_helper(dst, tmp2);
assert(!adr.uses(tmp1), "invalid dst for address decrement");
lwu(tmp1, adr);
subw(tmp1, tmp1, value, tmp2);
sw(tmp1, adr);
}
void MacroAssembler::cmpptr(Register src1, Address src2, Label& equal) {

10
src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
View File

@ -1054,11 +1054,11 @@ public:
// to use a 2nd scratch register to hold the constant. so, an address
// increment/decrement may trash both t0 and t1.
void increment(const Address dst, int64_t value = 1);
void incrementw(const Address dst, int32_t value = 1);
void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
void decrement(const Address dst, int64_t value = 1);
void decrementw(const Address dst, int32_t value = 1);
void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
void cmpptr(Register src1, Address src2, Label& equal);
@ -1272,7 +1272,7 @@ private:
}
int bitset_to_regs(unsigned int bitset, unsigned char* regs);
Address add_memory_helper(const Address dst);
Address add_memory_helper(const Address dst, Register tmp);
void load_reserved(Register addr, enum operand_size size, Assembler::Aqrl acquire);
void store_conditional(Register addr, Register new_val, enum operand_size size, Assembler::Aqrl release);

12
src/hotspot/cpu/riscv/riscv.ad
View File

@ -2450,17 +2450,13 @@ encode %{
// Recursive lock case
__ mv(flag, zr);
__ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
__ add(tmp, tmp, 1);
__ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
__ increment(Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value), 1, t0, tmp);
__ bind(cont);
__ bnez(flag, no_count);
__ ld(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
__ add(tmp, tmp, 1);
__ sd(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
__ increment(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
__ bind(no_count);
%}
@ -2537,9 +2533,7 @@ encode %{
__ bnez(flag, no_count);
__ ld(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
__ sub(tmp, tmp, 1);
__ sd(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
__ decrement(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
__ bind(no_count);
%}