diff --git a/src/hotspot/share/runtime/thread.cpp b/src/hotspot/share/runtime/thread.cpp
index ed1c8c2508f..9c12da15180 100644
--- a/src/hotspot/share/runtime/thread.cpp
+++ b/src/hotspot/share/runtime/thread.cpp
@@ -602,7 +602,6 @@ void Thread::SpinAcquire(volatile int * adr) {
 
 void Thread::SpinRelease(volatile int * adr) {
   assert(*adr != 0, "invariant");
-  OrderAccess::fence();      // guarantee at least release consistency.
   // Roach-motel semantics.
   // It's safe if subsequent LDs and STs float "up" into the critical section,
   // but prior LDs and STs within the critical section can't be allowed
@@ -610,8 +609,7 @@ void Thread::SpinRelease(volatile int * adr) {
   // Loads and stores in the critical section - which appear in program
   // order before the store that releases the lock - must also appear
   // before the store that releases the lock in memory visibility order.
-  // Conceptually we need a #loadstore|#storestore "release" MEMBAR before
-  // the ST of 0 into the lock-word which releases the lock, so fence
-  // more than covers this on all platforms.
-  *adr = 0;
+  // So we need a #loadstore|#storestore "release" memory barrier before
+  // the ST of 0 into the lock-word which releases the lock.
+  Atomic::release_store(adr, 0);
 }