From 4f3dc9d13a609ef50205f77e9cdf9c57fd30bcca Mon Sep 17 00:00:00 2001 From: Fei Yang Date: Wed, 15 Jan 2025 08:04:04 +0000 Subject: [PATCH] 8347352: RISC-V: Cleanup bitwise AND assembler routines Reviewed-by: rehn, fjiang, mli --- src/hotspot/cpu/riscv/assembler_riscv.hpp | 36 +++++++++---------- .../cpu/riscv/c1_MacroAssembler_riscv.cpp | 2 +- .../cpu/riscv/macroAssembler_riscv.cpp | 18 +++------- .../cpu/riscv/macroAssembler_riscv.hpp | 14 ++++---- src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp | 3 +- 5 files changed, 32 insertions(+), 41 deletions(-) diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp index a9d601edbbe..88317031562 100644 --- a/src/hotspot/cpu/riscv/assembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp @@ -835,7 +835,7 @@ enum operand_size { int8, int16, int32, uint32, int64 }; // Immediate Instruction #define INSN(NAME, op, funct3) \ - void NAME(Register Rd, Register Rs1, int32_t imm) { \ + void NAME(Register Rd, Register Rs1, int64_t imm) { \ guarantee(is_simm12(imm), "Immediate is out of validity"); \ unsigned insn = 0; \ patch((address)&insn, 6, 0, op); \ @@ -846,17 +846,17 @@ enum operand_size { int8, int16, int32, uint32, int64 }; emit(insn); \ } - INSN(_addi, 0b0010011, 0b000); - INSN(slti, 0b0010011, 0b010); - INSN(_addiw, 0b0011011, 0b000); - INSN(_and_imm12, 0b0010011, 0b111); - INSN(ori, 0b0010011, 0b110); - INSN(xori, 0b0010011, 0b100); + INSN(_addi, 0b0010011, 0b000); + INSN(_addiw, 0b0011011, 0b000); + INSN(_andi, 0b0010011, 0b111); + INSN(ori, 0b0010011, 0b110); + INSN(xori, 0b0010011, 0b100); + INSN(slti, 0b0010011, 0b010); #undef INSN #define INSN(NAME, op, funct3) \ - void NAME(Register Rd, Register Rs1, uint32_t imm) { \ + void NAME(Register Rd, Register Rs1, uint64_t imm) { \ guarantee(is_uimm12(imm), "Immediate is out of validity"); \ unsigned insn = 0; \ patch((address)&insn,6, 0, op); \ @@ -2230,7 +2230,7 @@ public: } #define INSN(NAME, funct3, op) \ - void NAME(Register Rd_Rs1, int32_t imm) { \ + void NAME(Register Rd_Rs1, int64_t imm) { \ assert_cond(is_simm6(imm)); \ uint16_t insn = 0; \ c_patch((address)&insn, 1, 0, op); \ @@ -2247,7 +2247,7 @@ public: #undef INSN #define INSN(NAME, funct3, op) \ - void NAME(int32_t imm) { \ + void NAME(int64_t imm) { \ assert_cond(is_simm10(imm)); \ assert_cond((imm & 0b1111) == 0); \ assert_cond(imm != 0); \ @@ -2268,7 +2268,7 @@ public: #undef INSN #define INSN(NAME, funct3, op) \ - void NAME(Register Rd, uint32_t uimm) { \ + void NAME(Register Rd, uint64_t uimm) { \ assert_cond(is_uimm10(uimm)); \ assert_cond((uimm & 0b11) == 0); \ assert_cond(uimm != 0); \ @@ -2325,7 +2325,7 @@ public: #undef INSN #define INSN(NAME, funct3, funct2, op) \ - void NAME(Register Rd_Rs1, int32_t imm) { \ + void NAME(Register Rd_Rs1, int64_t imm) { \ assert_cond(is_simm6(imm)); \ uint16_t insn = 0; \ c_patch((address)&insn, 1, 0, op); \ @@ -2950,7 +2950,7 @@ public: // Immediate Instructions // -------------------------- #define INSN(NAME) \ - void NAME(Register Rd, Register Rs1, int32_t imm) { \ + void NAME(Register Rd, Register Rs1, int64_t imm) { \ /* addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn */ \ if (do_compress()) { \ if (Rd == Rs1 && is_simm6(imm)) { \ @@ -2978,7 +2978,7 @@ public: // -------------------------- #define INSN(NAME) \ - void NAME(Register Rd, Register Rs1, int32_t imm) { \ + void NAME(Register Rd, Register Rs1, int64_t imm) { \ /* addiw -> c.addiw */ \ if (do_compress() && (Rd == Rs1 && Rd != x0 && is_simm6(imm))) { \ c_addiw(Rd, imm); \ @@ -2993,17 +2993,17 @@ public: // -------------------------- #define INSN(NAME) \ - void NAME(Register Rd, Register Rs1, int32_t imm) { \ - /* and_imm12 -> c.andi */ \ + void NAME(Register Rd, Register Rs1, int64_t imm) { \ + /* andi -> c.andi */ \ if (do_compress() && \ (Rd == Rs1 && Rd->is_compressed_valid() && is_simm6(imm))) { \ c_andi(Rd, imm); \ return; \ } \ - _and_imm12(Rd, Rs1, imm); \ + _andi(Rd, Rs1, imm); \ } - INSN(and_imm12); + INSN(andi); #undef INSN diff --git a/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp index 10aa5514fdf..530284f0c62 100644 --- a/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp @@ -301,7 +301,7 @@ void C1_MacroAssembler::allocate_array(Register obj, Register len, Register tmp1 // align object end mv(arr_size, (int32_t)base_offset_in_bytes + MinObjAlignmentInBytesMask); shadd(arr_size, len, arr_size, t0, f); - andi(arr_size, arr_size, ~(uint)MinObjAlignmentInBytesMask); + andi(arr_size, arr_size, ~MinObjAlignmentInBytesMask); try_allocate(obj, arr_size, 0, tmp1, tmp2, slow_case); diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp index f0e5992b04b..24504472509 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp @@ -2619,7 +2619,7 @@ void MacroAssembler::sub(Register Rd, Register Rn, int64_t decrement, Register t add(Rd, Rn, -decrement, tmp); } -void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register tmp) { +void MacroAssembler::addw(Register Rd, Register Rn, int64_t increment, Register tmp) { if (is_simm12(increment)) { addiw(Rd, Rn, increment); } else { @@ -2629,7 +2629,7 @@ void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register } } -void MacroAssembler::subw(Register Rd, Register Rn, int32_t decrement, Register tmp) { +void MacroAssembler::subw(Register Rd, Register Rn, int64_t decrement, Register tmp) { addw(Rd, Rn, -decrement, tmp); } @@ -2901,16 +2901,6 @@ void MacroAssembler::rolw(Register dst, Register src, uint32_t shift, Register t orr(dst, dst, tmp); } -void MacroAssembler::andi(Register Rd, Register Rn, int64_t imm, Register tmp) { - if (is_simm12(imm)) { - and_imm12(Rd, Rn, imm); - } else { - assert_different_registers(Rn, tmp); - mv(tmp, imm); - andr(Rd, Rn, tmp); - } -} - void MacroAssembler::orptr(Address adr, RegisterOrConstant src, Register tmp1, Register tmp2) { ld(tmp1, adr); if (src.is_register()) { @@ -6142,10 +6132,10 @@ void MacroAssembler::test_bit(Register Rd, Register Rs, uint32_t bit_pos) { } int64_t imm = (int64_t)(1UL << bit_pos); if (is_simm12(imm)) { - and_imm12(Rd, Rs, imm); + andi(Rd, Rs, imm); } else { srli(Rd, Rs, bit_pos); - and_imm12(Rd, Rd, 1); + andi(Rd, Rd, 1); } } diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp index b2e79edd963..04b95ba355b 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp @@ -886,17 +886,17 @@ public: public: // arith - void add(Register Rd, Register Rn, int64_t increment, Register tmp = t0); - void sub(Register Rd, Register Rn, int64_t decrement, Register tmp = t0); - void addw(Register Rd, Register Rn, int32_t increment, Register tmp = t0); - void subw(Register Rd, Register Rn, int32_t decrement, Register tmp = t0); + void add (Register Rd, Register Rn, int64_t increment, Register tmp = t0); + void sub (Register Rd, Register Rn, int64_t decrement, Register tmp = t0); + void addw(Register Rd, Register Rn, int64_t increment, Register tmp = t0); + void subw(Register Rd, Register Rn, int64_t decrement, Register tmp = t0); - void subi(Register Rd, Register Rn, int32_t decrement) { + void subi(Register Rd, Register Rn, int64_t decrement) { assert(is_simm12(-decrement), "Must be"); addi(Rd, Rn, -decrement); } - void subiw(Register Rd, Register Rn, int32_t decrement) { + void subiw(Register Rd, Register Rn, int64_t decrement) { assert(is_simm12(-decrement), "Must be"); addiw(Rd, Rn, -decrement); } @@ -928,7 +928,7 @@ public: void ror(Register dst, Register src, uint32_t shift, Register tmp = t0); void rolw(Register dst, Register src, uint32_t shift, Register tmp = t0); - void andi(Register Rd, Register Rn, int64_t imm, Register tmp = t0); + void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1); // Load and Store Instructions diff --git a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp index f919bd9c530..f9aa7bc2bd7 100644 --- a/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp +++ b/src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp @@ -1715,7 +1715,8 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, // NOTE: the oopMark is in swap_reg % 10 as the result of cmpxchg __ sub(swap_reg, swap_reg, sp); - __ andi(swap_reg, swap_reg, 3 - (int)os::vm_page_size()); + __ mv(t0, 3 - (int)os::vm_page_size()); + __ andr(swap_reg, swap_reg, t0); // Save the test result, for recursive case, the result is zero __ sd(swap_reg, Address(lock_reg, mark_word_offset));