diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp index bb7e2f5021f..02fbf5bfbf7 100644 --- a/src/hotspot/cpu/riscv/assembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp @@ -1399,7 +1399,6 @@ enum VectorMask { // Vector Floating-Point Sign-Injection Instructions INSN(vfsgnjx_vv, 0b1010111, 0b001, 0b001010); INSN(vfsgnjn_vv, 0b1010111, 0b001, 0b001001); - INSN(vfsgnj_vv, 0b1010111, 0b001, 0b001000); // Vector Floating-Point MIN/MAX Instructions INSN(vfmax_vv, 0b1010111, 0b001, 0b000110); @@ -1552,11 +1551,6 @@ enum VectorMask { INSN(vmfne_vf, 0b1010111, 0b101, 0b011100); INSN(vmfeq_vf, 0b1010111, 0b101, 0b011000); - // Vector Floating-Point Sign-Injection Instructions - INSN(vfsgnjx_vf, 0b1010111, 0b101, 0b001010); - INSN(vfsgnjn_vf, 0b1010111, 0b101, 0b001001); - INSN(vfsgnj_vf, 0b1010111, 0b101, 0b001000); - // Vector Floating-Point MIN/MAX Instructions INSN(vfmax_vf, 0b1010111, 0b101, 0b000110); INSN(vfmin_vf, 0b1010111, 0b101, 0b000100); diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp index 5e7a9ffa63a..c0de12c3205 100644 --- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp @@ -134,7 +134,7 @@ void unspill(VectorRegister v, int offset) { add(t0, sp, offset); - vl1re8_v(v, t0); + vl1r_v(v, t0); } void spill_copy_vector_stack_to_stack(int src_offset, int dst_offset, int vector_length_in_bytes) { diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp index 7679e15f41f..eb82ae2adeb 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp @@ -1278,7 +1278,7 @@ int MacroAssembler::pop_v(unsigned int bitset, Register stack) { int count = bitset_to_regs(bitset, regs); for (int i = count - 1; i >= 0; i--) { - vl1re8_v(as_VectorRegister(regs[i]), stack); + vl1r_v(as_VectorRegister(regs[i]), stack); add(stack, stack, vector_size_in_bytes); } diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp index 98077935cf1..83688b88846 100644 --- a/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp +++ b/src/hotspot/cpu/riscv/macroAssembler_riscv.hpp @@ -1265,6 +1265,10 @@ public: } // vector pseudo instructions + inline void vl1r_v(VectorRegister vd, Register rs) { + vl1re8_v(vd, rs); + } + inline void vmnot_m(VectorRegister vd, VectorRegister vs) { vmnand_mm(vd, vs, vs); } @@ -1281,6 +1285,10 @@ public: vfsgnjn_vv(vd, vs, vs, vm); } + inline void vfabs_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) { + vfsgnjx_vv(vd, vs, vs, vm); + } + inline void vmsgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) { vmslt_vv(vd, vs1, vs2, vm); } diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 272c2ce763e..fca6649e8de 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -259,7 +259,7 @@ instruct vabs_fp(vReg dst, vReg src) %{ ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); - __ vfsgnjx_vv(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), as_VectorRegister($src$$reg)); + __ vfabs_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); %} @@ -293,8 +293,7 @@ instruct vabs_fp_masked(vReg dst_src, vRegMask_V0 v0) %{ ins_encode %{ BasicType bt = Matcher::vector_element_basic_type(this); __ vsetvli_helper(bt, Matcher::vector_length(this)); - __ vfsgnjx_vv(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), - as_VectorRegister($dst_src$$reg), Assembler::v0_t); + __ vfabs_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t); %} ins_pipe(pipe_slow); %}