From 520ddac97053be669d9678375266ccfd6724e3e1 Mon Sep 17 00:00:00 2001 From: Varada M Date: Tue, 29 Oct 2024 18:20:03 +0000 Subject: [PATCH] 8331861: [PPC64] Implement load / store assembler functions which take an Address object Reviewed-by: amitkumar, mdoerr --- src/hotspot/cpu/ppc/assembler_ppc.hpp | 37 ++++++++++++------- src/hotspot/cpu/ppc/assembler_ppc.inline.hpp | 30 +++++++++++++++ src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp | 28 +++++++------- .../cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp | 4 +- 4 files changed, 70 insertions(+), 29 deletions(-) diff --git a/src/hotspot/cpu/ppc/assembler_ppc.hpp b/src/hotspot/cpu/ppc/assembler_ppc.hpp index d445108098b..b2711ac43b0 100644 --- a/src/hotspot/cpu/ppc/assembler_ppc.hpp +++ b/src/hotspot/cpu/ppc/assembler_ppc.hpp @@ -2502,19 +2502,19 @@ class Assembler : public AbstractAssembler { // load the constant are emitted beforehand. Store instructions need a // tmp reg if the constant is not encodable as immediate. // Size unpredictable. - void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); - void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); - void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); - void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); - void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); - void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); - void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); - void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); - void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); - void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); - void add( Register d, Register s, RegisterOrConstant roc); - void add( Register d, RegisterOrConstant roc, Register s) { add(d, s, roc); } - void sub( Register d, Register s, RegisterOrConstant roc); + void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); + void lwa(Register d, RegisterOrConstant roc, Register s1 = noreg); + void lwz(Register d, RegisterOrConstant roc, Register s1 = noreg); + void lha(Register d, RegisterOrConstant roc, Register s1 = noreg); + void lhz(Register d, RegisterOrConstant roc, Register s1 = noreg); + void lbz(Register d, RegisterOrConstant roc, Register s1 = noreg); + void std(Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); + void stw(Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); + void sth(Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); + void stb(Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); + void add(Register d, Register s, RegisterOrConstant roc); + void add(Register d, RegisterOrConstant roc, Register s) { add(d, s, roc); } + void sub(Register d, Register s, RegisterOrConstant roc); void xorr(Register d, Register s, RegisterOrConstant roc); void xorr(Register d, RegisterOrConstant roc, Register s) { xorr(d, s, roc); } void cmpw(ConditionRegister d, Register s, RegisterOrConstant roc); @@ -2522,6 +2522,17 @@ class Assembler : public AbstractAssembler { // Load pointer d from s1+roc. void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); } + void ld( Register d, Address &a); + void lwa(Register d, Address &a); + void lwz(Register d, Address &a); + void lha(Register d, Address &a); + void lhz(Register d, Address &a); + void lbz(Register d, Address &a); + void std(Register d, Address &a, Register tmp = noreg); + void stw(Register d, Address &a, Register tmp = noreg); + void sth(Register d, Address &a, Register tmp = noreg); + void stb(Register d, Address &a, Register tmp = noreg); + // Emit several instructions to load a 64 bit constant. This issues a fixed // instruction pattern so that the constant can be patched later on. enum { diff --git a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp index 98c8b629844..b0eaaccf0d0 100644 --- a/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp +++ b/src/hotspot/cpu/ppc/assembler_ppc.inline.hpp @@ -338,28 +338,46 @@ inline void Assembler::insrwi( Register a, Register s, int n, int b) // PPC 1, section 3.3.2 Fixed-Point Load Instructions inline void Assembler::lwzx( Register d, Register s1, Register s2) { emit_int32(LWZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::lwz( Register d, Address &a) { + lwz(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::lwz( Register d, int si16, Register s1) { emit_int32(LWZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} inline void Assembler::lwzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LWZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} inline void Assembler::lwax( Register d, Register s1, Register s2) { emit_int32(LWAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::lwa( Register d, Address &a) { + lwa(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::lwa( Register d, int si16, Register s1) { emit_int32(LWA_OPCODE | rt(d) | ds(si16) | ra0mem(s1));} inline void Assembler::lwbrx( Register d, Register s1, Register s2) { emit_int32(LWBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} inline void Assembler::lhzx( Register d, Register s1, Register s2) { emit_int32(LHZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::lhz( Register d, Address &a) { + lhz(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::lhz( Register d, int si16, Register s1) { emit_int32(LHZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} inline void Assembler::lhzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} inline void Assembler::lhbrx( Register d, Register s1, Register s2) { emit_int32(LHBRX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} inline void Assembler::lhax( Register d, Register s1, Register s2) { emit_int32(LHAX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::lha( Register d, Address &a) { + lha(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::lha( Register d, int si16, Register s1) { emit_int32(LHA_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} inline void Assembler::lhau( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LHAU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} inline void Assembler::lbzx( Register d, Register s1, Register s2) { emit_int32(LBZX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::lbz( Register d, Address &a) { + lbz(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::lbz( Register d, int si16, Register s1) { emit_int32(LBZ_OPCODE | rt(d) | d1(si16) | ra0mem(s1));} inline void Assembler::lbzu( Register d, int si16, Register s1) { assert(d != s1, "according to ibm manual"); emit_int32(LBZU_OPCODE | rt(d) | d1(si16) | rta0mem(s1));} +inline void Assembler::ld( Register d, Address &a) { + ld(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base()); +} inline void Assembler::ld( Register d, int si16, Register s1) { emit_int32(LD_OPCODE | rt(d) | ds(si16) | ra0mem(s1));} inline void Assembler::ld( Register d, ByteSize si16, Register s1) { assert(in_bytes(si16) < 0x7fff, "overflow"); ld(d, in_bytes(si16), s1); } inline void Assembler::ldx( Register d, Register s1, Register s2) { emit_int32(LDX_OPCODE | rt(d) | ra0mem(s1) | rb(s2));} @@ -371,19 +389,31 @@ inline void Assembler::ld_ptr(Register d, ByteSize b, Register s1) { ld(d, in_by // PPC 1, section 3.3.3 Fixed-Point Store Instructions inline void Assembler::stwx( Register d, Register s1, Register s2) { emit_int32(STWX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::stw( Register d, Address &a, Register tmp) { + stw(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base(), tmp); +} inline void Assembler::stw( Register d, int si16, Register s1) { emit_int32(STW_OPCODE | rs(d) | d1(si16) | ra0mem(s1));} inline void Assembler::stwu( Register d, int si16, Register s1) { emit_int32(STWU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));} inline void Assembler::stwbrx( Register d, Register s1, Register s2) { emit_int32(STWBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} inline void Assembler::sthx( Register d, Register s1, Register s2) { emit_int32(STHX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::sth( Register d, Address &a, Register tmp) { + sth(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base(), tmp); +} inline void Assembler::sth( Register d, int si16, Register s1) { emit_int32(STH_OPCODE | rs(d) | d1(si16) | ra0mem(s1));} inline void Assembler::sthu( Register d, int si16, Register s1) { emit_int32(STHU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));} inline void Assembler::sthbrx( Register d, Register s1, Register s2) { emit_int32(STHBRX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} inline void Assembler::stbx( Register d, Register s1, Register s2) { emit_int32(STBX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} +inline void Assembler::stb( Register d, Address &a, Register tmp) { + stb(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base(), tmp); +} inline void Assembler::stb( Register d, int si16, Register s1) { emit_int32(STB_OPCODE | rs(d) | d1(si16) | ra0mem(s1));} inline void Assembler::stbu( Register d, int si16, Register s1) { emit_int32(STBU_OPCODE | rs(d) | d1(si16) | rta0mem(s1));} +inline void Assembler::std( Register d, Address &a, Register tmp) { + std(d, a.index() != noreg ? RegisterOrConstant(a.index()) : RegisterOrConstant(a.disp()), a.base(), tmp); +} inline void Assembler::std( Register d, int si16, Register s1) { emit_int32(STD_OPCODE | rs(d) | ds(si16) | ra0mem(s1));} inline void Assembler::stdx( Register d, Register s1, Register s2) { emit_int32(STDX_OPCODE | rs(d) | ra0mem(s1) | rb(s2));} inline void Assembler::stdu( Register d, int si16, Register s1) { emit_int32(STDU_OPCODE | rs(d) | ds(si16) | rta0mem(s1));} diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp index 57e5f65d2f9..36e1ac82334 100644 --- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp +++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp @@ -168,9 +168,9 @@ void LIR_Assembler::osr_entry() { mo = frame_map()->address_for_monitor_object(i); assert(ml.index() == noreg && mo.index() == noreg, "sanity"); __ ld(R0, slot_offset + 0, OSR_buf); - __ std(R0, ml.disp(), ml.base()); + __ std(R0, ml); __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf); - __ std(R0, mo.disp(), mo.base()); + __ std(R0, mo); } if (use_OSR_bias) { @@ -601,7 +601,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { __ fcmpu(CCR0, rsrc, rsrc); if (dst_in_memory) { __ li(R0, 0); // 0 in case of NAN - __ std(R0, addr.disp(), addr.base()); + __ std(R0, addr); } else { __ li(dst->as_register(), 0); } @@ -625,7 +625,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { __ fcmpu(CCR0, rsrc, rsrc); if (dst_in_memory) { __ li(R0, 0); // 0 in case of NAN - __ std(R0, addr.disp(), addr.base()); + __ std(R0, addr); } else { __ li(dst->as_register_lo(), 0); } @@ -893,20 +893,20 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { int value = c->as_jint_bits(); __ load_const_optimized(src_reg, value); Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); - __ stw(src_reg, addr.disp(), addr.base()); + __ stw(src_reg, addr); break; } case T_ADDRESS: { int value = c->as_jint_bits(); __ load_const_optimized(src_reg, value); Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); - __ std(src_reg, addr.disp(), addr.base()); + __ std(src_reg, addr); break; } case T_OBJECT: { jobject2reg(c->as_jobject(), src_reg); Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); - __ std(src_reg, addr.disp(), addr.base()); + __ std(src_reg, addr); break; } case T_LONG: @@ -914,7 +914,7 @@ void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { int value = c->as_jlong_bits(); __ load_const_optimized(src_reg, value); Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); - __ std(src_reg, addr.disp(), addr.base()); + __ std(src_reg, addr); break; } default: @@ -1090,24 +1090,24 @@ void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { case T_FLOAT: { Address from = frame_map()->address_for_slot(src->single_stack_ix()); Address to = frame_map()->address_for_slot(dest->single_stack_ix()); - __ lwz(tmp, from.disp(), from.base()); - __ stw(tmp, to.disp(), to.base()); + __ lwz(tmp, from); + __ stw(tmp, to); break; } case T_ADDRESS: case T_OBJECT: { Address from = frame_map()->address_for_slot(src->single_stack_ix()); Address to = frame_map()->address_for_slot(dest->single_stack_ix()); - __ ld(tmp, from.disp(), from.base()); - __ std(tmp, to.disp(), to.base()); + __ ld(tmp, from); + __ std(tmp, to); break; } case T_LONG: case T_DOUBLE: { Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); - __ ld(tmp, from.disp(), from.base()); - __ std(tmp, to.disp(), to.base()); + __ ld(tmp, from); + __ std(tmp, to); break; } diff --git a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp index 8a65022126e..b9ea67dabe3 100644 --- a/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp +++ b/src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp @@ -610,14 +610,14 @@ void ZBarrierSetAssembler::try_resolve_jobject_in_native(MacroAssembler* masm, R // Resolve global handle __ ld(dst, 0, dst); - __ ld(tmp, load_bad_mask.disp(), load_bad_mask.base()); + __ ld(tmp, load_bad_mask); __ b(check_color); __ bind(weak_tagged); // Resolve weak handle __ ld(dst, 0, dst); - __ ld(tmp, mark_bad_mask.disp(), mark_bad_mask.base()); + __ ld(tmp, mark_bad_mask); __ bind(check_color); __ and_(tmp, tmp, dst);