diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestMultiplyReductionByte.java b/test/hotspot/jtreg/compiler/vectorapi/TestMultiplyReductionByte.java index e9bf906a1be..b56dc371559 100644 --- a/test/hotspot/jtreg/compiler/vectorapi/TestMultiplyReductionByte.java +++ b/test/hotspot/jtreg/compiler/vectorapi/TestMultiplyReductionByte.java @@ -35,7 +35,7 @@ import jdk.test.lib.Utils; /** * @test - * @bug 8378250 + * @bug 8378250 8381452 * @summary Verify correctness of byte vector MUL reduction across all species. * A register aliasing bug in mulreduce32B caused the upper half of * sign-extended data to overwrite the source, producing wrong results @@ -93,8 +93,13 @@ public class TestMultiplyReductionByte { @Test @IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"}, - applyIfCPUFeatureOr = {"avx2", "true", "asimd", "true", "rvv", "true"}, + applyIfCPUFeatureOr = {"avx2", "true", "rvv", "true"}, applyIf = {"MaxVectorSize", ">=32"}) + @IR(counts = {IRNode.MUL_REDUCTION_VI, "0"}, + applyIfCPUFeature = {"asimd", "true"}, + applyIf = {"MaxVectorSize", ">=32"}) + // AArch64 currently does not vectorize vectors larger than 128 bits, and + // that may change in the future. static byte testMulReduce256() { return ByteVector.fromArray(ByteVector.SPECIES_256, input, 0) .reduceLanes(VectorOperators.MUL); @@ -111,8 +116,13 @@ public class TestMultiplyReductionByte { @Test @IR(counts = {IRNode.MUL_REDUCTION_VI, ">=1"}, - applyIfCPUFeatureOr = {"avx512f", "true", "asimd", "true", "rvv", "true"}, + applyIfCPUFeatureOr = {"avx512f", "true", "rvv", "true"}, applyIf = {"MaxVectorSize", ">=64"}) + @IR(counts = {IRNode.MUL_REDUCTION_VI, "0"}, + applyIfCPUFeature = {"asimd", "true"}, + applyIf = {"MaxVectorSize", ">=64"}) + // AArch64 currently does not vectorize vectors larger than 128 bits, and + // that may change in the future. static byte testMulReduce512() { return ByteVector.fromArray(ByteVector.SPECIES_512, input, 0) .reduceLanes(VectorOperators.MUL);