From 5d3fdc1750645455d64a341e1437f779ba3fd20c Mon Sep 17 00:00:00 2001
From: Vladimir Kempik <vkempik@openjdk.org>
Date: Wed, 6 Sep 2023 06:49:10 +0000
Subject: [PATCH] 8315612: RISC-V: intrinsic for unsignedMultiplyHigh

Reviewed-by: fyang
---
 src/hotspot/cpu/riscv/riscv.ad | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index d03dc843c2b..1cca3ef9f37 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -6864,6 +6864,21 @@ instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
   ins_pipe(lmul_reg_reg);
 %}
 
+instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
+%{
+  match(Set dst (UMulHiL src1 src2));
+  ins_cost(IMUL_COST);
+  format %{ "mulhu  $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
+
+  ins_encode %{
+    __ mulhu(as_Register($dst$$reg),
+             as_Register($src1$$reg),
+             as_Register($src2$$reg));
+  %}
+
+  ins_pipe(lmul_reg_reg);
+%}
+
 // Integer Divide
 
 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{