From 67f03f2a4f5ac12748ffbf5c04f248a60869e180 Mon Sep 17 00:00:00 2001
From: Gui Cao <gcao@openjdk.org>
Date: Wed, 22 May 2024 06:56:40 +0000
Subject: [PATCH] 8332533: RISC-V: Enable vector variable shift instructions
 for machines with RVV

Reviewed-by: fyang, mli
---
 src/hotspot/cpu/riscv/matcher_riscv.hpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/hotspot/cpu/riscv/matcher_riscv.hpp b/src/hotspot/cpu/riscv/matcher_riscv.hpp
index 32665f5922c..2fa6e8c80ca 100644
--- a/src/hotspot/cpu/riscv/matcher_riscv.hpp
+++ b/src/hotspot/cpu/riscv/matcher_riscv.hpp
@@ -128,8 +128,8 @@
   static const bool int_in_long = true;
 
   // Does the CPU supports vector variable shift instructions?
-  static constexpr bool supports_vector_variable_shifts(void) {
-    return false;
+  static bool supports_vector_variable_shifts(void) {
+    return UseRVV;
   }
 
   // Does target support predicated operation emulation.