8327689: RISC-V: adjust test filters of zfh extension

Reviewed-by: fyang, gli
This commit is contained in:
Hamlin Li 2024-03-11 12:13:06 +00:00
parent 570ad67204
commit 680ac2cebe
4 changed files with 4 additions and 4 deletions

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@ -26,7 +26,7 @@
* @bug 8289551 8302976
* @summary Verify conversion between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*")
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run

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@ -26,7 +26,7 @@
* @bug 8289551 8302976
* @summary Verify NaN sign and significand bits are preserved across conversions
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*")
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @library /test/lib /

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@ -26,7 +26,7 @@
* @bug 8302976
* @summary Verify conversion between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch == "aarch64"
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*")
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run:

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@ -26,7 +26,7 @@
* @bug 8302976
* @summary Verify conversion cons between float and the binary16 format
* @requires (vm.cpu.features ~= ".*avx512vl.*" | vm.cpu.features ~= ".*f16c.*") | os.arch=="aarch64"
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh,.*")
* | (os.arch == "riscv64" & vm.cpu.features ~= ".*zfh.*")
* @requires vm.compiler1.enabled & vm.compiler2.enabled
* @requires vm.compMode != "Xcomp"
* @comment default run: