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8320347: Emulate vblendvp[sd] on ECore
Reviewed-by: sviswanathan, jbhateja
This commit is contained in:
Volodymyr Paprotski
Sandhya Viswanathan
parent
693847452f
commit
6aba6aa6f1
@ -1094,32 +1094,78 @@ void C2_MacroAssembler::vminmax_fp(int opcode, BasicType elem_bt,
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bool is_min = (opcode == Op_MinV || opcode == Op_MinReductionV);
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bool is_double_word = is_double_word_type(elem_bt);
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/* Note on 'non-obvious' assembly sequence:
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*
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* While there are vminps/vmaxps instructions, there are two important differences between hardware
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* and Java on how they handle floats:
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* a. -0.0 and +0.0 are considered equal (vminps/vmaxps will return second parameter when inputs are equal)
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* b. NaN is not necesarily propagated (vminps/vmaxps will return second parameter when either input is NaN)
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*
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* It is still more efficient to use vminps/vmaxps, but with some pre/post-processing:
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* a. -0.0/+0.0: Bias negative (positive) numbers to second parameter before vminps (vmaxps)
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* (only useful when signs differ, noop otherwise)
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* b. NaN: Check if it was the first parameter that had the NaN (with vcmp[UNORD_Q])
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* Following pseudo code describes the algorithm for max[FD] (Min algorithm is on similar lines):
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* btmp = (b < +0.0) ? a : b
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* atmp = (b < +0.0) ? b : a
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* Tmp = Max_Float(atmp , btmp)
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* Res = (atmp == NaN) ? atmp : Tmp
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*/
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void (MacroAssembler::*vblend)(XMMRegister, XMMRegister, XMMRegister, XMMRegister, int, bool, XMMRegister);
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void (MacroAssembler::*vmaxmin)(XMMRegister, XMMRegister, XMMRegister, int);
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void (MacroAssembler::*vcmp)(XMMRegister, XMMRegister, XMMRegister, int, int);
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XMMRegister mask;
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if (!is_double_word && is_min) {
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vblendvps(atmp, a, b, a, vlen_enc);
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vblendvps(btmp, b, a, a, vlen_enc);
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vminps(tmp, atmp, btmp, vlen_enc);
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vcmpps(btmp, atmp, atmp, Assembler::UNORD_Q, vlen_enc);
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vblendvps(dst, tmp, atmp, btmp, vlen_enc);
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mask = a;
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vblend = &MacroAssembler::vblendvps;
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vmaxmin = &MacroAssembler::vminps;
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vcmp = &MacroAssembler::vcmpps;
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} else if (!is_double_word && !is_min) {
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vblendvps(btmp, b, a, b, vlen_enc);
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vblendvps(atmp, a, b, b, vlen_enc);
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vmaxps(tmp, atmp, btmp, vlen_enc);
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vcmpps(btmp, atmp, atmp, Assembler::UNORD_Q, vlen_enc);
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vblendvps(dst, tmp, atmp, btmp, vlen_enc);
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mask = b;
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vblend = &MacroAssembler::vblendvps;
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vmaxmin = &MacroAssembler::vmaxps;
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vcmp = &MacroAssembler::vcmpps;
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} else if (is_double_word && is_min) {
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vblendvpd(atmp, a, b, a, vlen_enc);
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vblendvpd(btmp, b, a, a, vlen_enc);
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vminpd(tmp, atmp, btmp, vlen_enc);
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vcmppd(btmp, atmp, atmp, Assembler::UNORD_Q, vlen_enc);
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vblendvpd(dst, tmp, atmp, btmp, vlen_enc);
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mask = a;
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vblend = &MacroAssembler::vblendvpd;
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vmaxmin = &MacroAssembler::vminpd;
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vcmp = &MacroAssembler::vcmppd;
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} else {
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assert(is_double_word && !is_min, "sanity");
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vblendvpd(btmp, b, a, b, vlen_enc);
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vblendvpd(atmp, a, b, b, vlen_enc);
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vmaxpd(tmp, atmp, btmp, vlen_enc);
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vcmppd(btmp, atmp, atmp, Assembler::UNORD_Q, vlen_enc);
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vblendvpd(dst, tmp, atmp, btmp, vlen_enc);
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mask = b;
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vblend = &MacroAssembler::vblendvpd;
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vmaxmin = &MacroAssembler::vmaxpd;
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vcmp = &MacroAssembler::vcmppd;
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}
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// Make sure EnableX86ECoreOpts isn't disabled on register overlaps
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XMMRegister maxmin, scratch;
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if (dst == btmp) {
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maxmin = btmp;
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scratch = tmp;
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} else {
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maxmin = tmp;
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scratch = btmp;
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}
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bool precompute_mask = EnableX86ECoreOpts && UseAVX>1;
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if (precompute_mask && !is_double_word) {
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vpsrad(tmp, mask, 32, vlen_enc);
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mask = tmp;
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} else if (precompute_mask && is_double_word) {
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vpxor(tmp, tmp, tmp, vlen_enc);
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vpcmpgtq(tmp, tmp, mask, vlen_enc);
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mask = tmp;
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}
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(this->*vblend)(atmp, a, b, mask, vlen_enc, !precompute_mask, btmp);
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(this->*vblend)(btmp, b, a, mask, vlen_enc, !precompute_mask, tmp);
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(this->*vmaxmin)(maxmin, atmp, btmp, vlen_enc);
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(this->*vcmp)(scratch, atmp, atmp, Assembler::UNORD_Q, vlen_enc);
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(this->*vblend)(dst, maxmin, atmp, scratch, vlen_enc, false, scratch);
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}
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void C2_MacroAssembler::evminmax_fp(int opcode, BasicType elem_bt,
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@ -5318,18 +5364,18 @@ void C2_MacroAssembler::vector_signum_avx(int opcode, XMMRegister dst, XMMRegist
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if (opcode == Op_SignumVD) {
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vsubpd(dst, zero, one, vec_enc);
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// if src < 0 ? -1 : 1
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vblendvpd(dst, one, dst, src, vec_enc);
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vblendvpd(dst, one, dst, src, vec_enc, true, xtmp1);
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// if src == NaN, -0.0 or 0.0 return src.
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vcmppd(xtmp1, src, zero, Assembler::EQ_UQ, vec_enc);
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vblendvpd(dst, dst, src, xtmp1, vec_enc);
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vblendvpd(dst, dst, src, xtmp1, vec_enc, false, xtmp1);
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} else {
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assert(opcode == Op_SignumVF, "");
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vsubps(dst, zero, one, vec_enc);
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// if src < 0 ? -1 : 1
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vblendvps(dst, one, dst, src, vec_enc);
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vblendvps(dst, one, dst, src, vec_enc, true, xtmp1);
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// if src == NaN, -0.0 or 0.0 return src.
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vcmpps(xtmp1, src, zero, Assembler::EQ_UQ, vec_enc);
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vblendvps(dst, dst, src, xtmp1, vec_enc);
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vblendvps(dst, dst, src, xtmp1, vec_enc, false, xtmp1);
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}
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}
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@ -3566,6 +3566,56 @@ void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vecto
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}
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}
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// Vector float blend
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// vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
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void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
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// WARN: Allow dst == (src1|src2), mask == scratch
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bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
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bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
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bool dst_available = dst != mask && (dst != src1 || dst != src2);
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if (blend_emulation && scratch_available && dst_available) {
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if (compute_mask) {
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vpsrad(scratch, mask, 32, vector_len);
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mask = scratch;
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}
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if (dst == src1) {
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vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
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vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
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} else {
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vpand (dst, mask, src2, vector_len); // if mask == 1, src2
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vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
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}
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vpor(dst, dst, scratch, vector_len);
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} else {
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Assembler::vblendvps(dst, src1, src2, mask, vector_len);
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}
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}
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// vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
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void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
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// WARN: Allow dst == (src1|src2), mask == scratch
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bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
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bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
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bool dst_available = dst != mask && (dst != src1 || dst != src2);
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if (blend_emulation && scratch_available && dst_available) {
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if (compute_mask) {
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vpxor(scratch, scratch, scratch, vector_len);
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vpcmpgtq(scratch, scratch, mask, vector_len);
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mask = scratch;
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}
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if (dst == src1) {
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vpandn(dst, mask, src1, vector_len); // if mask == 0, src
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vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
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} else {
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vpand (dst, mask, src2, vector_len); // if mask == 1, src2
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vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
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}
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vpor(dst, dst, scratch, vector_len);
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} else {
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Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
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}
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}
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void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
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Assembler::vpcmpeqb(dst, nds, src, vector_len);
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@ -1130,6 +1130,10 @@ public:
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using Assembler::vbroadcastss;
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void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
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// Vector float blend
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void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
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void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
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void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
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void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
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void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
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@ -7801,7 +7801,7 @@ instruct blendvp(vec dst, vec src, vec mask, rxmm0 tmp) %{
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%}
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instruct vblendvpI(legVec dst, legVec src1, legVec src2, legVec mask) %{
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predicate(UseAVX > 0 &&
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predicate(UseAVX > 0 && !EnableX86ECoreOpts &&
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n->in(2)->bottom_type()->isa_vectmask() == NULL &&
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Matcher::vector_length_in_bytes(n) <= 32 &&
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is_integral_type(Matcher::vector_element_basic_type(n)));
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@ -7815,7 +7815,7 @@ instruct vblendvpI(legVec dst, legVec src1, legVec src2, legVec mask) %{
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%}
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instruct vblendvpFD(legVec dst, legVec src1, legVec src2, legVec mask) %{
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predicate(UseAVX > 0 &&
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predicate(UseAVX > 0 && !EnableX86ECoreOpts &&
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n->in(2)->bottom_type()->isa_vectmask() == NULL &&
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Matcher::vector_length_in_bytes(n) <= 32 &&
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!is_integral_type(Matcher::vector_element_basic_type(n)));
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@ -7828,6 +7828,22 @@ instruct vblendvpFD(legVec dst, legVec src1, legVec src2, legVec mask) %{
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ins_pipe( pipe_slow );
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%}
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instruct vblendvp(legVec dst, legVec src1, legVec src2, legVec mask, legVec vtmp) %{
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predicate(UseAVX > 0 && EnableX86ECoreOpts &&
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n->in(2)->bottom_type()->isa_vectmask() == NULL &&
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Matcher::vector_length_in_bytes(n) <= 32);
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match(Set dst (VectorBlend (Binary src1 src2) mask));
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format %{ "vector_blend $dst,$src1,$src2,$mask\t! using $vtmp as TEMP" %}
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effect(TEMP vtmp, TEMP dst);
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ins_encode %{
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int vlen_enc = vector_length_encoding(this);
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__ vpandn($vtmp$$XMMRegister, $mask$$XMMRegister, $src1$$XMMRegister, vlen_enc);
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__ vpand ($dst$$XMMRegister, $mask$$XMMRegister, $src2$$XMMRegister, vlen_enc);
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__ vpor ($dst$$XMMRegister, $dst$$XMMRegister, $vtmp$$XMMRegister, vlen_enc);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct evblendvp64(vec dst, vec src1, vec src2, vec mask, kReg ktmp) %{
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predicate(Matcher::vector_length_in_bytes(n) == 64 &&
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n->in(2)->bottom_type()->isa_vectmask() == NULL);
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@ -4478,34 +4478,15 @@ instruct loadD(regD dst, memory mem)
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ins_pipe(pipe_slow); // XXX
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%}
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// Following pseudo code describes the algorithm for max[FD]:
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// Min algorithm is on similar lines
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// btmp = (b < +0.0) ? a : b
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// atmp = (b < +0.0) ? b : a
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// Tmp = Max_Float(atmp , btmp)
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// Res = (atmp == NaN) ? atmp : Tmp
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// max = java.lang.Math.max(float a, float b)
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instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MaxF a b));
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effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
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format %{
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"vblendvps $btmp,$b,$a,$b \n\t"
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"vblendvps $atmp,$a,$b,$b \n\t"
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"vmaxss $tmp,$atmp,$btmp \n\t"
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"vcmpps.unordered $btmp,$atmp,$atmp \n\t"
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"vblendvps $dst,$tmp,$atmp,$btmp \n\t"
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%}
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format %{ "maxF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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ins_encode %{
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int vector_len = Assembler::AVX_128bit;
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__ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
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__ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
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__ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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__ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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__ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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%}
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__ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
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@ -4527,20 +4508,9 @@ instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MaxD a b));
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effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
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format %{
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"vblendvpd $btmp,$b,$a,$b \n\t"
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"vblendvpd $atmp,$a,$b,$b \n\t"
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"vmaxsd $tmp,$atmp,$btmp \n\t"
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"vcmppd.unordered $btmp,$atmp,$atmp \n\t"
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"vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
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%}
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format %{ "maxD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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ins_encode %{
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int vector_len = Assembler::AVX_128bit;
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__ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
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__ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
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__ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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__ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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__ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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__ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
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@ -4563,20 +4533,9 @@ instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp,
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MinF a b));
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effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
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format %{
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"vblendvps $atmp,$a,$b,$a \n\t"
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"vblendvps $btmp,$b,$a,$a \n\t"
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"vminss $tmp,$atmp,$btmp \n\t"
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"vcmpps.unordered $btmp,$atmp,$atmp \n\t"
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"vblendvps $dst,$tmp,$atmp,$btmp \n\t"
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%}
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format %{ "minF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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ins_encode %{
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int vector_len = Assembler::AVX_128bit;
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__ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
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__ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
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__ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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__ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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__ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
|
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__ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
|
||||
%}
|
||||
ins_pipe( pipe_slow );
|
||||
%}
|
||||
@ -4599,20 +4558,9 @@ instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
|
||||
predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
|
||||
match(Set dst (MinD a b));
|
||||
effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
|
||||
format %{
|
||||
"vblendvpd $atmp,$a,$b,$a \n\t"
|
||||
"vblendvpd $btmp,$b,$a,$a \n\t"
|
||||
"vminsd $tmp,$atmp,$btmp \n\t"
|
||||
"vcmppd.unordered $btmp,$atmp,$atmp \n\t"
|
||||
"vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
|
||||
%}
|
||||
format %{ "minD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
|
||||
ins_encode %{
|
||||
int vector_len = Assembler::AVX_128bit;
|
||||
__ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
|
||||
__ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
|
||||
__ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
|
||||
__ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
|
||||
__ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
|
||||
__ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
|
||||
%}
|
||||
ins_pipe( pipe_slow );
|
||||
%}
|
||||
|
||||
@ -33,6 +33,8 @@
|
||||
|
||||
package compiler.vectorization;
|
||||
|
||||
import java.util.Random;
|
||||
|
||||
import compiler.lib.ir_framework.*;
|
||||
|
||||
public class TestSignumVector {
|
||||
@ -62,12 +64,22 @@ public class TestSignumVector {
|
||||
public void kernel_test_signum_double() {
|
||||
dinp = new double[ARRLEN];
|
||||
dout = new double[ARRLEN];
|
||||
Random rnd = new Random(20);
|
||||
for(int i = 0 ; i < ARRLEN; i++) {
|
||||
dinp[i] = (double)i*1.4;
|
||||
dinp[i] = (i-ARRLEN/2)*rnd.nextDouble();
|
||||
}
|
||||
for (int i = 0; i < ITERS; i++) {
|
||||
test_signum_double(dout , dinp);
|
||||
}
|
||||
for(int i = 0 ; i < ARRLEN; i++) {
|
||||
if (i-ARRLEN/2<0) {
|
||||
if (dout[i] != -1.0) throw new RuntimeException("Expected negative numbers in first half of array: " + java.util.Arrays.toString(dout));
|
||||
} else if (i-ARRLEN/2==0) {
|
||||
if (dout[i] != 0) throw new RuntimeException("Expected zero in the middle of array: " + java.util.Arrays.toString(dout));
|
||||
} else {
|
||||
if (dout[i] != 1.0) throw new RuntimeException("Expected positive numbers in second half of array: " + java.util.Arrays.toString(dout));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@Test
|
||||
@ -82,11 +94,21 @@ public class TestSignumVector {
|
||||
public void kernel_test_round() {
|
||||
finp = new float[ARRLEN];
|
||||
fout = new float[ARRLEN];
|
||||
Random rnd = new Random(20);
|
||||
for(int i = 0 ; i < ARRLEN; i++) {
|
||||
finp[i] = (float)i*1.4f;
|
||||
finp[i] = (i-ARRLEN/2)*rnd.nextFloat();
|
||||
}
|
||||
for (int i = 0; i < ITERS; i++) {
|
||||
test_signum_float(fout , finp);
|
||||
}
|
||||
for(int i = 0 ; i < ARRLEN; i++) {
|
||||
if (i-ARRLEN/2<0) {
|
||||
if (fout[i] != -1.0) throw new RuntimeException("Expected negative numbers in first half of array: " + java.util.Arrays.toString(fout));
|
||||
} else if (i-ARRLEN/2==0) {
|
||||
if (fout[i] != 0) throw new RuntimeException("Expected zero in the middle of array: " + java.util.Arrays.toString(fout));
|
||||
} else {
|
||||
if (fout[i] != 1.0) throw new RuntimeException("Expected positive numbers in second half of array: " + java.util.Arrays.toString(fout));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -42,6 +42,7 @@
|
||||
package compiler.vectorization.runner;
|
||||
|
||||
import compiler.lib.ir_framework.*;
|
||||
import java.util.Random;
|
||||
|
||||
public class BasicDoubleOpTest extends VectorizationTestRunner {
|
||||
|
||||
@ -50,11 +51,63 @@ public class BasicDoubleOpTest extends VectorizationTestRunner {
|
||||
private double[] a;
|
||||
private double[] b;
|
||||
private double[] c;
|
||||
private double[] d;
|
||||
private double[] e;
|
||||
|
||||
public BasicDoubleOpTest() {
|
||||
// Positive test values sign | exponent | mantisa
|
||||
double smallPositive = Double.longBitsToDouble(0<<63 | 0x03f << 52 | 0x30000f);
|
||||
double positive = Double.longBitsToDouble(0<<63 | 0x07f << 52 | 0x30000f);
|
||||
double bigPositive = Double.longBitsToDouble(0<<63 | 0x07f << 52 | 0x30100f);
|
||||
double biggerPositive = Double.longBitsToDouble(0<<63 | 0x7fe << 52 | 0x30000f);
|
||||
double maxPositive = Double.MAX_VALUE;
|
||||
|
||||
// Special positive
|
||||
double nan1 = Double.longBitsToDouble(0<<63 | 0x7ff << 52 | 0x7fffff);
|
||||
double nan2 = Double.longBitsToDouble(0<<63 | 0x7ff << 52 | 0x30000f);
|
||||
double inf = Double.longBitsToDouble(0<<63 | 0x7ff << 52);
|
||||
double zero = 0.0;
|
||||
|
||||
// Negative test values sign | exponent | mantisa
|
||||
double smallNegative = Double.longBitsToDouble(1<<63 | 0x003 << 52 | 0x30000f);
|
||||
double negative = Double.longBitsToDouble(1<<63 | 0x783 << 52 | 0x30100f);
|
||||
double bigNegative = Double.longBitsToDouble(1<<63 | 0x783 << 52 | 0x30000f);
|
||||
double biggerNegative = Double.longBitsToDouble(1<<63 | 0x786 << 52 | 0x30000f);
|
||||
double maxNegative = Double.longBitsToDouble(1<<63 | 0x7fe << 52 | 0x7fffff);
|
||||
|
||||
// Special negative
|
||||
double nNan1 = Double.longBitsToDouble(1<<63 | 0x7ff << 52 | 0x7fffff);
|
||||
double nNan2 = Double.longBitsToDouble(1<<63 | 0x7ff << 52 | 0x30000f);
|
||||
double nInf = Double.longBitsToDouble(1<<63 | 0x7ff << 52);
|
||||
double nZero = -0.0;
|
||||
|
||||
double[] numberList = new double[] {
|
||||
nInf, maxNegative, biggerNegative, bigNegative, negative, smallNegative, nZero,
|
||||
zero, smallPositive, positive, bigPositive, biggerPositive, maxPositive, inf,
|
||||
nan1, nan2, nNan1, nNan2
|
||||
};
|
||||
|
||||
Random rnd = new Random(10);
|
||||
a = new double[SIZE];
|
||||
b = new double[SIZE];
|
||||
c = new double[SIZE];
|
||||
d = new double[SIZE];
|
||||
e = new double[SIZE];
|
||||
|
||||
for (int i = 0; i < SIZE;) {
|
||||
for (int j = 0; j < numberList.length && i < SIZE; j++, i++) {
|
||||
for (int k = j; k < numberList.length && i < SIZE; k++, i++) {
|
||||
if (rnd.nextBoolean()) {
|
||||
d[i] = numberList[j];
|
||||
e[i] = numberList[k];
|
||||
} else {
|
||||
d[i] = numberList[k];
|
||||
e[i] = numberList[j];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
a[i] = 850.0 * i + 22222.22;
|
||||
b[i] = -12345.678;
|
||||
@ -179,7 +232,7 @@ public class BasicDoubleOpTest extends VectorizationTestRunner {
|
||||
public double[] vectorMax() {
|
||||
double[] res = new double[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
res[i] = Math.max(a[i], b[i]);
|
||||
res[i] = Math.max(d[i], e[i]);
|
||||
}
|
||||
return res;
|
||||
}
|
||||
@ -190,7 +243,7 @@ public class BasicDoubleOpTest extends VectorizationTestRunner {
|
||||
public double[] vectorMin() {
|
||||
double[] res = new double[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
res[i] = Math.min(a[i], b[i]);
|
||||
res[i] = Math.min(d[i], e[i]);
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
@ -42,6 +42,7 @@
|
||||
package compiler.vectorization.runner;
|
||||
|
||||
import compiler.lib.ir_framework.*;
|
||||
import java.util.Random;
|
||||
|
||||
public class BasicFloatOpTest extends VectorizationTestRunner {
|
||||
|
||||
@ -50,11 +51,72 @@ public class BasicFloatOpTest extends VectorizationTestRunner {
|
||||
private float[] a;
|
||||
private float[] b;
|
||||
private float[] c;
|
||||
private float[] d;
|
||||
private float[] e;
|
||||
|
||||
public BasicFloatOpTest() {
|
||||
// Positive test values sign | exponent | mantisa
|
||||
float smallPositive = Float.intBitsToFloat(0<<31 | 0x3f << 23 | 0x30000f);
|
||||
float positive = Float.intBitsToFloat(0<<31 | 0x7f << 23 | 0x30000f);
|
||||
float bigPositive = Float.intBitsToFloat(0<<31 | 0x7f << 23 | 0x30100f);
|
||||
float biggerPositive = Float.intBitsToFloat(0<<31 | 0xfe << 23 | 0x30000f);
|
||||
float maxPositive = Float.MAX_VALUE;
|
||||
|
||||
// Special positive
|
||||
float nan1 = Float.intBitsToFloat(0<<31 | 0xff << 23 | 0x7fffff);
|
||||
float nan2 = Float.intBitsToFloat(0<<31 | 0xff << 23 | 0x30000f);
|
||||
float inf = Float.intBitsToFloat(0<<31 | 0xff << 23);
|
||||
float zero = 0.0f;
|
||||
|
||||
// Negative test values sign | exponent | mantisa
|
||||
float smallNegative = Float.intBitsToFloat(1<<31 | 0x03 << 23 | 0x30000f);
|
||||
float negative = Float.intBitsToFloat(1<<31 | 0x83 << 23 | 0x30100f);
|
||||
float bigNegative = Float.intBitsToFloat(1<<31 | 0x83 << 23 | 0x30000f);
|
||||
float biggerNegative = Float.intBitsToFloat(1<<31 | 0x86 << 23 | 0x30000f);
|
||||
float maxNegative = Float.intBitsToFloat(1<<31 | 0xfe << 23 | 0x7fffff);
|
||||
|
||||
// Special negative
|
||||
float nNan1 = Float.intBitsToFloat(1<<31 | 0xff << 23 | 0x7fffff);
|
||||
float nNan2 = Float.intBitsToFloat(1<<31 | 0xff << 23 | 0x30000f);
|
||||
float nInf = Float.intBitsToFloat(1<<31 | 0xff << 23);
|
||||
float nZero = -0.0f;
|
||||
|
||||
float[] orderedList = new float[] {
|
||||
nInf, maxNegative, biggerNegative, bigNegative, negative, smallNegative, nZero,
|
||||
zero, smallPositive, positive, bigPositive, biggerPositive, maxPositive, inf
|
||||
};
|
||||
|
||||
float[] NaNs = new float[] {
|
||||
nan1, nan2, nNan1, nNan2
|
||||
};
|
||||
|
||||
float[] numberList = new float[] {
|
||||
nInf, maxNegative, biggerNegative, bigNegative, negative, smallNegative, nZero,
|
||||
zero, smallPositive, positive, bigPositive, biggerPositive, maxPositive, inf,
|
||||
nan1, nan2, nNan1, nNan2
|
||||
};
|
||||
|
||||
Random rnd = new Random(11);
|
||||
a = new float[SIZE];
|
||||
b = new float[SIZE];
|
||||
c = new float[SIZE];
|
||||
d = new float[SIZE];
|
||||
e = new float[SIZE];
|
||||
|
||||
for (int i = 0; i < SIZE;) {
|
||||
for (int j = 0; j < numberList.length && i < SIZE; j++, i++) {
|
||||
for (int k = j; k < numberList.length && i < SIZE; k++, i++) {
|
||||
if (rnd.nextBoolean()) {
|
||||
d[i] = numberList[j];
|
||||
e[i] = numberList[k];
|
||||
} else {
|
||||
d[i] = numberList[k];
|
||||
e[i] = numberList[j];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
a[i] = 850.0f * i + 22222.22f;
|
||||
b[i] = -12345.678f;
|
||||
@ -146,7 +208,7 @@ public class BasicFloatOpTest extends VectorizationTestRunner {
|
||||
public float[] vectorMax() {
|
||||
float[] res = new float[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
res[i] = Math.max(a[i], b[i]);
|
||||
res[i] = Math.max(d[i], e[i]);
|
||||
}
|
||||
return res;
|
||||
}
|
||||
@ -157,7 +219,7 @@ public class BasicFloatOpTest extends VectorizationTestRunner {
|
||||
public float[] vectorMin() {
|
||||
float[] res = new float[SIZE];
|
||||
for (int i = 0; i < SIZE; i++) {
|
||||
res[i] = Math.min(a[i], b[i]);
|
||||
res[i] = Math.min(d[i], e[i]);
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user