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8151340: aarch64: prefetch the destination word for write prior to ldxr/stxr loops
Aarch64: add prefetch for write prior to ldxr/stxr loops. Reviewed-by: aph
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5f3739f293
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@ -4683,6 +4683,7 @@ encode %{
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__ br(Assembler::EQ, cont);
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} else {
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Label retry_load;
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__ prfm(Address(oop), PSTL1STRM);
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__ bind(retry_load);
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__ ldaxr(tmp, oop);
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__ cmp(tmp, disp_hdr);
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@ -4737,6 +4738,7 @@ encode %{
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__ cmp(rscratch1, disp_hdr);
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} else {
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Label retry_load, fail;
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__ prfm(Address(tmp), PSTL1STRM);
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__ bind(retry_load);
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__ ldaxr(rscratch1, tmp);
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__ cmp(disp_hdr, rscratch1);
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@ -4830,6 +4832,7 @@ encode %{
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__ cmp(tmp, box);
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} else {
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Label retry_load;
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__ prfm(Address(oop), PSTL1STRM);
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__ bind(retry_load);
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__ ldxr(tmp, oop);
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__ cmp(box, tmp);
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@ -1565,6 +1565,7 @@ void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
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Label retry_load, nope;
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// flush and load exclusive from the memory location
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// and fail if it is not what we expect
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__ prfm(Address(addr), PSTL1STRM);
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__ bind(retry_load);
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__ ldaxrw(rscratch1, addr);
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__ cmpw(rscratch1, cmpval);
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@ -1590,6 +1591,7 @@ void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
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Label retry_load, nope;
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// flush and load exclusive from the memory location
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// and fail if it is not what we expect
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__ prfm(Address(addr), PSTL1STRM);
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__ bind(retry_load);
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__ ldaxr(rscratch1, addr);
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__ cmp(rscratch1, cmpval);
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@ -3170,6 +3172,7 @@ void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr
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}
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Label again;
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__ lea(tmp, addr);
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__ prfm(Address(tmp), PSTL1STRM);
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__ bind(again);
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(_masm->*lda)(dst, tmp);
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(_masm->*add)(rscratch1, dst, inc);
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@ -3189,6 +3192,7 @@ void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr
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assert_different_registers(obj, addr.base(), tmp, rscratch2, dst);
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Label again;
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__ lea(tmp, addr);
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__ prfm(Address(tmp), PSTL1STRM);
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__ bind(again);
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(_masm->*lda)(dst, tmp);
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(_masm->*stl)(rscratch2, obj, tmp);
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@ -1638,6 +1638,7 @@ Address MacroAssembler::form_address(Register Rd, Register base, long byte_offse
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void MacroAssembler::atomic_incw(Register counter_addr, Register tmp, Register tmp2) {
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Label retry_load;
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prfm(Address(counter_addr), PSTL1STRM);
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bind(retry_load);
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// flush and load exclusive from the memory location
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ldxrw(tmp, counter_addr);
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@ -2078,7 +2079,7 @@ void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Reg
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membar(AnyAny);
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} else {
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Label retry_load, nope;
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prfm(Address(addr), PSTL1STRM);
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bind(retry_load);
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// flush and load exclusive from the memory location
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// and fail if it is not what we expect
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@ -2114,7 +2115,7 @@ void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Regis
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membar(AnyAny);
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} else {
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Label retry_load, nope;
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prfm(Address(addr), PSTL1STRM);
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bind(retry_load);
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// flush and load exclusive from the memory location
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// and fail if it is not what we expect
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@ -2149,6 +2150,7 @@ void MacroAssembler::cmpxchg(Register addr, Register expected,
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} else {
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BLOCK_COMMENT("cmpxchg {");
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Label retry_load, done;
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prfm(Address(addr), PSTL1STRM);
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bind(retry_load);
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load_exclusive(tmp, addr, size, acquire);
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if (size == xword)
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@ -2177,6 +2179,7 @@ void MacroAssembler::atomic_##OP(Register prev, RegisterOrConstant incr, Registe
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result = different(prev, incr, addr) ? prev : rscratch2; \
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\
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Label retry_load; \
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prfm(Address(addr), PSTL1STRM); \
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bind(retry_load); \
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LDXR(result, addr); \
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OP(rscratch1, result, incr); \
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@ -2199,6 +2202,7 @@ void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) {
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result = different(prev, newv, addr) ? prev : rscratch2; \
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\
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Label retry_load; \
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prfm(Address(addr), PSTL1STRM); \
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bind(retry_load); \
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LDXR(result, addr); \
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STXR(rscratch1, newv, addr); \
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@ -1984,6 +1984,7 @@ void TemplateInterpreterGenerator::count_bytecode() {
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__ push(rscratch3);
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Label L;
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__ mov(rscratch2, (address) &BytecodeCounter::_counter_value);
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__ prfm(Address(rscratch2), PSTL1STRM);
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__ bind(L);
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__ ldxr(rscratch1, rscratch2);
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__ add(rscratch1, rscratch1, 1);
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