infernap12/jdk
1
0
Fork 0
mirror of https://github.com/openjdk/jdk.git synced 2026-02-28 19:20:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

8182583: AArch64: FMA Vectorization on aarch64

Browse Source 
Reviewed-by: aph
This commit is contained in:
Yang Zhang 2017-06-23 09:25:27 +08:00 committed by Ningsheng Jian
parent e62cebc78a
commit 77bc4e75e3
2 changed files with 89 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

87
hotspot/src/cpu/aarch64/vm/aarch64.ad
View File

@ -16777,6 +16777,48 @@ instruct vmla4I(vecX dst, vecX src1, vecX src2)
ins_pipe(vmla128);
%}
// dst + src1 * src2
instruct vmla2F(vecD dst, vecD src1, vecD src2) %{
predicate(UseFMA && n->as_Vector()->length() == 2);
match(Set dst (FmaVF dst (Binary src1 src2)));
format %{ "fmla $dst,$src1,$src2\t# vector (2S)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmla(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp64);
%}
// dst + src1 * src2
instruct vmla4F(vecX dst, vecX src1, vecX src2) %{
predicate(UseFMA && n->as_Vector()->length() == 4);
match(Set dst (FmaVF dst (Binary src1 src2)));
format %{ "fmla $dst,$src1,$src2\t# vector (4S)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmla(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp128);
%}
// dst + src1 * src2
instruct vmla2D(vecX dst, vecX src1, vecX src2) %{
predicate(UseFMA && n->as_Vector()->length() == 2);
match(Set dst (FmaVD dst (Binary src1 src2)));
format %{ "fmla $dst,$src1,$src2\t# vector (2D)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmla(as_FloatRegister($dst$$reg), __ T2D,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp128);
%}
// --------------------------------- MLS --------------------------------------
instruct vmls4S(vecD dst, vecD src1, vecD src2)
@ -16836,6 +16878,51 @@ instruct vmls4I(vecX dst, vecX src1, vecX src2)
ins_pipe(vmla128);
%}
// dst - src1 * src2
instruct vmls2F(vecD dst, vecD src1, vecD src2) %{
predicate(UseFMA && n->as_Vector()->length() == 2);
match(Set dst (FmaVF dst (Binary (NegVF src1) src2)));
match(Set dst (FmaVF dst (Binary src1 (NegVF src2))));
format %{ "fmls $dst,$src1,$src2\t# vector (2S)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmls(as_FloatRegister($dst$$reg), __ T2S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp64);
%}
// dst - src1 * src2
instruct vmls4F(vecX dst, vecX src1, vecX src2) %{
predicate(UseFMA && n->as_Vector()->length() == 4);
match(Set dst (FmaVF dst (Binary (NegVF src1) src2)));
match(Set dst (FmaVF dst (Binary src1 (NegVF src2))));
format %{ "fmls $dst,$src1,$src2\t# vector (4S)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmls(as_FloatRegister($dst$$reg), __ T4S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp128);
%}
// dst - src1 * src2
instruct vmls2D(vecX dst, vecX src1, vecX src2) %{
predicate(UseFMA && n->as_Vector()->length() == 2);
match(Set dst (FmaVD dst (Binary (NegVD src1) src2)));
match(Set dst (FmaVD dst (Binary src1 (NegVD src2))));
format %{ "fmls $dst,$src1,$src2\t# vector (2D)" %}
ins_cost(INSN_COST);
ins_encode %{
__ fmls(as_FloatRegister($dst$$reg), __ T2D,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(vmuldiv_fp128);
%}
// --------------------------------- DIV --------------------------------------
instruct vdiv2F(vecD dst, vecD src1, vecD src2)

2
hotspot/src/cpu/aarch64/vm/assembler_aarch64.hpp
View File

@ -2201,6 +2201,8 @@ public:
INSN(fdiv, 1, 0, 0b111111);
INSN(fmul, 1, 0, 0b110111);
INSN(fsub, 0, 1, 0b110101);
INSN(fmla, 0, 0, 0b110011);
INSN(fmls, 0, 1, 0b110011);
#undef INSN