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8381617: vm_version_windows_aarch64.cpp: PF_ARM_SVE_INSTRUCTIONS_AVAILABLE undeclared identifier

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Reviewed-by: kvn, macarte
This commit is contained in:
Ashay Rane 2026-04-20 16:29:13 +00:00 committed by Vladimir Kozlov
parent ae5b765e38
commit 78e962592f
5 changed files with 137 additions and 85 deletions
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19
src/hotspot/os_cpu/windows_aarch64/sve_windows_aarch64.S
View File

@ -24,19 +24,26 @@
; Support for int get_sve_vector_length();
;
; Returns the current SVE vector length in bytes.
; This function uses the INCB instruction which increments a register
; by the number of bytes in an SVE vector register.
; This function uses the RDVL instruction which reads a multiple of the
; vector register size into a scalar register.
;
; Note: This function will fault if SVE is not available or enabled.
; The caller must ensure SVE support is detected before calling.
; Note: This function will fault if SVE is not available or enabled. The
; caller must ensure SVE support is detected before calling.
ALIGN 4
EXPORT get_sve_vector_length
AREA sve_text, CODE
get_sve_vector_length
mov x0, #0
incb x0
; Older versions of Visual Studio aren't aware of SVE mnemonics, so we use
; the raw instruction encoding to satisfy the compiler. This function call
; is gated by `VM_Version::supports_sve()`, so this instruction will never
; run on non-SVE hardware.
;
; See https://www.scs.stanford.edu/~zyedidia/arm64/rdvl_r_i.html for a quick
; reference to the instruction encoding.
DCD 0x04BF5020 ; rdvl x0, #1 (i.e. x0 = 1 * vector_length_in_bytes)
ret
END

47
src/hotspot/os_cpu/windows_aarch64/vm_version_windows_aarch64.cpp
View File

@ -26,19 +26,52 @@
#include "runtime/os.hpp"
#include "runtime/vm_version.hpp"
// Assembly function to get SVE vector length using INCB instruction
// Since PF_ARM_SVE_INSTRUCTIONS_AVAILABLE and related constants were added in
// Windows 11 (version 24H2) and in Windows Server 2025, we define them here for
// compatibility with older SDK versions.
#ifndef PF_ARM_SVE_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE 46
#endif
#ifndef PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE 47
#endif
#ifndef PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE 51
#endif
#ifndef PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE 64
#endif
#ifndef PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE
#define PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE 65
#endif
#ifndef PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE
#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE 67
#endif
// Assembly function to get SVE vector length using RDVL instruction
extern "C" int get_sve_vector_length();
int VM_Version::get_current_sve_vector_length() {
assert(VM_Version::supports_sve(), "should not call this");
// Use assembly instruction to get the actual SVE vector length
return VM_Version::supports_sve() ? get_sve_vector_length() : 0; // This value is in bytes
return VM_Version::supports_sve() ? get_sve_vector_length() : 0;
}
int VM_Version::set_and_get_current_sve_vector_length(int length) {
assert(VM_Version::supports_sve(), "should not call this");
// Use assembly instruction to get the SVE vector length
return VM_Version::supports_sve() ? get_sve_vector_length() : 0; // This value is in bytes
// Unlike Linux, Windows does not present a way to modify the VL (the
// rationale is that the OS expects the application to use the maximum vector
// length supported by the hardware), so we simply return the current VL. If
// the user sets `MaxVectorSize` that is not the same as the maximum possible
// vector length, then the caller (`VM_Version::initialize()`) will print a
// warning, set `MaxVectorSize` to the value returned by this function, and
// move on.
return VM_Version::supports_sve() ? get_sve_vector_length() : 0;
}
void VM_Version::get_os_cpu_info() {
@ -67,6 +100,10 @@ void VM_Version::get_os_cpu_info() {
if (IsProcessorFeaturePresent(PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE)) {
set_feature(CPU_SVEBITPERM);
}
if (IsProcessorFeaturePresent(PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE)) {
set_feature(CPU_FPHP);
set_feature(CPU_ASIMDHP);
}
if (IsProcessorFeaturePresent(PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE)) {
set_feature(CPU_SHA3);
}

18
test/hotspot/jtreg/compiler/c2/irTests/TestFloat16ScalarOperations.java
View File

@ -24,7 +24,7 @@
/**
* @test
* @bug 8308363 8336406
* @bug 8308363 8336406 8381617
* @summary Validate compiler IR for various Float16 scalar operations.
* @modules jdk.incubator.vector
* @requires vm.compiler2.enabled
@ -714,9 +714,13 @@ public class TestFloat16ScalarOperations {
@Test
@IR(counts = {IRNode.FMA_HF, " 0 ", IRNode.REINTERPRET_S2HF, " 0 ", IRNode.REINTERPRET_HF2S, " 0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"},
// On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
applyIfPlatform = {"windows", "false"})
@IR(counts = {IRNode.FMA_HF, " 0 ", IRNode.REINTERPRET_S2HF, " 0 ", IRNode.REINTERPRET_HF2S, " 0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"},
// On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
applyIfPlatform = {"windows", "false"})
@Warmup(10000)
public void testFMAConstantFolding() {
// If any argument is NaN, the result is NaN.
@ -752,9 +756,13 @@ public class TestFloat16ScalarOperations {
@Test
@IR(failOn = {IRNode.ADD_HF, IRNode.SUB_HF, IRNode.MUL_HF, IRNode.DIV_HF, IRNode.SQRT_HF, IRNode.FMA_HF},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zfh", "true"},
// On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
applyIfPlatform = {"windows", "false"})
@IR(failOn = {IRNode.ADD_HF, IRNode.SUB_HF, IRNode.MUL_HF, IRNode.DIV_HF, IRNode.SQRT_HF, IRNode.FMA_HF},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"},
// On Windows, both GCC and MSVC don't set __STDC_IEC_559__, so FMAs on constants are not folded.
applyIfPlatform = {"windows", "false"})
@Warmup(10000)
public void testRounding1() {
dst[0] = float16ToRawShortBits(add(RANDOM1, RANDOM2));

112
test/hotspot/jtreg/compiler/loopopts/superword/TestReductions.java
View File

@ -33,7 +33,7 @@
/*
* @test id=vanilla
* @bug 8340093 8342095
* @bug 8340093 8342095 8381617
* @summary Test vectorization of reduction loops.
* @modules jdk.incubator.vector
* @library /test/lib /
@ -42,7 +42,7 @@
/*
* @test id=force-vectorization
* @bug 8340093 8342095
* @bug 8340093 8342095 8381617
* @summary Test vectorization of reduction loops.
* @modules jdk.incubator.vector
* @library /test/lib /
@ -1802,7 +1802,7 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MUL_REDUCTION_VL, "> 0",
IRNode.MUL_VL, "> 0"}, // vector accumulator
applyIfCPUFeature = {"avx512dq", "true"},
applyIfCPUFeatureOr = {"avx512dq", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512dq", "false", "sse4.1", "true"})
@ -1810,7 +1810,7 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MUL_REDUCTION_VL, "> 0",
IRNode.MUL_VL, "= 0"}, // Reduction NOT moved out of loop
applyIfCPUFeatureOr = {"asimd", "true"},
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
// Note: NEON does not support MulVL for auto vectorization. There is
// a scalarized implementation, but that is not profitable for
@ -1874,10 +1874,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.AND_REDUCTION_V, "> 0",
IRNode.AND_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While AndReductionV is implemented in NEON (see longAndSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -1895,10 +1895,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.OR_REDUCTION_V, "> 0",
IRNode.OR_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While OrReductionV is implemented in NEON (see longOrSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -1916,10 +1916,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.XOR_REDUCTION_V, "> 0",
IRNode.XOR_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longXorSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -1937,10 +1937,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.ADD_REDUCTION_VL, "> 0",
IRNode.ADD_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longAddSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -1958,13 +1958,13 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MUL_REDUCTION_VL, "> 0",
IRNode.MUL_VL, "> 0"},
applyIfCPUFeature = {"avx512dq", "true"},
applyIfCPUFeatureOr = {"avx512dq", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512dq", "false", "sse4.1", "true"})
// I think this could vectorize, but currently does not. Filed: JDK-8370673
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// MulVL is not implemented on NEON, so we also not have the reduction.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -1982,13 +1982,13 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MIN_REDUCTION_V, "> 0",
IRNode.MIN_VL, "> 0"},
applyIfCPUFeature = {"avx512", "true"},
applyIfCPUFeatureOr = {"avx512", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512", "false", "avx2", "true"})
// I think this could vectorize, but currently does not. Filed: JDK-8370671
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longMinSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2006,13 +2006,13 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MAX_REDUCTION_V, "> 0",
IRNode.MAX_VL, "> 0"},
applyIfCPUFeature = {"avx512", "true"},
applyIfCPUFeatureOr = {"avx512", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512", "false", "avx2", "true"})
// I think this could vectorize, but currently does not. Filed: JDK-8370671
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longMaxSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2031,10 +2031,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.AND_REDUCTION_V, "> 0",
IRNode.AND_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While AndReductionV is implemented in NEON (see longAndSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2052,10 +2052,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.OR_REDUCTION_V, "> 0",
IRNode.OR_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While OrReductionV is implemented in NEON (see longOrSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2073,10 +2073,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.XOR_REDUCTION_V, "> 0",
IRNode.XOR_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longXorSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2094,10 +2094,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.ADD_REDUCTION_VL, "> 0",
IRNode.ADD_VL, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longAddSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2115,7 +2115,7 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MUL_REDUCTION_VL, "> 0",
IRNode.MUL_VL, "> 0"},
applyIfCPUFeature = {"avx512dq", "true"},
applyIfCPUFeatureOr = {"avx512dq", "true", "sve", "true"},
applyIfAnd = {"AutoVectorizationOverrideProfitability", "> 0",
"LoopUnrollLimit", ">= 1000"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2126,7 +2126,7 @@ public class TestReductions {
// If you can eliminate this exception for LoopUnrollLimit, please remove
// the flag completely from the test, also the "addFlags" at the top.
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// MulVL is not implemented on NEON, so we also not have the reduction.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2144,13 +2144,13 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MIN_REDUCTION_V, "> 0",
IRNode.MIN_VL, "> 0"},
applyIfCPUFeature = {"avx512", "true"},
applyIfCPUFeatureOr = {"avx512", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512", "false", "avx2", "true"})
// I think this could vectorize, but currently does not. Filed: JDK-8370671
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longMinSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2168,13 +2168,13 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_L, "> 0",
IRNode.MAX_REDUCTION_V, "> 0",
IRNode.MAX_VL, "> 0"},
applyIfCPUFeature = {"avx512", "true"},
applyIfCPUFeatureOr = {"avx512", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"avx512", "false", "avx2", "true"})
// I think this could vectorize, but currently does not. Filed: JDK-8370671
@IR(failOn = IRNode.LOAD_VECTOR_L,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// While MaxReductionV is implemented in NEON (see longMaxSimple), MulVL is not.
// Filed: JDK-8370686
@IR(failOn = IRNode.LOAD_VECTOR_L,
@ -2193,10 +2193,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.ADD_REDUCTION_V, "> 0",
IRNode.ADD_VF, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "= 2"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2217,10 +2217,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.MUL_REDUCTION_VF, "> 0",
IRNode.MUL_VF, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "= 2"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2276,10 +2276,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.ADD_REDUCTION_V, "> 0",
IRNode.ADD_VF, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2297,10 +2297,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.MUL_REDUCTION_VF, "> 0",
IRNode.MUL_VF, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2353,10 +2353,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.ADD_REDUCTION_V, "> 0",
IRNode.ADD_VF, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2374,10 +2374,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_F, "> 0",
IRNode.MUL_REDUCTION_VF, "> 0",
IRNode.MUL_VF, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_F,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_F,
@ -2430,10 +2430,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.ADD_REDUCTION_VD, "> 0",
IRNode.ADD_VD, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "= 2"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,
@ -2454,10 +2454,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.MUL_REDUCTION_VD, "> 0",
IRNode.MUL_VD, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "= 2"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,
@ -2513,10 +2513,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.ADD_REDUCTION_V, "> 0",
IRNode.ADD_VD, "= 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,
@ -2534,10 +2534,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.MUL_REDUCTION_VD, "> 0",
IRNode.MUL_VD, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,
@ -2590,10 +2590,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.ADD_REDUCTION_V, "> 0",
IRNode.ADD_VD, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,
@ -2611,10 +2611,10 @@ public class TestReductions {
@IR(counts = {IRNode.LOAD_VECTOR_D, "> 0",
IRNode.MUL_REDUCTION_VD, "> 0",
IRNode.MUL_VD, "> 0"},
applyIfCPUFeature = {"sse4.1", "true"},
applyIfCPUFeatureOr = {"sse4.1", "true", "sve", "true"},
applyIf = {"AutoVectorizationOverrideProfitability", "> 0"})
@IR(failOn = IRNode.LOAD_VECTOR_D,
applyIfCPUFeatureAnd = {"asimd", "true"})
applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
// I think this could vectorize, but currently does not. Filed: JDK-8370677
// But: it is not clear that it would be profitable, given the sequential reduction.
@IR(failOn = IRNode.LOAD_VECTOR_D,

26
test/hotspot/jtreg/compiler/vectorization/TestFloat16VectorOperations.java
View File

@ -24,7 +24,7 @@
/**
* @test
* @bug 8346236
* @bug 8346236 8381617
* @summary Auto-vectorization support for various Float16 operations
* @modules jdk.incubator.vector
* @library /test/lib /
@ -96,7 +96,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.ADD_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.ADD_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorAddFloat16() {
@ -117,7 +117,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.SUB_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.SUB_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorSubFloat16() {
@ -138,7 +138,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.MUL_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.MUL_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorMulFloat16() {
@ -158,7 +158,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.DIV_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.DIV_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorDivFloat16() {
@ -178,7 +178,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.MIN_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.MIN_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorMinFloat16() {
@ -198,7 +198,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.MAX_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.MAX_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorMaxFloat16() {
@ -218,7 +218,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.SQRT_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.SQRT_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorSqrtFloat16() {
@ -238,7 +238,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorFmaFloat16() {
@ -260,7 +260,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorFmaFloat16ScalarMixedConstants() {
@ -283,7 +283,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.FMA_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorFmaFloat16MixedConstants() {
@ -306,7 +306,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.FMA_VHF, " 0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.FMA_VHF, " 0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorFmaFloat16AllConstants() {
@ -333,7 +333,7 @@ public class TestFloat16VectorOperations {
@Test
@Warmup(50)
@IR(counts = {IRNode.ADD_VHF, " >0 "},
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true", "sve", "true"})
applyIfCPUFeatureOr = {"avx512_fp16", "true", "zvfh", "true"})
@IR(counts = {IRNode.ADD_VHF, " >0 "},
applyIfCPUFeatureAnd = {"fphp", "true", "asimdhp", "true"})
public void vectorAddConstInputFloat16() {