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8259601: AArch64: Fix reinterpretX2D match rule issue

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Reviewed-by: adinn, njian
This commit is contained in:
Xiaohong Gong 2021-01-13 05:52:45 +00:00 committed by Ningsheng Jian
parent 15dd8f3aa4
commit 793017d2ed
2 changed files with 40 additions and 24 deletions
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23
src/hotspot/cpu/aarch64/aarch64_neon.ad
View File

@ -1,5 +1,5 @@
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, Arm Limited. All rights reserved.
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -84,9 +84,11 @@ instruct reinterpretD2X(vecX dst, vecD src)
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src" %}
format %{ " # reinterpret $dst,$src\t# D2X" %}
ins_encode %{
// If register is the same, then move is not needed.
// If registers are the same, no register move is required - the
// upper 64 bits of 'src' are expected to have been initialized
// to zero.
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
@ -102,14 +104,13 @@ instruct reinterpretX2D(vecD dst, vecX src)
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src" %}
format %{ " # reinterpret $dst,$src\t# X2D" %}
ins_encode %{
// If register is the same, then move is not needed.
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
}
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
// the "dst" register must be cleared to zero.
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
%}
ins_pipe(vlogical64);
%}

41
src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
View File

@ -1,5 +1,5 @@
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, Arm Limited. All rights reserved.
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@ -97,16 +97,18 @@ dnl $1 $2
REINTERPRET(D, 8)
REINTERPRET(X, 16)
dnl
define(`REINTERPRET_X', `
instruct reinterpret$1`'2$2`'(vec$2 dst, vec$1 src)
instruct reinterpretD2X(vecX dst, vecD src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == $3 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == $4);
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src" %}
format %{ " # reinterpret $dst,$src\t# D2X" %}
ins_encode %{
// If register is the same, then move is not needed.
// If registers are the same, no register move is required - the
// upper 64 bits of 'src' are expected to have been initialized
// to zero.
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
@ -114,11 +116,24 @@ instruct reinterpret$1`'2$2`'(vec$2 dst, vec$1 src)
}
%}
ins_pipe(vlogical64);
%}')dnl
dnl $1 $2 $3 $4
REINTERPRET_X(D, X, 16, 8)
REINTERPRET_X(X, D, 8, 16)
dnl
%}
instruct reinterpretX2D(vecD dst, vecX src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src\t# X2D" %}
ins_encode %{
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
// the "dst" register must be cleared to zero.
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
%}
ins_pipe(vlogical64);
%}
// ------------------------------ Vector cast -------------------------------
dnl