From 79880e56375a1c17ec6ad29bb0ab01868bc956ff Mon Sep 17 00:00:00 2001 From: Hamlin Li Date: Mon, 3 Mar 2025 18:28:28 +0000 Subject: [PATCH] 8351033: RISC-V: TestFloat16ScalarOperations asserts with offset (4210) is too large to be patched in one beq/bge/bgeu/blt/bltu/bne instruction! Reviewed-by: fyang --- src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp index e52cf7565be..f145eb879df 100644 --- a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp +++ b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp @@ -2287,7 +2287,7 @@ void C2_MacroAssembler::float16_to_float(FloatRegister dst, Register src, Regist mv(t0, 0x7c00); andr(tmp, src, t0); // jump to stub processing NaN and Inf cases. - beq(t0, tmp, stub->entry()); + beq(t0, tmp, stub->entry(), true); // non-NaN or non-Inf cases, just use built-in instructions. fmv_h_x(dst, src); @@ -2330,7 +2330,7 @@ void C2_MacroAssembler::float_to_float16(Register dst, FloatRegister src, FloatR // replace fclass with feq as performance optimization. feq_s(t0, src, src); // jump to stub processing NaN cases. - beqz(t0, stub->entry()); + beqz(t0, stub->entry(), true); // non-NaN cases, just use built-in instructions. fcvt_h_s(ftmp, src); @@ -2391,7 +2391,7 @@ void C2_MacroAssembler::float16_to_float_v(VectorRegister dst, VectorRegister sr vfwcvt_f_f_v(dst, src); // jump to stub processing NaN and Inf cases if there is any of them in the vector-wide. - bnez(t0, stub->entry()); + bnez(t0, stub->entry(), true); bind(stub->continuation()); } @@ -2445,7 +2445,7 @@ void C2_MacroAssembler::float_to_float16_v(VectorRegister dst, VectorRegister sr vfncvt_f_f_w(dst, src); // jump to stub processing NaN cases. - bnez(t0, stub->entry()); + bnez(t0, stub->entry(), true); bind(stub->continuation()); }