mirror of
https://github.com/openjdk/jdk.git
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8332265: RISC-V: Materialize pointers faster by using a temp register
Reviewed-by: fyang, luhenry, mli
This commit is contained in:
Robbin Ehn
parent
aa4c83a5bf
commit
7b52d0acfc
@ -135,7 +135,7 @@ static jlong as_long(LIR_Opr data) {
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Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
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if (addr->base()->is_illegal()) {
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assert(addr->index()->is_illegal(), "must be illegal too");
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__ movptr(tmp, addr->disp());
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__ movptr(tmp, (address)addr->disp());
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return Address(tmp, 0);
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}
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@ -42,8 +42,10 @@ jint CodeInstaller::pd_next_offset(NativeInstruction* inst, jint pc_offset, JVMC
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return pc_offset + NativeCall::instruction_size;
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} else if (inst->is_jump()) {
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return pc_offset + NativeJump::instruction_size;
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} else if (inst->is_movptr()) {
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return pc_offset + NativeMovConstReg::movptr_instruction_size;
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} else if (inst->is_movptr1()) {
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return pc_offset + NativeMovConstReg::movptr1_instruction_size;
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} else if (inst->is_movptr2()) {
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return pc_offset + NativeMovConstReg::movptr2_instruction_size;
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} else {
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JVMCI_ERROR_0("unsupported type of instruction for call site");
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}
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@ -640,7 +640,7 @@ void MacroAssembler::emit_static_call_stub() {
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// Jump to the entry point of the c2i stub.
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int32_t offset = 0;
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movptr(t0, 0, offset);
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movptr(t0, 0, offset, t1); // lui + lui + slli + add
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jr(t0, offset);
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}
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@ -1425,15 +1425,34 @@ static int patch_offset_in_pc_relative(address branch, int64_t offset) {
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return PC_RELATIVE_INSTRUCTION_NUM * NativeInstruction::instruction_size;
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}
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static int patch_addr_in_movptr(address branch, address target) {
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const int MOVPTR_INSTRUCTIONS_NUM = 6; // lui + addi + slli + addi + slli + addi/jalr/load
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static int patch_addr_in_movptr1(address branch, address target) {
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int32_t lower = ((intptr_t)target << 35) >> 35;
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int64_t upper = ((intptr_t)target - lower) >> 29;
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Assembler::patch(branch + 0, 31, 12, upper & 0xfffff); // Lui. target[48:29] + target[28] ==> branch[31:12]
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Assembler::patch(branch + 4, 31, 20, (lower >> 17) & 0xfff); // Addi. target[28:17] ==> branch[31:20]
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Assembler::patch(branch + 12, 31, 20, (lower >> 6) & 0x7ff); // Addi. target[16: 6] ==> branch[31:20]
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Assembler::patch(branch + 20, 31, 20, lower & 0x3f); // Addi/Jalr/Load. target[ 5: 0] ==> branch[31:20]
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return MOVPTR_INSTRUCTIONS_NUM * NativeInstruction::instruction_size;
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return NativeMovConstReg::movptr1_instruction_size;
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}
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static int patch_addr_in_movptr2(address instruction_address, address target) {
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uintptr_t addr = (uintptr_t)target;
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assert(addr < (1ull << 48), "48-bit overflow in address constant");
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unsigned int upper18 = (addr >> 30ull);
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int lower30 = (addr & 0x3fffffffu);
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int low12 = (lower30 << 20) >> 20;
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int mid18 = ((lower30 - low12) >> 12);
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Assembler::patch(instruction_address + (NativeInstruction::instruction_size * 0), 31, 12, (upper18 & 0xfffff)); // Lui
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Assembler::patch(instruction_address + (NativeInstruction::instruction_size * 1), 31, 12, (mid18 & 0xfffff)); // Lui
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// Slli
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// Add
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Assembler::patch(instruction_address + (NativeInstruction::instruction_size * 4), 31, 20, low12 & 0xfff); // Addi/Jalr/Load
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assert(MacroAssembler::target_addr_for_insn(instruction_address) == target, "Must be");
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return NativeMovConstReg::movptr2_instruction_size;
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}
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static int patch_imm_in_li64(address branch, address target) {
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@ -1507,7 +1526,7 @@ static long get_offset_of_pc_relative(address insn_addr) {
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return offset;
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}
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static address get_target_of_movptr(address insn_addr) {
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static address get_target_of_movptr1(address insn_addr) {
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assert_cond(insn_addr != nullptr);
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intptr_t target_address = (((int64_t)Assembler::sextract(Assembler::ld_instr(insn_addr), 31, 12)) & 0xfffff) << 29; // Lui.
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target_address += ((int64_t)Assembler::sextract(Assembler::ld_instr(insn_addr + 4), 31, 20)) << 17; // Addi.
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@ -1516,6 +1535,17 @@ static address get_target_of_movptr(address insn_addr) {
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return (address) target_address;
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}
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static address get_target_of_movptr2(address insn_addr) {
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assert_cond(insn_addr != nullptr);
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int32_t upper18 = ((Assembler::sextract(Assembler::ld_instr(insn_addr + NativeInstruction::instruction_size * 0), 31, 12)) & 0xfffff); // Lui
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int32_t mid18 = ((Assembler::sextract(Assembler::ld_instr(insn_addr + NativeInstruction::instruction_size * 1), 31, 12)) & 0xfffff); // Lui
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// 2 // Slli
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// 3 // Add
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int32_t low12 = ((Assembler::sextract(Assembler::ld_instr(insn_addr + NativeInstruction::instruction_size * 4), 31, 20))); // Addi/Jalr/Load.
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address ret = (address)(((intptr_t)upper18<<30ll) + ((intptr_t)mid18<<12ll) + low12);
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return ret;
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}
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static address get_target_of_li64(address insn_addr) {
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assert_cond(insn_addr != nullptr);
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intptr_t target_address = (((int64_t)Assembler::sextract(Assembler::ld_instr(insn_addr), 31, 12)) & 0xfffff) << 44; // Lui.
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@ -1535,30 +1565,32 @@ address MacroAssembler::get_target_of_li32(address insn_addr) {
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// Patch any kind of instruction; there may be several instructions.
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// Return the total length (in bytes) of the instructions.
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int MacroAssembler::pd_patch_instruction_size(address branch, address target) {
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assert_cond(branch != nullptr);
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int64_t offset = target - branch;
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if (NativeInstruction::is_jal_at(branch)) { // jal
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return patch_offset_in_jal(branch, offset);
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} else if (NativeInstruction::is_branch_at(branch)) { // beq/bge/bgeu/blt/bltu/bne
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return patch_offset_in_conditional_branch(branch, offset);
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} else if (NativeInstruction::is_pc_relative_at(branch)) { // auipc, addi/jalr/load
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return patch_offset_in_pc_relative(branch, offset);
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} else if (NativeInstruction::is_movptr_at(branch)) { // movptr
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return patch_addr_in_movptr(branch, target);
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} else if (NativeInstruction::is_li64_at(branch)) { // li64
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return patch_imm_in_li64(branch, target);
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} else if (NativeInstruction::is_li32_at(branch)) { // li32
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int MacroAssembler::pd_patch_instruction_size(address instruction_address, address target) {
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assert_cond(instruction_address != nullptr);
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int64_t offset = target - instruction_address;
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if (NativeInstruction::is_jal_at(instruction_address)) { // jal
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return patch_offset_in_jal(instruction_address, offset);
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} else if (NativeInstruction::is_branch_at(instruction_address)) { // beq/bge/bgeu/blt/bltu/bne
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return patch_offset_in_conditional_branch(instruction_address, offset);
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} else if (NativeInstruction::is_pc_relative_at(instruction_address)) { // auipc, addi/jalr/load
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return patch_offset_in_pc_relative(instruction_address, offset);
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} else if (NativeInstruction::is_movptr1_at(instruction_address)) { // movptr1
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return patch_addr_in_movptr1(instruction_address, target);
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} else if (NativeInstruction::is_movptr2_at(instruction_address)) { // movptr2
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return patch_addr_in_movptr2(instruction_address, target);
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} else if (NativeInstruction::is_li64_at(instruction_address)) { // li64
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return patch_imm_in_li64(instruction_address, target);
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} else if (NativeInstruction::is_li32_at(instruction_address)) { // li32
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int64_t imm = (intptr_t)target;
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return patch_imm_in_li32(branch, (int32_t)imm);
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} else if (NativeInstruction::is_li16u_at(branch)) {
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return patch_imm_in_li32(instruction_address, (int32_t)imm);
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} else if (NativeInstruction::is_li16u_at(instruction_address)) {
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int64_t imm = (intptr_t)target;
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return patch_imm_in_li16u(branch, (uint16_t)imm);
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return patch_imm_in_li16u(instruction_address, (uint16_t)imm);
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} else {
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#ifdef ASSERT
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tty->print_cr("pd_patch_instruction_size: instruction 0x%x at " INTPTR_FORMAT " could not be patched!\n",
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Assembler::ld_instr(branch), p2i(branch));
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Disassembler::decode(branch - 16, branch + 16);
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Assembler::ld_instr(instruction_address), p2i(instruction_address));
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Disassembler::decode(instruction_address - 16, instruction_address + 16);
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#endif
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ShouldNotReachHere();
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return -1;
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@ -1574,8 +1606,10 @@ address MacroAssembler::target_addr_for_insn(address insn_addr) {
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offset = get_offset_of_conditional_branch(insn_addr);
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} else if (NativeInstruction::is_pc_relative_at(insn_addr)) { // auipc, addi/jalr/load
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offset = get_offset_of_pc_relative(insn_addr);
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} else if (NativeInstruction::is_movptr_at(insn_addr)) { // movptr
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return get_target_of_movptr(insn_addr);
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} else if (NativeInstruction::is_movptr1_at(insn_addr)) { // movptr1
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return get_target_of_movptr1(insn_addr);
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} else if (NativeInstruction::is_movptr2_at(insn_addr)) { // movptr2
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return get_target_of_movptr2(insn_addr);
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} else if (NativeInstruction::is_li64_at(insn_addr)) { // li64
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return get_target_of_li64(insn_addr);
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} else if (NativeInstruction::is_li32_at(insn_addr)) { // li32
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@ -1594,9 +1628,12 @@ int MacroAssembler::patch_oop(address insn_addr, address o) {
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// Move narrow OOP
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uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
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return patch_imm_in_li32(insn_addr, (int32_t)n);
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} else if (NativeInstruction::is_movptr_at(insn_addr)) {
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} else if (NativeInstruction::is_movptr1_at(insn_addr)) {
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// Move wide OOP
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return patch_addr_in_movptr(insn_addr, o);
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return patch_addr_in_movptr1(insn_addr, o);
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} else if (NativeInstruction::is_movptr2_at(insn_addr)) {
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// Move wide OOP
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return patch_addr_in_movptr2(insn_addr, o);
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}
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ShouldNotReachHere();
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return -1;
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@ -1617,16 +1654,31 @@ void MacroAssembler::reinit_heapbase() {
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}
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}
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void MacroAssembler::movptr(Register Rd, address addr, int32_t &offset) {
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int64_t imm64 = (int64_t)addr;
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void MacroAssembler::movptr(Register Rd, address addr, Register temp) {
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int offset = 0;
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movptr(Rd, addr, offset, temp);
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addi(Rd, Rd, offset);
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}
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void MacroAssembler::movptr(Register Rd, address addr, int32_t &offset, Register temp) {
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uint64_t uimm64 = (uint64_t)addr;
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#ifndef PRODUCT
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{
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char buffer[64];
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snprintf(buffer, sizeof(buffer), "0x%" PRIx64, imm64);
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snprintf(buffer, sizeof(buffer), "0x%" PRIx64, uimm64);
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block_comment(buffer);
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}
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#endif
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assert((uintptr_t)imm64 < (1ull << 48), "48-bit overflow in address constant");
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assert(uimm64 < (1ull << 48), "48-bit overflow in address constant");
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if (temp == noreg) {
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movptr1(Rd, uimm64, offset);
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} else {
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movptr2(Rd, uimm64, offset, temp);
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}
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}
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void MacroAssembler::movptr1(Register Rd, uint64_t imm64, int32_t &offset) {
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// Load upper 31 bits
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int64_t imm = imm64 >> 17;
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int64_t upper = imm, lower = imm;
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@ -1645,6 +1697,23 @@ void MacroAssembler::movptr(Register Rd, address addr, int32_t &offset) {
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offset = imm64 & 0x3f;
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}
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void MacroAssembler::movptr2(Register Rd, uint64_t addr, int32_t &offset, Register tmp) {
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assert_different_registers(Rd, tmp, noreg);
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uint32_t upper18 = (addr >> 30ull);
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int32_t lower30 = (addr & 0x3fffffffu);
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int32_t low12 = (lower30 << 20) >> 20;
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int32_t mid18 = ((lower30 - low12) >> 12);
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lui(tmp, upper18 << 12);
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lui(Rd, mid18 << 12);
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slli(tmp, tmp, 18);
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add(Rd, Rd, tmp);
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offset = low12;
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}
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void MacroAssembler::add(Register Rd, Register Rn, int64_t increment, Register temp) {
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if (is_simm12(increment)) {
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addi(Rd, Rn, increment);
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@ -2120,6 +2189,7 @@ void MacroAssembler::movoop(Register dst, jobject obj) {
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// Move a metadata address into a register.
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void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
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assert((uintptr_t)obj < (1ull << 48), "48-bit overflow in metadata");
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int oop_index;
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if (obj == nullptr) {
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oop_index = oop_recorder()->allocate_metadata_index(obj);
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@ -3554,7 +3624,7 @@ address MacroAssembler::trampoline_call(Address entry) {
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address MacroAssembler::ic_call(address entry, jint method_index) {
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RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
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IncompressibleRegion ir(this); // relocations
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movptr(t1, (address)Universe::non_oop_word());
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movptr(t1, (address)Universe::non_oop_word(), t0);
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assert_cond(entry != nullptr);
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return trampoline_call(Address(entry, rh));
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}
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@ -3661,8 +3731,8 @@ int MacroAssembler::max_trampoline_stub_size() {
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}
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int MacroAssembler::static_call_stub_size() {
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// (lui, addi, slli, addi, slli, addi) + (lui, addi, slli, addi, slli) + jalr
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return 12 * NativeInstruction::instruction_size;
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// (lui, addi, slli, addi, slli, addi) + (lui + lui + slli + add) + jalr
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return 11 * NativeInstruction::instruction_size;
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}
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Address MacroAssembler::add_memory_helper(const Address dst, Register tmp) {
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@ -804,17 +804,16 @@ public:
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}
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}
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void movptr(Register Rd, address addr, int32_t &offset);
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void movptr(Register Rd, address addr) {
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int offset = 0;
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movptr(Rd, addr, offset);
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addi(Rd, Rd, offset);
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}
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inline void movptr(Register Rd, uintptr_t imm64) {
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movptr(Rd, (address)imm64);
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}
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// Generates a load of a 48-bit constant which can be
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// patched to any 48-bit constant, i.e. address.
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// If common case supply additional temp register
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// to shorten the instruction sequence.
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void movptr(Register Rd, address addr, Register tmp = noreg);
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void movptr(Register Rd, address addr, int32_t &offset, Register tmp = noreg);
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private:
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void movptr1(Register Rd, uintptr_t addr, int32_t &offset);
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void movptr2(Register Rd, uintptr_t addr, int32_t &offset, Register tmp);
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public:
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// arith
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void add (Register Rd, Register Rn, int64_t increment, Register temp = t0);
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@ -84,7 +84,7 @@ bool NativeInstruction::is_load_pc_relative_at(address instr) {
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check_load_pc_relative_data_dependency(instr);
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}
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bool NativeInstruction::is_movptr_at(address instr) {
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bool NativeInstruction::is_movptr1_at(address instr) {
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return is_lui_at(instr) && // Lui
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is_addi_at(instr + instruction_size) && // Addi
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is_slli_shift_at(instr + instruction_size * 2, 11) && // Slli Rd, Rs, 11
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@ -93,7 +93,18 @@ bool NativeInstruction::is_movptr_at(address instr) {
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(is_addi_at(instr + instruction_size * 5) ||
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is_jalr_at(instr + instruction_size * 5) ||
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is_load_at(instr + instruction_size * 5)) && // Addi/Jalr/Load
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check_movptr_data_dependency(instr);
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check_movptr1_data_dependency(instr);
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}
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bool NativeInstruction::is_movptr2_at(address instr) {
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return is_lui_at(instr) && // lui
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is_lui_at(instr + instruction_size) && // lui
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is_slli_shift_at(instr + instruction_size * 2, 18) && // slli Rd, Rs, 18
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is_add_at(instr + instruction_size * 3) &&
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(is_addi_at(instr + instruction_size * 4) ||
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is_jalr_at(instr + instruction_size * 4) ||
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is_load_at(instr + instruction_size * 4)) && // Addi/Jalr/Load
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check_movptr2_data_dependency(instr);
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}
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bool NativeInstruction::is_li16u_at(address instr) {
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@ -201,10 +212,11 @@ void NativeCall::insert(address code_pos, address entry) { Unimplemented(); }
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//-------------------------------------------------------------------
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void NativeMovConstReg::verify() {
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if (!(nativeInstruction_at(instruction_address())->is_movptr() ||
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is_auipc_at(instruction_address()))) {
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fatal("should be MOVPTR or AUIPC");
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NativeInstruction* ni = nativeInstruction_at(instruction_address());
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if (ni->is_movptr() || ni->is_auipc()) {
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return;
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}
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fatal("should be MOVPTR or AUIPC");
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}
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intptr_t NativeMovConstReg::data() const {
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@ -223,7 +235,7 @@ void NativeMovConstReg::set_data(intptr_t x) {
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} else {
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// Store x into the instruction stream.
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MacroAssembler::pd_patch_instruction_size(instruction_address(), (address)x);
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ICache::invalidate_range(instruction_address(), movptr_instruction_size);
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ICache::invalidate_range(instruction_address(), movptr1_instruction_size /* > movptr2_instruction_size */ );
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}
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// Find and replace the oop/metadata corresponding to this
|
||||
@ -393,13 +405,15 @@ void NativeJump::patch_verified_entry(address entry, address verified_entry, add
|
||||
ICache::invalidate_range(verified_entry, instruction_size);
|
||||
}
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
|
||||
void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
|
||||
CodeBuffer cb(code_pos, instruction_size);
|
||||
MacroAssembler a(&cb);
|
||||
Assembler::IncompressibleRegion ir(&a); // Fixed length: see NativeGeneralJump::get_instruction_size()
|
||||
|
||||
int32_t offset = 0;
|
||||
a.movptr(t0, entry, offset); // lui, addi, slli, addi, slli
|
||||
a.movptr(t0, entry, offset, t1); // lui, lui, slli, add
|
||||
a.jr(t0, offset); // jalr
|
||||
|
||||
ICache::invalidate_range(code_pos, instruction_size);
|
||||
@ -410,6 +424,8 @@ void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer)
|
||||
ShouldNotCallThis();
|
||||
}
|
||||
|
||||
//-------------------------------------------------------------------
|
||||
|
||||
address NativeCallTrampolineStub::destination(nmethod *nm) const {
|
||||
return ptr_at(data_offset);
|
||||
}
|
||||
|
||||
@ -64,7 +64,11 @@ class NativeInstruction {
|
||||
}
|
||||
|
||||
bool is_jal() const { return is_jal_at(addr_at(0)); }
|
||||
bool is_movptr() const { return is_movptr_at(addr_at(0)); }
|
||||
bool is_movptr() const { return is_movptr1_at(addr_at(0)) ||
|
||||
is_movptr2_at(addr_at(0)); }
|
||||
bool is_movptr1() const { return is_movptr1_at(addr_at(0)); }
|
||||
bool is_movptr2() const { return is_movptr2_at(addr_at(0)); }
|
||||
bool is_auipc() const { return is_auipc_at(addr_at(0)); }
|
||||
bool is_call() const { return is_call_at(addr_at(0)); }
|
||||
bool is_jump() const { return is_jump_at(addr_at(0)); }
|
||||
|
||||
@ -76,9 +80,10 @@ class NativeInstruction {
|
||||
static bool is_float_load_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0000111; }
|
||||
static bool is_auipc_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010111; }
|
||||
static bool is_jump_at(address instr) { assert_cond(instr != nullptr); return is_branch_at(instr) || is_jal_at(instr) || is_jalr_at(instr); }
|
||||
static bool is_add_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110011 && extract_funct3(instr) == 0b000; }
|
||||
static bool is_addi_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010011 && extract_funct3(instr) == 0b000; }
|
||||
static bool is_addiw_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0011011 && extract_funct3(instr) == 0b000; }
|
||||
static bool is_addiw_to_zr_at(address instr) { assert_cond(instr != nullptr); return is_addiw_at(instr) && extract_rd(instr) == zr; }
|
||||
static bool is_addiw_to_zr_at(address instr){ assert_cond(instr != nullptr); return is_addiw_at(instr) && extract_rd(instr) == zr; }
|
||||
static bool is_lui_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110111; }
|
||||
static bool is_lui_to_zr_at(address instr) { assert_cond(instr != nullptr); return is_lui_at(instr) && extract_rd(instr) == zr; }
|
||||
|
||||
@ -109,7 +114,7 @@ class NativeInstruction {
|
||||
// addi
|
||||
// slli
|
||||
// addi/jalr/load
|
||||
static bool check_movptr_data_dependency(address instr) {
|
||||
static bool check_movptr1_data_dependency(address instr) {
|
||||
address lui = instr;
|
||||
address addi1 = lui + instruction_size;
|
||||
address slli1 = addi1 + instruction_size;
|
||||
@ -127,6 +132,26 @@ class NativeInstruction {
|
||||
extract_rs1(last_instr) == extract_rd(slli2);
|
||||
}
|
||||
|
||||
// the instruction sequence of movptr2 is as below:
|
||||
// lui
|
||||
// lui
|
||||
// slli
|
||||
// add
|
||||
// addi/jalr/load
|
||||
static bool check_movptr2_data_dependency(address instr) {
|
||||
address lui1 = instr;
|
||||
address lui2 = lui1 + instruction_size;
|
||||
address slli = lui2 + instruction_size;
|
||||
address add = slli + instruction_size;
|
||||
address last_instr = add + instruction_size;
|
||||
return extract_rd(add) == extract_rd(lui2) &&
|
||||
extract_rs1(add) == extract_rd(lui2) &&
|
||||
extract_rs2(add) == extract_rd(slli) &&
|
||||
extract_rs1(slli) == extract_rd(lui1) &&
|
||||
extract_rd(slli) == extract_rd(lui1) &&
|
||||
extract_rs1(last_instr) == extract_rd(add);
|
||||
}
|
||||
|
||||
// the instruction sequence of li64 is as below:
|
||||
// lui
|
||||
// addi
|
||||
@ -204,7 +229,8 @@ class NativeInstruction {
|
||||
extract_rs1(load) == extract_rd(load);
|
||||
}
|
||||
|
||||
static bool is_movptr_at(address instr);
|
||||
static bool is_movptr1_at(address instr);
|
||||
static bool is_movptr2_at(address instr);
|
||||
static bool is_li16u_at(address instr);
|
||||
static bool is_li32_at(address instr);
|
||||
static bool is_li64_at(address instr);
|
||||
@ -351,26 +377,33 @@ inline NativeCall* nativeCall_before(address return_address) {
|
||||
class NativeMovConstReg: public NativeInstruction {
|
||||
public:
|
||||
enum RISCV_specific_constants {
|
||||
movptr_instruction_size = 6 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli, addi. See movptr().
|
||||
load_pc_relative_instruction_size = 2 * NativeInstruction::instruction_size, // auipc, ld
|
||||
instruction_offset = 0,
|
||||
displacement_offset = 0
|
||||
movptr1_instruction_size = 6 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli, addi. See movptr1().
|
||||
movptr2_instruction_size = 5 * NativeInstruction::instruction_size, // lui, lui, slli, add, addi. See movptr2().
|
||||
load_pc_relative_instruction_size = 2 * NativeInstruction::instruction_size // auipc, ld
|
||||
};
|
||||
|
||||
address instruction_address() const { return addr_at(instruction_offset); }
|
||||
address instruction_address() const { return addr_at(0); }
|
||||
address next_instruction_address() const {
|
||||
// if the instruction at 5 * instruction_size is addi,
|
||||
// it means a lui + addi + slli + addi + slli + addi instruction sequence,
|
||||
// and the next instruction address should be addr_at(6 * instruction_size).
|
||||
// However, when the instruction at 5 * instruction_size isn't addi,
|
||||
// the next instruction address should be addr_at(5 * instruction_size)
|
||||
if (nativeInstruction_at(instruction_address())->is_movptr()) {
|
||||
if (is_addi_at(addr_at(movptr_instruction_size - NativeInstruction::instruction_size))) {
|
||||
if (is_movptr1_at(instruction_address())) {
|
||||
if (is_addi_at(addr_at(movptr1_instruction_size - NativeInstruction::instruction_size))) {
|
||||
// Assume: lui, addi, slli, addi, slli, addi
|
||||
return addr_at(movptr_instruction_size);
|
||||
return addr_at(movptr1_instruction_size);
|
||||
} else {
|
||||
// Assume: lui, addi, slli, addi, slli
|
||||
return addr_at(movptr_instruction_size - NativeInstruction::instruction_size);
|
||||
return addr_at(movptr1_instruction_size - NativeInstruction::instruction_size);
|
||||
}
|
||||
} else if (is_movptr2_at(instruction_address())) {
|
||||
if (is_addi_at(addr_at(movptr2_instruction_size - NativeInstruction::instruction_size))) {
|
||||
// Assume: lui, lui, slli, add, addi
|
||||
return addr_at(movptr2_instruction_size);
|
||||
} else {
|
||||
// Assume: lui, lui, slli, add
|
||||
return addr_at(movptr2_instruction_size - NativeInstruction::instruction_size);
|
||||
}
|
||||
} else if (is_load_pc_relative_at(instruction_address())) {
|
||||
// Assume: auipc, ld
|
||||
@ -383,12 +416,6 @@ class NativeMovConstReg: public NativeInstruction {
|
||||
intptr_t data() const;
|
||||
void set_data(intptr_t x);
|
||||
|
||||
void flush() {
|
||||
if (!maybe_cpool_ref(instruction_address())) {
|
||||
ICache::invalidate_range(instruction_address(), movptr_instruction_size);
|
||||
}
|
||||
}
|
||||
|
||||
void verify();
|
||||
void print();
|
||||
|
||||
@ -399,14 +426,14 @@ class NativeMovConstReg: public NativeInstruction {
|
||||
|
||||
inline NativeMovConstReg* nativeMovConstReg_at(address addr) {
|
||||
assert_cond(addr != nullptr);
|
||||
NativeMovConstReg* test = (NativeMovConstReg*)(addr - NativeMovConstReg::instruction_offset);
|
||||
NativeMovConstReg* test = (NativeMovConstReg*)(addr);
|
||||
DEBUG_ONLY(test->verify());
|
||||
return test;
|
||||
}
|
||||
|
||||
inline NativeMovConstReg* nativeMovConstReg_before(address addr) {
|
||||
assert_cond(addr != nullptr);
|
||||
NativeMovConstReg* test = (NativeMovConstReg*)(addr - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
|
||||
NativeMovConstReg* test = (NativeMovConstReg*)(addr - NativeMovConstReg::instruction_size);
|
||||
DEBUG_ONLY(test->verify());
|
||||
return test;
|
||||
}
|
||||
@ -484,10 +511,7 @@ inline NativeJump* nativeJump_at(address addr) {
|
||||
class NativeGeneralJump: public NativeJump {
|
||||
public:
|
||||
enum RISCV_specific_constants {
|
||||
instruction_size = 6 * NativeInstruction::instruction_size, // lui, addi, slli, addi, slli, jalr
|
||||
instruction_offset = 0,
|
||||
data_offset = 0,
|
||||
next_instruction_offset = 6 * NativeInstruction::instruction_size // lui, addi, slli, addi, slli, jalr
|
||||
instruction_size = 5 * NativeInstruction::instruction_size, // lui, lui, slli, add, jalr
|
||||
};
|
||||
|
||||
address jump_destination() const;
|
||||
|
||||
@ -1244,7 +1244,7 @@ int MachCallStaticJavaNode::ret_addr_offset()
|
||||
|
||||
int MachCallDynamicJavaNode::ret_addr_offset()
|
||||
{
|
||||
return 7 * NativeInstruction::instruction_size; // movptr, jal
|
||||
return NativeMovConstReg::movptr2_instruction_size + NativeInstruction::instruction_size; // movptr2, jal
|
||||
}
|
||||
|
||||
int MachCallRuntimeNode::ret_addr_offset() {
|
||||
@ -1285,12 +1285,11 @@ int CallStaticJavaDirectNode::compute_padding(int current_offset) const
|
||||
// ensure that it does not span a cache line so that it can be patched.
|
||||
int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
|
||||
{
|
||||
// skip the movptr in MacroAssembler::ic_call():
|
||||
// lui + addi + slli + addi + slli + addi
|
||||
// Though movptr() has already 4-byte aligned with or without RVC,
|
||||
// skip the movptr2 in MacroAssembler::ic_call():
|
||||
// lui, lui, slli, add, addi
|
||||
// Though movptr2() has already 4-byte aligned with or without RVC,
|
||||
// We need to prevent from further changes by explicitly calculating the size.
|
||||
const int movptr_size = 6 * NativeInstruction::instruction_size;
|
||||
current_offset += movptr_size;
|
||||
current_offset += NativeMovConstReg::movptr2_instruction_size;
|
||||
// to make sure the address of jal 4-byte aligned.
|
||||
return align_up(current_offset, alignment_required()) - current_offset;
|
||||
}
|
||||
@ -10014,7 +10013,7 @@ instruct CallDynamicJavaDirect(method meth, rFlagsReg cr)
|
||||
|
||||
effect(USE meth, KILL cr);
|
||||
|
||||
ins_cost(BRANCH_COST + ALU_COST * 6);
|
||||
ins_cost(BRANCH_COST + ALU_COST * 5);
|
||||
|
||||
format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
|
||||
|
||||
|
||||
@ -223,7 +223,7 @@ address UpcallLinker::make_upcall_stub(jobject receiver, Method* entry,
|
||||
|
||||
__ block_comment("{ on_entry");
|
||||
__ la(c_rarg0, Address(sp, frame_data_offset));
|
||||
__ movptr(c_rarg1, (intptr_t) receiver);
|
||||
__ movptr(c_rarg1, (address) receiver);
|
||||
__ rt_call(CAST_FROM_FN_PTR(address, UpcallLinker::on_entry));
|
||||
__ mv(xthread, x10);
|
||||
__ reinit_heapbase();
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user