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8272310: AArch64: Add missing changes for shared vector helper methods in m4 files

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Reviewed-by: jiefu
This commit is contained in:
Xiaohong Gong 2021-08-12 11:07:04 +00:00 committed by Jie Fu
parent b29fbad940
commit 7e14c3cc11
2 changed files with 7 additions and 7 deletions
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6
src/hotspot/cpu/aarch64/aarch64_neon_ad.m4
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@ -872,7 +872,7 @@ instruct vcmpD(vecD dst, vecD src1, vecD src2, immI cond)
format %{ "vcmpD $dst, $src1, $src2\t# vector compare " %}
ins_cost(INSN_COST);
ins_encode %{
BasicType bt = vector_element_basic_type(this);
BasicType bt = Matcher::vector_element_basic_type(this);
assert(type2aelembytes(bt) != 8, "not supported");
__ neon_compare(as_FloatRegister($dst$$reg), bt, as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg), (int)$cond$$constant, /*isQ*/ false);
@ -887,7 +887,7 @@ instruct vcmpX(vecX dst, vecX src1, vecX src2, immI cond)
format %{ "vcmpX $dst, $src1, $src2\t# vector compare " %}
ins_cost(INSN_COST);
ins_encode %{
BasicType bt = vector_element_basic_type(this);
BasicType bt = Matcher::vector_element_basic_type(this);
__ neon_compare(as_FloatRegister($dst$$reg), bt, as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg), (int)$cond$$constant, /*isQ*/ true);
%}
@ -2292,7 +2292,7 @@ ifelse($1, `_LT8B', `
__ clz($dst$$Register, $dst$$Register);
__ lsrw($dst$$Register, $dst$$Register, 3);dnl
ifelse(`$1', `_LT8B', `
__ movw(rscratch1, vector_length(this, $src));
__ movw(rscratch1, Matcher::vector_length(this, $src));
__ cmpw($dst$$Register, rscratch1);
__ cselw($dst$$Register, rscratch1, $dst$$Register, Assembler::GE);')
%}

8
src/hotspot/cpu/aarch64/aarch64_sve_ad.m4
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@ -214,7 +214,7 @@ instruct loadV(vReg dst, vmemA mem) %{
ins_encode %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
vector_element_basic_type(this), $mem->opcode(),
Matcher::vector_element_basic_type(this), $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
@ -228,7 +228,7 @@ instruct storeV(vReg src, vmemA mem) %{
ins_encode %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), true, src_reg, ptrue,
vector_element_basic_type(this, $src), $mem->opcode(),
Matcher::vector_element_basic_type(this, $src), $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
@ -386,7 +386,7 @@ instruct vmin(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this);
BasicType bt = Matcher::vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
if (is_floating_point_type(bt)) {
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
@ -406,7 +406,7 @@ instruct vmax(vReg dst_src1, vReg src2) %{
ins_cost(SVE_COST);
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this);
BasicType bt = Matcher::vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
if (is_floating_point_type(bt)) {
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,