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8185969: PPC64: Improve VSR support to use up to 64 registers
Reviewed-by: mdoerr, goetz
This commit is contained in:
Gustavo Serra Scalet
Martin Doerr
parent
f79aa532aa
commit
85fedbbb12
@ -510,8 +510,13 @@ class Assembler : public AbstractAssembler {
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LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
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STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
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MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
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MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1),
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MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
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MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
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MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1),
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XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3),
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XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3),
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XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3),
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// Vector Permute and Formatting
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VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
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@ -561,6 +566,7 @@ class Assembler : public AbstractAssembler {
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VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ),
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VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ),
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VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ),
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VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ),
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VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ),
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VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ),
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VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ),
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@ -1099,16 +1105,19 @@ class Assembler : public AbstractAssembler {
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static int vrs( VectorRegister r) { return vrs(r->encoding());}
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static int vrt( VectorRegister r) { return vrt(r->encoding());}
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// Only used on SHA sigma instructions (VX-form)
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static int vst( int x) { return opp_u_field(x, 16, 16); }
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static int vsix( int x) { return opp_u_field(x, 20, 17); }
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// Support Vector-Scalar (VSX) instructions.
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static int vsra( int x) { return opp_u_field(x, 15, 11); }
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static int vsrb( int x) { return opp_u_field(x, 20, 16); }
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static int vsrc( int x) { return opp_u_field(x, 25, 21); }
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static int vsrs( int x) { return opp_u_field(x, 10, 6); }
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static int vsrt( int x) { return opp_u_field(x, 10, 6); }
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static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
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static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
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static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
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static int vsrt( int x) { return vsrs(x); }
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static int vsdm( int x) { return opp_u_field(x, 23, 22); }
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static int vsra( VectorSRegister r) { return vsra(r->encoding());}
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static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}
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static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}
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static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}
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static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}
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@ -2038,6 +2047,7 @@ class Assembler : public AbstractAssembler {
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inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b);
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@ -2113,6 +2123,7 @@ class Assembler : public AbstractAssembler {
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inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vor( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vmr( VectorRegister d, VectorRegister a);
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inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b);
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inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b);
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@ -2136,8 +2147,19 @@ class Assembler : public AbstractAssembler {
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inline void lxvd2x( VectorSRegister d, Register a, Register b);
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inline void stxvd2x( VectorSRegister d, Register a);
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inline void stxvd2x( VectorSRegister d, Register a, Register b);
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inline void mtvrwz( VectorRegister d, Register a);
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inline void mfvrwz( Register a, VectorRegister d);
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inline void mtvrd( VectorRegister d, Register a);
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inline void mfvrd( Register a, VectorRegister d);
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inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
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inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
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inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b);
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// VSX Extended Mnemonics
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inline void xxspltd( VectorSRegister d, VectorSRegister a, int x);
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inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b);
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inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b);
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inline void xxswapd( VectorSRegister d, VectorSRegister a);
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// Vector-Scalar (VSX) instructions.
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inline void mtfprd( FloatRegister d, Register a);
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@ -758,12 +758,23 @@ inline void Assembler::lvsl( VectorRegister d, Register s1, Register s2) { emit
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inline void Assembler::lvsr( VectorRegister d, Register s1, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | ra0mem(s1) | rb(s2)); }
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// Vector-Scalar (VSX) instructions.
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inline void Assembler::lxvd2x (VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
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inline void Assembler::lxvd2x (VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
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inline void Assembler::stxvd2x(VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
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inline void Assembler::stxvd2x(VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
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inline void Assembler::mtvrd( VectorRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vrt(d) | ra(a) | 1u); } // 1u: d is treated as Vector (VMX/Altivec).
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inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vrt(d) | ra(a) | 1u); } // 1u: d is treated as Vector (VMX/Altivec).
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inline void Assembler::lxvd2x( VectorSRegister d, Register s1) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
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inline void Assembler::lxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( LXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
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inline void Assembler::stxvd2x( VectorSRegister d, Register s1) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra(0) | rb(s1)); }
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inline void Assembler::stxvd2x( VectorSRegister d, Register s1, Register s2) { emit_int32( STXVD2X_OPCODE | vsrt(d) | ra0mem(s1) | rb(s2)); }
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inline void Assembler::mtvrd( VectorRegister d, Register a) { emit_int32( MTVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
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inline void Assembler::mfvrd( Register a, VectorRegister d) { emit_int32( MFVSRD_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
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inline void Assembler::mtvrwz( VectorRegister d, Register a) { emit_int32( MTVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
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inline void Assembler::mfvrwz( Register a, VectorRegister d) { emit_int32( MFVSRWZ_OPCODE | vsrt(d->to_vsr()) | ra(a)); }
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inline void Assembler::xxpermdi(VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm) { emit_int32( XXPERMDI_OPCODE | vsrt(d) | vsra(a) | vsrb(b) | vsdm(dm)); }
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inline void Assembler::xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
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inline void Assembler::xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b) { emit_int32( XXMRGHW_OPCODE | vsrt(d) | vsra(a) | vsrb(b)); }
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// VSX Extended Mnemonics
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inline void Assembler::xxspltd( VectorSRegister d, VectorSRegister a, int x) { xxpermdi(d, a, a, x ? 3 : 0); }
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inline void Assembler::xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 0); }
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inline void Assembler::xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b) { xxpermdi(d, a, b, 3); }
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inline void Assembler::xxswapd( VectorSRegister d, VectorSRegister a) { xxpermdi(d, a, a, 2); }
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// Vector-Scalar (VSX) instructions.
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inline void Assembler::mtfprd( FloatRegister d, Register a) { emit_int32( MTVSRD_OPCODE | frt(d) | ra(a)); }
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@ -811,6 +822,7 @@ inline void Assembler::vaddsws( VectorRegister d, VectorRegister a, VectorRegist
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inline void Assembler::vaddubm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vadduwm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vadduhm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vaddudm( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUDM_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vaddubs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUBS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vadduws( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUWS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vadduhs( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VADDUHS_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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@ -887,6 +899,7 @@ inline void Assembler::vand( VectorRegister d, VectorRegister a, VectorRegist
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inline void Assembler::vandc( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VANDC_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vnor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VNOR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VOR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vmr( VectorRegister d, VectorRegister a) { emit_int32( VOR_OPCODE | vrt(d) | vra(a) | vrb(a)); }
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inline void Assembler::vxor( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VXOR_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vrld( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLD_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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inline void Assembler::vrlb( VectorRegister d, VectorRegister a, VectorRegister b) { emit_int32( VRLB_OPCODE | vrt(d) | vra(a) | vrb(b)); }
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2013 SAP SE. All rights reserved.
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* Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2017 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -81,8 +81,17 @@ const char* VectorSRegisterImpl::name() const {
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"VSR0", "VSR1", "VSR2", "VSR3", "VSR4", "VSR5", "VSR6", "VSR7",
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"VSR8", "VSR9", "VSR10", "VSR11", "VSR12", "VSR13", "VSR14", "VSR15",
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"VSR16", "VSR17", "VSR18", "VSR19", "VSR20", "VSR21", "VSR22", "VSR23",
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"VSR24", "VSR25", "VSR26", "VSR27", "VSR28", "VSR29", "VSR30", "VSR31"
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"VSR24", "VSR25", "VSR26", "VSR27", "VSR28", "VSR29", "VSR30", "VSR31",
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"VSR32", "VSR33", "VSR34", "VSR35", "VSR36", "VSR37", "VSR38", "VSR39",
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"VSR40", "VSR41", "VSR42", "VSR43", "VSR44", "VSR45", "VSR46", "VSR47",
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"VSR48", "VSR49", "VSR50", "VSR51", "VSR52", "VSR53", "VSR54", "VSR55",
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"VSR56", "VSR57", "VSR58", "VSR59", "VSR60", "VSR61", "VSR62", "VSR63"
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};
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return is_valid() ? names[encoding()] : "vsnoreg";
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}
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// Method to convert a VectorRegister to a Vector-Scalar Register (VectorSRegister)
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VectorSRegister VectorRegisterImpl::to_vsr() const {
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if (this == vnoreg) { return vsnoregi; }
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return as_VectorSRegister(encoding() + 32);
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}
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2016 SAP SE. All rights reserved.
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* Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2012, 2017 SAP SE. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -398,6 +398,11 @@ inline VectorRegister as_VectorRegister(int encoding) {
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return (VectorRegister)(intptr_t)encoding;
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}
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// Forward declaration
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// Use VectorSRegister as a shortcut.
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class VectorSRegisterImpl;
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typedef VectorSRegisterImpl* VectorSRegister;
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// The implementation of vector registers for the Power architecture
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class VectorRegisterImpl: public AbstractRegisterImpl {
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public:
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@ -415,6 +420,9 @@ class VectorRegisterImpl: public AbstractRegisterImpl {
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bool is_valid() const { return 0 <= value() && value() < number_of_registers; }
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const char* name() const;
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// convert to VSR
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VectorSRegister to_vsr() const;
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};
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// The Vector registers of the Power architecture
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@ -491,10 +499,6 @@ CONSTANT_REGISTER_DECLARATION(VectorRegister, VR31, (31));
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#endif // DONT_USE_REGISTER_DEFINES
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// Use VectorSRegister as a shortcut.
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class VectorSRegisterImpl;
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typedef VectorSRegisterImpl* VectorSRegister;
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inline VectorSRegister as_VectorSRegister(int encoding) {
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return (VectorSRegister)(intptr_t)encoding;
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}
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@ -503,7 +507,7 @@ inline VectorSRegister as_VectorSRegister(int encoding) {
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class VectorSRegisterImpl: public AbstractRegisterImpl {
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public:
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enum {
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number_of_registers = 32
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number_of_registers = 64
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};
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// construction
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@ -554,6 +558,38 @@ CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR28, (28));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR29, (29));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR30, (30));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR31, (31));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR32, (32));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR33, (33));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR34, (34));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR35, (35));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR36, (36));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR37, (37));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR38, (38));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR39, (39));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR40, (40));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR41, (41));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR42, (42));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR43, (43));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR44, (44));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR45, (45));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR46, (46));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR47, (47));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR48, (48));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR49, (49));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR50, (50));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR51, (51));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR52, (52));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR53, (53));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR54, (54));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR55, (55));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR56, (56));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR57, (57));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR58, (58));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR59, (59));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR60, (60));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR61, (61));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR62, (62));
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CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR63, (63));
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#ifndef DONT_USE_REGISTER_DEFINES
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#define vsnoregi ((VectorSRegister)(vsnoreg_VectorSRegisterEnumValue))
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@ -589,6 +625,38 @@ CONSTANT_REGISTER_DECLARATION(VectorSRegister, VSR31, (31));
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#define VSR29 ((VectorSRegister)( VSR29_VectorSRegisterEnumValue))
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#define VSR30 ((VectorSRegister)( VSR30_VectorSRegisterEnumValue))
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#define VSR31 ((VectorSRegister)( VSR31_VectorSRegisterEnumValue))
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#define VSR32 ((VectorSRegister)( VSR32_VectorSRegisterEnumValue))
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#define VSR33 ((VectorSRegister)( VSR33_VectorSRegisterEnumValue))
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#define VSR34 ((VectorSRegister)( VSR34_VectorSRegisterEnumValue))
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#define VSR35 ((VectorSRegister)( VSR35_VectorSRegisterEnumValue))
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#define VSR36 ((VectorSRegister)( VSR36_VectorSRegisterEnumValue))
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#define VSR37 ((VectorSRegister)( VSR37_VectorSRegisterEnumValue))
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#define VSR38 ((VectorSRegister)( VSR38_VectorSRegisterEnumValue))
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#define VSR39 ((VectorSRegister)( VSR39_VectorSRegisterEnumValue))
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#define VSR40 ((VectorSRegister)( VSR40_VectorSRegisterEnumValue))
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#define VSR41 ((VectorSRegister)( VSR41_VectorSRegisterEnumValue))
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#define VSR42 ((VectorSRegister)( VSR42_VectorSRegisterEnumValue))
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#define VSR43 ((VectorSRegister)( VSR43_VectorSRegisterEnumValue))
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#define VSR44 ((VectorSRegister)( VSR44_VectorSRegisterEnumValue))
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||||
#define VSR45 ((VectorSRegister)( VSR45_VectorSRegisterEnumValue))
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||||
#define VSR46 ((VectorSRegister)( VSR46_VectorSRegisterEnumValue))
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||||
#define VSR47 ((VectorSRegister)( VSR47_VectorSRegisterEnumValue))
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||||
#define VSR48 ((VectorSRegister)( VSR48_VectorSRegisterEnumValue))
|
||||
#define VSR49 ((VectorSRegister)( VSR49_VectorSRegisterEnumValue))
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||||
#define VSR50 ((VectorSRegister)( VSR50_VectorSRegisterEnumValue))
|
||||
#define VSR51 ((VectorSRegister)( VSR51_VectorSRegisterEnumValue))
|
||||
#define VSR52 ((VectorSRegister)( VSR52_VectorSRegisterEnumValue))
|
||||
#define VSR53 ((VectorSRegister)( VSR53_VectorSRegisterEnumValue))
|
||||
#define VSR54 ((VectorSRegister)( VSR54_VectorSRegisterEnumValue))
|
||||
#define VSR55 ((VectorSRegister)( VSR55_VectorSRegisterEnumValue))
|
||||
#define VSR56 ((VectorSRegister)( VSR56_VectorSRegisterEnumValue))
|
||||
#define VSR57 ((VectorSRegister)( VSR57_VectorSRegisterEnumValue))
|
||||
#define VSR58 ((VectorSRegister)( VSR58_VectorSRegisterEnumValue))
|
||||
#define VSR59 ((VectorSRegister)( VSR59_VectorSRegisterEnumValue))
|
||||
#define VSR60 ((VectorSRegister)( VSR60_VectorSRegisterEnumValue))
|
||||
#define VSR61 ((VectorSRegister)( VSR61_VectorSRegisterEnumValue))
|
||||
#define VSR62 ((VectorSRegister)( VSR62_VectorSRegisterEnumValue))
|
||||
#define VSR63 ((VectorSRegister)( VSR63_VectorSRegisterEnumValue))
|
||||
#endif // DONT_USE_REGISTER_DEFINES
|
||||
|
||||
// Maximum number of incoming arguments that can be passed in i registers.
|
||||
@ -609,7 +677,7 @@ class ConcreteRegisterImpl : public AbstractRegisterImpl {
|
||||
* 2 // register halves
|
||||
+ ConditionRegisterImpl::number_of_registers // condition code registers
|
||||
+ SpecialRegisterImpl::number_of_registers // special registers
|
||||
+ VectorRegisterImpl::number_of_registers // vector registers
|
||||
+ VectorRegisterImpl::number_of_registers // VSX registers
|
||||
};
|
||||
|
||||
static const int max_gpr;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user