From 96fb31e2dbc16875c6c8183096cd03f30d0632ee Mon Sep 17 00:00:00 2001
From: Dingli Zhang <dzhang@openjdk.org>
Date: Wed, 28 May 2025 02:27:06 +0000
Subject: [PATCH] 8357695: RISC-V: Move vector intrinsic condition checks into
 match_rule_supported_vector

Reviewed-by: fyang, fjiang
---
 src/hotspot/cpu/riscv/riscv.ad   | 15 ---------------
 src/hotspot/cpu/riscv/riscv_v.ad | 14 ++++++++++++++
 2 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index 3cc645c8fe6..c711d2db640 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -1882,18 +1882,6 @@ bool Matcher::match_rule_supported(int opcode) {
     case Op_EncodeISOArray:
       return UseRVV;
 
-    // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
-    // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
-    case Op_RoundVF:
-      return UseRVV && MaxVectorSize >= 32;
-
-    // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
-    // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
-    // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
-    // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
-    case Op_RoundVD:
-      return UseRVV && MaxVectorSize >= 64;
-
     case Op_PopCountI:
     case Op_PopCountL:
       return UsePopCountInstruction;
@@ -1917,9 +1905,6 @@ bool Matcher::match_rule_supported(int opcode) {
     case Op_FmaF:
     case Op_FmaD:
       return UseFMA;
-    case Op_FmaVF:
-    case Op_FmaVD:
-      return UseRVV && UseFMA;
 
     case Op_ConvHF2F:
     case Op_ConvF2HF:
diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad
index de4c2b408d4..8b5759ce11c 100644
--- a/src/hotspot/cpu/riscv/riscv_v.ad
+++ b/src/hotspot/cpu/riscv/riscv_v.ad
@@ -122,6 +122,20 @@ source %{
         return UseZvfh;
       case Op_FmaVHF:
         return UseZvfh && UseFMA;
+      case Op_FmaVF:
+      case Op_FmaVD:
+        return UseFMA;
+
+      // For float, current test shows that, it brings performance gain when vlen >= 8, but brings
+      // regression when vlen == 4. So only enable this intrinsic when vlen >= 8.
+      // For double, current test shows that even with vlen == 4, there is still some regression.
+      // Although there is no hardware to verify it, from the trend of performance data on hardwares
+      // (with vlen == 2 and 4 respectively), it's promising to bring better performance rather than
+      // regression for double when vlen == 8. So only enable this intrinsic when vlen >= 8.
+      case Op_RoundVF:
+      case Op_RoundVD:
+        return vlen >= 8;
+
       default:
         break;
     }