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https://github.com/openjdk/jdk.git
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8167987: change merge context to clear for mask register usage model
Reviewed-by: kvn
This commit is contained in:
Michael Berg
parent
23e5629a05
commit
993bfb6565
@ -2461,6 +2461,7 @@ void Assembler::movdqu(Address dst, XMMRegister src) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
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emit_int8(0x7F);
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emit_operand(src, dst);
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@ -2490,6 +2491,7 @@ void Assembler::vmovdqu(Address dst, XMMRegister src) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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// swap src<->dst for encoding
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assert(src != xnoreg, "sanity");
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
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@ -2590,6 +2592,7 @@ void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vect
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.set_is_evex_instruction();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
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@ -2623,6 +2626,7 @@ void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_is_evex_instruction();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
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emit_int8(0x7F);
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@ -2655,6 +2659,7 @@ void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_is_evex_instruction();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
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emit_int8(0x7F);
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@ -2794,6 +2799,7 @@ void Assembler::movsd(Address dst, XMMRegister src) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
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attributes.reset_is_clear_context();
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attributes.set_rex_vex_w_reverted();
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simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
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emit_int8(0x11);
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@ -2823,6 +2829,7 @@ void Assembler::movss(Address dst, XMMRegister src) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
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emit_int8(0x11);
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emit_operand(src, dst);
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@ -3362,6 +3369,7 @@ void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Addre
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.set_is_evex_instruction();
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int dst_enc = kdst->encoding();
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@ -3384,6 +3392,7 @@ void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMReg
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assert(is_vector_masking(), "");
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assert(VM_Version::supports_avx512vlbw(), "");
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InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.reset_is_clear_context();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.set_is_evex_instruction();
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int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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@ -3423,6 +3432,7 @@ void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Addre
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.set_is_evex_instruction();
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vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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@ -3493,6 +3503,7 @@ void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int
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assert(VM_Version::supports_evex(), "");
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InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_is_evex_instruction();
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attributes.reset_is_clear_context();
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int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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emit_int8(0x76);
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emit_int8((unsigned char)(0xC0 | encode));
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@ -3503,6 +3514,7 @@ void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vect
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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attributes.set_is_evex_instruction();
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int dst_enc = kdst->encoding();
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vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
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@ -3532,6 +3544,7 @@ void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int
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void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
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assert(VM_Version::supports_evex(), "");
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InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.reset_is_clear_context();
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attributes.set_is_evex_instruction();
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int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
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emit_int8(0x29);
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@ -3543,6 +3556,7 @@ void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vect
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assert(VM_Version::supports_evex(), "");
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
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attributes.reset_is_clear_context();
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attributes.set_is_evex_instruction();
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attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
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int dst_enc = kdst->encoding();
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@ -3763,6 +3777,7 @@ void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vecto
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
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attributes.reset_is_clear_context();
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attributes.set_embedded_opmask_register_specifier(mask);
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attributes.set_is_evex_instruction();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
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@ -6208,6 +6223,7 @@ void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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emit_int8(0x39);
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emit_operand(src, dst);
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@ -6238,6 +6254,7 @@ void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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emit_int8(0x39);
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emit_operand(src, dst);
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@ -6298,6 +6315,7 @@ void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
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InstructionMark im(this);
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InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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emit_int8(0x19);
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emit_operand(src, dst);
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@ -6328,6 +6346,7 @@ void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
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attributes.reset_is_clear_context();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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emit_int8(0x19);
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emit_operand(src, dst);
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@ -6371,6 +6390,7 @@ void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
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InstructionMark im(this);
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InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
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attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
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attributes.reset_is_clear_context();
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vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
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emit_int8(0x1B);
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emit_operand(src, dst);
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@ -7181,7 +7201,9 @@ void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, boo
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// fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
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byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
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// last is EVEX.z for zero/merge actions
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byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
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if (_attributes->is_no_reg_mask() == false) {
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byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
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}
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emit_int8(byte4);
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}
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@ -2139,7 +2139,7 @@ public:
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_input_size_in_bits(Assembler::EVEX_NObit),
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_is_evex_instruction(false),
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_evex_encoding(0),
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_is_clear_context(false),
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_is_clear_context(true),
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_is_extended_context(false),
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_current_assembler(NULL),
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_embedded_opmask_register_specifier(1) { // hard code k1, it will be initialized for now
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@ -2205,7 +2205,7 @@ public:
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void set_evex_encoding(int value) { _evex_encoding = value; }
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// Set the Evex.Z field to be used to clear all non directed XMM/YMM/ZMM components
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void set_is_clear_context(void) { _is_clear_context = true; }
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void reset_is_clear_context(void) { _is_clear_context = false; }
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// Map back to current asembler so that we can manage object level assocation
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void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
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