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8297359: RISC-V: improve performance of floating Max Min intrinsics

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Reviewed-by: fyang
This commit is contained in:
Vladimir Kempik 2022-11-26 16:15:55 +00:00
parent 6c05771b9b
commit 99d3840d36
2 changed files with 22 additions and 21 deletions
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27
src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
View File

@ -1329,27 +1329,28 @@ void C2_MacroAssembler::minmax_FD(FloatRegister dst, FloatRegister src1, FloatRe
bool is_double, bool is_min) {
assert_different_registers(dst, src1, src2);
Label Done;
fsflags(zr);
Label Done, Compare;
is_double ? fclass_d(t0, src1)
: fclass_s(t0, src1);
is_double ? fclass_d(t1, src2)
: fclass_s(t1, src2);
orr(t0, t0, t1);
andi(t0, t0, 0b1100000000); //if src1 or src2 is quiet or signaling NaN then return NaN
beqz(t0, Compare);
is_double ? fadd_d(dst, src1, src2)
: fadd_s(dst, src1, src2);
j(Done);
bind(Compare);
if (is_double) {
is_min ? fmin_d(dst, src1, src2)
: fmax_d(dst, src1, src2);
// Checking NaNs
flt_d(zr, src1, src2);
} else {
is_min ? fmin_s(dst, src1, src2)
: fmax_s(dst, src1, src2);
// Checking NaNs
flt_s(zr, src1, src2);
}
frflags(t0);
beqz(t0, Done);
// In case of NaNs
is_double ? fadd_d(dst, src1, src2)
: fadd_s(dst, src1, src2);
bind(Done);
}

16
src/hotspot/cpu/riscv/riscv.ad
View File

@ -7226,9 +7226,9 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
%}
// Math.max(FF)F
instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
match(Set dst (MaxF src1 src2));
effect(TEMP_DEF dst);
effect(TEMP_DEF dst, KILL cr);
format %{ "maxF $dst, $src1, $src2" %}
@ -7242,9 +7242,9 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
%}
// Math.min(FF)F
instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
match(Set dst (MinF src1 src2));
effect(TEMP_DEF dst);
effect(TEMP_DEF dst, KILL cr);
format %{ "minF $dst, $src1, $src2" %}
@ -7258,9 +7258,9 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
%}
// Math.max(DD)D
instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
match(Set dst (MaxD src1 src2));
effect(TEMP_DEF dst);
effect(TEMP_DEF dst, KILL cr);
format %{ "maxD $dst, $src1, $src2" %}
@ -7274,9 +7274,9 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
%}
// Math.min(DD)D
instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
match(Set dst (MinD src1 src2));
effect(TEMP_DEF dst);
effect(TEMP_DEF dst, KILL cr);
format %{ "minD $dst, $src1, $src2" %}