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8351162: Clean up x86 (Macro)Assembler after 32-bit x86 removal
Reviewed-by: kvn, coleenp
This commit is contained in:
Aleksey Shipilev
parent
2be5bc847a
commit
9a5c7b3fa9
@ -24,6 +24,8 @@
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#include "asm/assembler.hpp"
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#include "asm/assembler.inline.hpp"
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#include "asm/codeBuffer.hpp"
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#include "code/codeCache.hpp"
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#include "gc/shared/cardTableBarrierSet.hpp"
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#include "interpreter/interpreter.hpp"
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#include "memory/resourceArea.hpp"
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@ -119,8 +121,6 @@ AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
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// Implementation of Address
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#ifdef _LP64
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Address Address::make_array(ArrayAddress adr) {
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// Not implementable on 64bit machines
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// Should have been handled higher up the call chain.
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@ -157,30 +157,6 @@ Address::Address(int disp, address loc, relocInfo::relocType rtype) {
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ShouldNotReachHere();
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}
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}
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#else // LP64
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Address Address::make_array(ArrayAddress adr) {
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AddressLiteral base = adr.base();
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Address index = adr.index();
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assert(index._disp == 0, "must not have disp"); // maybe it can?
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Address array(index._base, index._index, index._scale, (intptr_t) base.target());
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array._rspec = base._rspec;
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return array;
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}
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// exceedingly dangerous constructor
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Address::Address(address loc, RelocationHolder spec) {
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_base = noreg;
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_index = noreg;
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_scale = no_scale;
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_disp = (intptr_t) loc;
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_rspec = spec;
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_xmmindex = xnoreg;
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_isxmmindex = false;
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}
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#endif // _LP64
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// Convert the raw encoding form into the form expected by the constructor for
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@ -214,7 +190,6 @@ void Assembler::init_attributes(void) {
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_legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
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_legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
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_legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
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NOT_LP64(_is_managed = false;)
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_attributes = nullptr;
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}
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@ -744,8 +719,8 @@ void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc,
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assert(inst_mark() != nullptr, "must be inside InstructionMark");
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address next_ip = pc() + sizeof(int32_t) + post_addr_length;
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int64_t adjusted = disp;
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// Do rip-rel adjustment for 64bit
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LP64_ONLY(adjusted -= (next_ip - inst_mark()));
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// Do rip-rel adjustment
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adjusted -= (next_ip - inst_mark());
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assert(is_simm32(adjusted),
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"must be 32bit offset (RIP relative address)");
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emit_data((int32_t) adjusted, rspec, disp32_operand);
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@ -846,7 +821,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case FS_segment:
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case GS_segment:
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// Seems dubious
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LP64_ONLY(assert(false, "shouldn't have that prefix"));
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assert(false, "shouldn't have that prefix");
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assert(ip == inst+1, "only one prefix allowed");
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goto again_after_prefix;
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@ -859,11 +834,9 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case REX_RB:
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case REX_RX:
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case REX_RXB:
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NOT_LP64(assert(false, "64bit prefixes"));
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goto again_after_prefix;
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case REX2:
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NOT_LP64(assert(false, "64bit prefixes"));
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if ((0xFF & *ip++) & REX2BIT_W) {
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is_64bit = true;
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}
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@ -877,7 +850,6 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case REX_WRB:
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case REX_WRX:
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case REX_WRXB:
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NOT_LP64(assert(false, "64bit prefixes"));
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is_64bit = true;
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goto again_after_prefix;
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@ -916,11 +888,9 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case REX_WRB:
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case REX_WRX:
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case REX_WRXB:
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NOT_LP64(assert(false, "64bit prefix found"));
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goto again_after_size_prefix2;
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case REX2:
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NOT_LP64(assert(false, "64bit prefix found"));
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if ((0xFF & *ip++) & REX2BIT_W) {
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is_64bit = true;
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}
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@ -945,14 +915,9 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case REP8(0xB8): // movl/q r, #32/#64(oop?)
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if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
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// these asserts are somewhat nonsensical
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#ifndef _LP64
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assert(which == imm_operand || which == disp32_operand,
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"which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
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#else
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assert(((which == call32_operand || which == imm_operand) && is_64bit) ||
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(which == narrow_oop_operand && !is_64bit),
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"which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
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#endif // _LP64
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return ip;
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case 0x69: // imul r, a, #32
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@ -1113,8 +1078,6 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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// to check for them in product version.
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// Check second byte
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NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
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int vex_opcode;
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// First byte
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if ((0xFF & *inst) == VEX_3bytes) {
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@ -1216,8 +1179,8 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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case REX_WRX:
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case REX_WRXB:
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case REX2:
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NOT_LP64(assert(false, "found 64bit prefix"));
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ip++;
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// fall-through
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default:
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ip++;
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}
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@ -1232,12 +1195,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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}
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assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
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#ifdef _LP64
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assert(which != imm_operand, "instruction is not a movq reg, imm64");
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#else
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// assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
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assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
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#endif // LP64
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assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
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// parse the output of emit_operand
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@ -1292,11 +1250,7 @@ address Assembler::locate_operand(address inst, WhichOperand which) {
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return ip + tail_size;
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}
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#ifdef _LP64
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assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
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#else
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assert(which == imm_operand, "instruction has only an imm field");
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#endif // LP64
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return ip;
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}
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@ -1319,8 +1273,7 @@ void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
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// assert(format == imm32_operand, "cannot specify a nonzero format");
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opnd = locate_operand(inst, call32_operand);
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} else if (r->is_data()) {
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assert(format == imm_operand || format == disp32_operand
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LP64_ONLY(|| format == narrow_oop_operand), "format ok");
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assert(format == imm_operand || format == disp32_operand || format == narrow_oop_operand, "format ok");
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opnd = locate_operand(inst, (WhichOperand)format);
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} else {
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assert(format == imm_operand, "cannot specify a format");
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@ -1830,9 +1783,6 @@ void Assembler::blsrl(Register dst, Address src) {
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}
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void Assembler::call(Label& L, relocInfo::relocType rtype) {
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// suspect disp32 is always good
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int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
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if (L.is_bound()) {
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const int long_size = 5;
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int offs = (int)( target(L) - pc() );
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@ -1840,14 +1790,14 @@ void Assembler::call(Label& L, relocInfo::relocType rtype) {
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InstructionMark im(this);
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// 1110 1000 #32-bit disp
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emit_int8((unsigned char)0xE8);
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emit_data(offs - long_size, rtype, operand);
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emit_data(offs - long_size, rtype, disp32_operand);
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} else {
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InstructionMark im(this);
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// 1110 1000 #32-bit disp
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L.add_patch_at(code(), locator());
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emit_int8((unsigned char)0xE8);
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emit_data(int(0), rtype, operand);
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emit_data(int(0), rtype, disp32_operand);
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}
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}
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@ -1874,8 +1824,7 @@ void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
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// Technically, should use call32_operand, but this format is
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// implied by the fact that we're emitting a call instruction.
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int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
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emit_data((int) disp, rspec, operand);
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emit_data((int) disp, rspec, disp32_operand);
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}
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void Assembler::cdql() {
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@ -1887,7 +1836,6 @@ void Assembler::cld() {
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}
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void Assembler::cmovl(Condition cc, Register dst, Register src) {
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NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
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int encode = prefix_and_encode(dst->encoding(), src->encoding(), true /* is_map1 */);
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emit_opcode_prefix_and_encoding(0x40 | cc, 0xC0, encode);
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}
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@ -1900,7 +1848,6 @@ void Assembler::ecmovl(Condition cc, Register dst, Register src1, Register src2)
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void Assembler::cmovl(Condition cc, Register dst, Address src) {
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InstructionMark im(this);
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NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
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prefix(src, dst, false, true /* is_map1 */);
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emit_int8((0x40 | cc));
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emit_operand(dst, src, 0);
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@ -2091,8 +2038,7 @@ void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
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case 2:
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case 4:
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break;
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LP64_ONLY(case 8:)
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// This instruction is not valid in 32 bits
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case 8:
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// Note:
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// http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
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//
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@ -2111,7 +2057,7 @@ void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
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assert(0, "Unsupported value for a sizeInBytes argument");
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break;
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}
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LP64_ONLY(prefix(crc, v, p);)
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prefix(crc, v, p);
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emit_int32(0x0F,
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0x38,
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0xF0 | w,
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@ -2140,15 +2086,14 @@ void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
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case 2:
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case 4:
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break;
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LP64_ONLY(case 8:)
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// This instruction is not valid in 32 bits
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case 8:
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p = REX_W;
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break;
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default:
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assert(0, "Unsupported value for a sizeInBytes argument");
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break;
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}
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LP64_ONLY(prefix(crc, adr, p);)
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prefix(crc, adr, p);
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emit_int24(0x0F, 0x38, (0xF0 | w));
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emit_operand(crc, adr, 0);
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}
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@ -2840,7 +2785,6 @@ void Assembler::leal(Register dst, Address src) {
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emit_operand(dst, src, 0);
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}
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#ifdef _LP64
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void Assembler::lea(Register dst, Label& L) {
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emit_prefix_and_int8(get_prefixq(Address(), dst), (unsigned char)0x8D);
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if (!L.is_bound()) {
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@ -2858,7 +2802,6 @@ void Assembler::lea(Register dst, Label& L) {
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emit_int32(disp);
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}
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}
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#endif
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void Assembler::lfence() {
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emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
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@ -2916,7 +2859,7 @@ void Assembler::sfence() {
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}
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void Assembler::mov(Register dst, Register src) {
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LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
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movq(dst, src);
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}
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void Assembler::movapd(XMMRegister dst, XMMRegister src) {
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@ -2941,7 +2884,6 @@ void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
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}
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void Assembler::movb(Register dst, Address src) {
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NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
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InstructionMark im(this);
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prefix(src, dst, true);
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emit_int8((unsigned char)0x8A);
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@ -3932,7 +3874,6 @@ void Assembler::movsbl(Register dst, Address src) { // movsxb
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}
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void Assembler::movsbl(Register dst, Register src) { // movsxb
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NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
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int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true, true /* is_map1 */);
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emit_opcode_prefix_and_encoding((unsigned char)0xBE, 0xC0, encode);
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}
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@ -4082,7 +4023,6 @@ void Assembler::movzbl(Register dst, Address src) { // movzxb
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}
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void Assembler::movzbl(Register dst, Register src) { // movzxb
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NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
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int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true, true /* is_map1 */);
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emit_opcode_prefix_and_encoding((unsigned char)0xB6, 0xC0, encode);
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}
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@ -5810,16 +5750,6 @@ void Assembler::popf() {
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emit_int8((unsigned char)0x9D);
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}
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#ifndef _LP64 // no 32bit push/pop on amd64
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void Assembler::popl(Address dst) {
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// NOTE: this will adjust stack by 8byte on 64bits
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InstructionMark im(this);
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prefix(dst);
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emit_int8((unsigned char)0x8F);
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emit_operand(rax, dst, 0);
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}
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#endif
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void Assembler::prefetchnta(Address src) {
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InstructionMark im(this);
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prefix(src, true /* is_map1 */);
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@ -6220,7 +6150,6 @@ void Assembler::evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1,
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emit_int16(0x6D, (0xC0 | encode));
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}
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#ifdef _LP64
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void Assembler::push2(Register src1, Register src2, bool with_ppx) {
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assert(VM_Version::supports_apx_f(), "requires APX");
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InstructionAttr attributes(0, /* rex_w */ with_ppx, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
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@ -6282,8 +6211,6 @@ void Assembler::popp(Register dst) {
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int encode = prefixq_and_encode_rex2(dst->encoding());
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emit_int8((unsigned char)0x58 | encode);
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}
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#endif //_LP64
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void Assembler::push(int32_t imm32) {
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// in 64bits we push 64bits onto the stack but only
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@ -6301,16 +6228,6 @@ void Assembler::pushf() {
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emit_int8((unsigned char)0x9C);
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}
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#ifndef _LP64 // no 32bit push/pop on amd64
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void Assembler::pushl(Address src) {
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// Note this will push 64bit on 64bit
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InstructionMark im(this);
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prefix(src);
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emit_int8((unsigned char)0xFF);
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emit_operand(rsi, src, 0);
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}
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#endif
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void Assembler::rcll(Register dst, int imm8) {
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assert(isShiftCount(imm8), "illegal shift count");
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int encode = prefix_and_encode(dst->encoding());
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@ -6353,43 +6270,37 @@ void Assembler::rdtsc() {
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void Assembler::rep_mov() {
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// REP
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// MOVSQ
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LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
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NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);)
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emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);
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}
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// sets rcx bytes with rax, value at [edi]
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void Assembler::rep_stosb() {
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// REP
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// STOSB
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LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
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NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);)
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emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);
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}
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// sets rcx pointer sized words with rax, value at [edi]
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// generic
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void Assembler::rep_stos() {
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// REP
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// LP64:STOSQ, LP32:STOSD
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LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
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NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
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// STOSQ
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emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);
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}
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// scans rcx pointer sized words at [edi] for occurrence of rax,
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// generic
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void Assembler::repne_scan() { // repne_scan
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// SCASQ
|
||||
LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
|
||||
NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);)
|
||||
emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
// scans rcx 4 byte words at [edi] for occurrence of rax,
|
||||
// generic
|
||||
void Assembler::repne_scanl() { // repne_scan
|
||||
// SCASL
|
||||
emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
|
||||
}
|
||||
#endif
|
||||
|
||||
void Assembler::ret(int imm16) {
|
||||
if (imm16 == 0) {
|
||||
@ -6464,7 +6375,6 @@ void Assembler::erorl(Register dst, Register src, bool no_flags) {
|
||||
emit_int16((unsigned char)0xD3, (0xC8 | encode));
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
void Assembler::rorq(Register dst) {
|
||||
int encode = prefixq_and_encode(dst->encoding());
|
||||
emit_int16((unsigned char)0xD3, (0xC8 | encode));
|
||||
@ -6527,15 +6437,6 @@ void Assembler::erolq(Register dst, Register src, int imm8, bool no_flags) {
|
||||
} else {
|
||||
emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void Assembler::sahf() {
|
||||
#ifdef _LP64
|
||||
// Not supported in 64bit mode
|
||||
ShouldNotReachHere();
|
||||
#endif
|
||||
emit_int8((unsigned char)0x9E);
|
||||
}
|
||||
|
||||
void Assembler::sall(Address dst, int imm8) {
|
||||
@ -6988,7 +6889,6 @@ void Assembler::eshrdl(Register dst, Register src1, Register src2, int8_t imm8,
|
||||
emit_int24(0x2C, (0xC0 | encode), imm8);
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
void Assembler::shldq(Register dst, Register src, int8_t imm8) {
|
||||
int encode = prefixq_and_encode(src->encoding(), dst->encoding(), true /* is_map1 */);
|
||||
emit_opcode_prefix_and_encoding((unsigned char)0xA4, 0xC0, encode, imm8);
|
||||
@ -7014,7 +6914,6 @@ void Assembler::eshrdq(Register dst, Register src1, Register src2, int8_t imm8,
|
||||
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
|
||||
emit_int24(0x2C, (0xC0 | encode), imm8);
|
||||
}
|
||||
#endif
|
||||
|
||||
// copies a single word from [esi] to [edi]
|
||||
void Assembler::smovl() {
|
||||
@ -7208,7 +7107,6 @@ void Assembler::subss(XMMRegister dst, Address src) {
|
||||
}
|
||||
|
||||
void Assembler::testb(Register dst, int imm8, bool use_ral) {
|
||||
NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
|
||||
if (dst == rax) {
|
||||
if (use_ral) {
|
||||
emit_int8((unsigned char)0xA8);
|
||||
@ -12872,54 +12770,6 @@ void Assembler::emit_farith(int b1, int b2, int i) {
|
||||
emit_int16(b1, b2 + i);
|
||||
}
|
||||
|
||||
#ifndef _LP64
|
||||
// 32bit only pieces of the assembler
|
||||
|
||||
void Assembler::emms() {
|
||||
NOT_LP64(assert(VM_Version::supports_mmx(), ""));
|
||||
emit_int16(0x0F, 0x77);
|
||||
}
|
||||
|
||||
void Assembler::vzeroupper() {
|
||||
vzeroupper_uncached();
|
||||
}
|
||||
|
||||
void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
|
||||
// NO PREFIX AS NEVER 64BIT
|
||||
InstructionMark im(this);
|
||||
emit_int16((unsigned char)0x81, (0xF8 | src1->encoding()));
|
||||
emit_data(imm32, rspec, 0);
|
||||
}
|
||||
|
||||
void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
|
||||
// NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
|
||||
InstructionMark im(this);
|
||||
emit_int8((unsigned char)0x81);
|
||||
emit_operand(rdi, src1, 4);
|
||||
emit_data(imm32, rspec, 0);
|
||||
}
|
||||
|
||||
// The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
|
||||
// and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
|
||||
// into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
|
||||
void Assembler::cmpxchg8(Address adr) {
|
||||
InstructionMark im(this);
|
||||
emit_int16(0x0F, (unsigned char)0xC7);
|
||||
emit_operand(rcx, adr, 0);
|
||||
}
|
||||
|
||||
void Assembler::decl(Register dst) {
|
||||
// Don't use it directly. Use MacroAssembler::decrementl() instead.
|
||||
emit_int8(0x48 | dst->encoding());
|
||||
}
|
||||
|
||||
void Assembler::edecl(Register dst, Register src, bool no_flags) {
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
(void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
|
||||
emit_int8(0x48 | src->encoding());
|
||||
}
|
||||
#endif // !_LP64
|
||||
|
||||
// SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
|
||||
static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
|
||||
// SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
|
||||
@ -13053,7 +12903,7 @@ void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix
|
||||
// is allowed in legacy mode and has resources which will fit in it.
|
||||
// Pure EVEX instructions will have is_evex_instruction set in their definition.
|
||||
if (!attributes->is_legacy_mode()) {
|
||||
if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
|
||||
if (UseAVX > 2 && !attributes->is_evex_instruction()) {
|
||||
if ((attributes->get_vector_len() != AVX_512bit) && !is_extended) {
|
||||
attributes->set_is_legacy_mode();
|
||||
}
|
||||
@ -13068,7 +12918,6 @@ void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix
|
||||
assert((!is_extended || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
|
||||
}
|
||||
|
||||
clear_managed();
|
||||
if (UseAVX > 2 && !attributes->is_legacy_mode())
|
||||
{
|
||||
bool evex_r = (xreg_enc >= 16);
|
||||
@ -13116,7 +12965,7 @@ int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexS
|
||||
// is allowed in legacy mode and has resources which will fit in it.
|
||||
// Pure EVEX instructions will have is_evex_instruction set in their definition.
|
||||
if (!attributes->is_legacy_mode()) {
|
||||
if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
|
||||
if (UseAVX > 2 && !attributes->is_evex_instruction()) {
|
||||
if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
|
||||
!is_extended) {
|
||||
attributes->set_is_legacy_mode();
|
||||
@ -13138,7 +12987,6 @@ int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexS
|
||||
assert(((!is_extended) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
|
||||
}
|
||||
|
||||
clear_managed();
|
||||
if (UseAVX > 2 && !attributes->is_legacy_mode())
|
||||
{
|
||||
bool evex_r = (dst_enc >= 16);
|
||||
@ -14038,55 +13886,6 @@ void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, b
|
||||
emit_int16((unsigned char)0x8A, (0xC0 | encode));
|
||||
}
|
||||
|
||||
#ifndef _LP64
|
||||
|
||||
void Assembler::incl(Register dst) {
|
||||
// Don't use it directly. Use MacroAssembler::incrementl() instead.
|
||||
emit_int8(0x40 | dst->encoding());
|
||||
}
|
||||
|
||||
void Assembler::eincl(Register dst, Register src, bool no_flags) {
|
||||
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
|
||||
(void) evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
|
||||
emit_int8(0x40 | src->encoding());
|
||||
}
|
||||
|
||||
void Assembler::lea(Register dst, Address src) {
|
||||
leal(dst, src);
|
||||
}
|
||||
|
||||
void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
|
||||
InstructionMark im(this);
|
||||
emit_int8((unsigned char)0xC7);
|
||||
emit_operand(rax, dst, 4);
|
||||
emit_data((int)imm32, rspec, 0);
|
||||
}
|
||||
|
||||
void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
|
||||
InstructionMark im(this);
|
||||
int encode = prefix_and_encode(dst->encoding());
|
||||
emit_int8((0xB8 | encode));
|
||||
emit_data((int)imm32, rspec, 0);
|
||||
}
|
||||
|
||||
void Assembler::popa() { // 32bit
|
||||
emit_int8(0x61);
|
||||
}
|
||||
|
||||
void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
|
||||
InstructionMark im(this);
|
||||
emit_int8(0x68);
|
||||
emit_data(imm32, rspec, 0);
|
||||
}
|
||||
|
||||
void Assembler::pusha() { // 32bit
|
||||
emit_int8(0x60);
|
||||
}
|
||||
|
||||
#else // LP64
|
||||
|
||||
// 64bit only pieces of the assembler
|
||||
|
||||
// This should only be used by 64bit instructions that can use rip-relative
|
||||
// it cannot be used by instructions that want an immediate value.
|
||||
|
||||
@ -16039,7 +15838,6 @@ void Assembler::rorxq(Register dst, Address src, int imm8) {
|
||||
emit_int8(imm8);
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
void Assembler::salq(Address dst, int imm8) {
|
||||
InstructionMark im(this);
|
||||
assert(isShiftCount(imm8 >> 1), "illegal shift count");
|
||||
@ -16194,7 +15992,6 @@ void Assembler::esarq(Register dst, Register src, bool no_flags) {
|
||||
int encode = evex_prefix_and_encode_ndd(0, dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
|
||||
emit_int16((unsigned char)0xD3, (0xF8 | encode));
|
||||
}
|
||||
#endif
|
||||
|
||||
void Assembler::sbbq(Address dst, int32_t imm32) {
|
||||
InstructionMark im(this);
|
||||
@ -16539,8 +16336,6 @@ void Assembler::exorq(Register dst, Address src1, Register src2, bool no_flags)
|
||||
emit_operand(src2, src1, 0);
|
||||
}
|
||||
|
||||
#endif // !LP64
|
||||
|
||||
void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) {
|
||||
if (VM_Version::supports_evex()) {
|
||||
_tuple_type = tuple_type;
|
||||
|
||||
@ -35,7 +35,6 @@
|
||||
class Argument {
|
||||
public:
|
||||
enum {
|
||||
#ifdef _LP64
|
||||
#ifdef _WIN64
|
||||
n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
|
||||
n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
|
||||
@ -49,16 +48,10 @@ class Argument {
|
||||
#endif // _WIN64
|
||||
n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
|
||||
n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
|
||||
#else
|
||||
n_register_parameters = 0, // 0 registers used to pass arguments
|
||||
n_int_register_parameters_j = 0,
|
||||
n_float_register_parameters_j = 0
|
||||
#endif // _LP64
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
#ifdef _LP64
|
||||
// Symbolically name the register arguments used by the c calling convention.
|
||||
// Windows is different from linux/solaris. So much for standards...
|
||||
|
||||
@ -138,15 +131,6 @@ constexpr Register rscratch2 = r11; // volatile
|
||||
constexpr Register r12_heapbase = r12; // callee-saved
|
||||
constexpr Register r15_thread = r15; // callee-saved
|
||||
|
||||
#else
|
||||
// rscratch1 will appear in 32bit code that is dead but of course must compile
|
||||
// Using noreg ensures if the dead code is incorrectly live and executed it
|
||||
// will cause an assertion failure
|
||||
#define rscratch1 noreg
|
||||
#define rscratch2 noreg
|
||||
|
||||
#endif // _LP64
|
||||
|
||||
// JSR 292
|
||||
// On x86, the SP does not have to be saved when invoking method handle intrinsics
|
||||
// or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
|
||||
@ -168,7 +152,7 @@ class Address {
|
||||
times_2 = 1,
|
||||
times_4 = 2,
|
||||
times_8 = 3,
|
||||
times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
|
||||
times_ptr = times_8
|
||||
};
|
||||
static ScaleFactor times(int size) {
|
||||
assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
|
||||
@ -197,7 +181,6 @@ class Address {
|
||||
|
||||
// Easily misused constructors make them private
|
||||
// %%% can we make these go away?
|
||||
NOT_LP64(Address(address loc, RelocationHolder spec);)
|
||||
Address(int disp, address loc, relocInfo::relocType rtype);
|
||||
Address(int disp, address loc, RelocationHolder spec);
|
||||
|
||||
@ -456,7 +439,7 @@ class InstructionAttr;
|
||||
|
||||
// 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
|
||||
// See fxsave and xsave(EVEX enabled) documentation for layout
|
||||
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
|
||||
const int FPUStateSizeInWords = 2688 / wordSize;
|
||||
|
||||
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
|
||||
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
|
||||
@ -628,12 +611,8 @@ class Assembler : public AbstractAssembler {
|
||||
imm_operand = 0, // embedded 32-bit|64-bit immediate operand
|
||||
disp32_operand = 1, // embedded 32-bit displacement or address
|
||||
call32_operand = 2, // embedded 32-bit self-relative displacement
|
||||
#ifndef _LP64
|
||||
_WhichOperand_limit = 3
|
||||
#else
|
||||
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
|
||||
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
|
||||
_WhichOperand_limit = 4
|
||||
#endif
|
||||
};
|
||||
|
||||
// Comparison predicates for integral types & FP types when using SSE
|
||||
@ -721,7 +700,6 @@ private:
|
||||
bool _legacy_mode_dq;
|
||||
bool _legacy_mode_vl;
|
||||
bool _legacy_mode_vlbw;
|
||||
NOT_LP64(bool _is_managed;)
|
||||
|
||||
InstructionAttr *_attributes;
|
||||
void set_attributes(InstructionAttr* attributes);
|
||||
@ -907,25 +885,13 @@ private:
|
||||
void emit_opcode_prefix_and_encoding(int byte1, int ocp_and_encoding);
|
||||
void emit_opcode_prefix_and_encoding(int byte1, int byte2, int ocp_and_encoding);
|
||||
void emit_opcode_prefix_and_encoding(int byte1, int byte2, int ocp_and_encoding, int byte3);
|
||||
bool always_reachable(AddressLiteral adr) NOT_LP64( { return true; } );
|
||||
bool reachable(AddressLiteral adr) NOT_LP64( { return true; } );
|
||||
bool always_reachable(AddressLiteral adr);
|
||||
bool reachable(AddressLiteral adr);
|
||||
|
||||
|
||||
// These are all easily abused and hence protected
|
||||
|
||||
public:
|
||||
// 32BIT ONLY SECTION
|
||||
#ifndef _LP64
|
||||
// Make these disappear in 64bit mode since they would never be correct
|
||||
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
|
||||
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
|
||||
|
||||
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
|
||||
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
|
||||
|
||||
void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
|
||||
#else
|
||||
// 64BIT ONLY SECTION
|
||||
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
|
||||
|
||||
void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
|
||||
@ -933,7 +899,6 @@ private:
|
||||
|
||||
void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
|
||||
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
|
||||
#endif // _LP64
|
||||
|
||||
protected:
|
||||
// These are unique in that we are ensured by the caller that the 32bit
|
||||
@ -1017,17 +982,10 @@ private:
|
||||
void init_attributes(void);
|
||||
void clear_attributes(void) { _attributes = nullptr; }
|
||||
|
||||
void set_managed(void) { NOT_LP64(_is_managed = true;) }
|
||||
void clear_managed(void) { NOT_LP64(_is_managed = false;) }
|
||||
bool is_managed(void) {
|
||||
NOT_LP64(return _is_managed;)
|
||||
LP64_ONLY(return false;) }
|
||||
|
||||
void lea(Register dst, Address src);
|
||||
|
||||
void mov(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
// support caching the result of some routines
|
||||
|
||||
// must be called before pusha(), popa(), vzeroupper() - checked with asserts
|
||||
@ -1047,7 +1005,6 @@ private:
|
||||
// New Zero Upper setcc instruction.
|
||||
void esetzucc(Condition cc, Register dst);
|
||||
|
||||
#endif
|
||||
void vzeroupper_uncached();
|
||||
void decq(Register dst);
|
||||
void edecq(Register dst, Register src, bool no_flags);
|
||||
@ -1069,9 +1026,7 @@ private:
|
||||
void rep_stos();
|
||||
void rep_stosb();
|
||||
void repne_scan();
|
||||
#ifdef _LP64
|
||||
void repne_scanl();
|
||||
#endif
|
||||
|
||||
// Vanilla instructions in lexical order
|
||||
|
||||
@ -1121,7 +1076,6 @@ private:
|
||||
void eincq(Register dst, Register src, bool no_flags);
|
||||
void eincq(Register dst, Address src, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
//Add Unsigned Integers with Carry Flag
|
||||
void adcxq(Register dst, Register src);
|
||||
void eadcxq(Register dst, Register src1, Register src2);
|
||||
@ -1129,7 +1083,6 @@ private:
|
||||
//Add Unsigned Integers with Overflow Flag
|
||||
void adoxq(Register dst, Register src);
|
||||
void eadoxq(Register dst, Register src1, Register src2);
|
||||
#endif
|
||||
|
||||
void addr_nop_4();
|
||||
void addr_nop_5();
|
||||
@ -1206,10 +1159,8 @@ private:
|
||||
void bsfl(Register dst, Register src);
|
||||
void bsrl(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void bsfq(Register dst, Register src);
|
||||
void bsrq(Register dst, Register src);
|
||||
#endif
|
||||
|
||||
void bswapl(Register reg);
|
||||
|
||||
@ -1395,10 +1346,6 @@ private:
|
||||
void emit_farith(int b1, int b2, int i);
|
||||
|
||||
public:
|
||||
#ifndef _LP64
|
||||
void emms();
|
||||
#endif // !_LP64
|
||||
|
||||
// operands that only take the original 32bit registers
|
||||
void emit_operand32(Register reg, Address adr, int post_addr_length);
|
||||
|
||||
@ -1417,12 +1364,10 @@ private:
|
||||
void divl(Register src); // Unsigned division
|
||||
void edivl(Register src, bool no_flags); // Unsigned division
|
||||
|
||||
#ifdef _LP64
|
||||
void idivq(Register src);
|
||||
void eidivq(Register src, bool no_flags);
|
||||
void divq(Register src); // Unsigned division
|
||||
void edivq(Register src, bool no_flags); // Unsigned division
|
||||
#endif
|
||||
|
||||
void imull(Register src);
|
||||
void eimull(Register src, bool no_flags);
|
||||
@ -1435,7 +1380,6 @@ private:
|
||||
void imull(Register dst, Address src);
|
||||
void eimull(Register dst, Register src1, Address src2, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void imulq(Register dst, Register src);
|
||||
void eimulq(Register dst, Register src, bool no_flags);
|
||||
void eimulq(Register dst, Register src1, Register src2, bool no_flags);
|
||||
@ -1448,7 +1392,6 @@ private:
|
||||
void eimulq(Register dst, Register src1, Address src2, bool no_flags);
|
||||
void imulq(Register dst);
|
||||
void eimulq(Register dst, bool no_flags);
|
||||
#endif
|
||||
|
||||
// jcc is the generic conditional branch generator to run-
|
||||
// time routines, jcc is used for branches to labels. jcc
|
||||
@ -1500,9 +1443,7 @@ private:
|
||||
|
||||
void leaq(Register dst, Address src);
|
||||
|
||||
#ifdef _LP64
|
||||
void lea(Register dst, Label& L);
|
||||
#endif
|
||||
|
||||
void lfence();
|
||||
|
||||
@ -1514,12 +1455,10 @@ private:
|
||||
void lzcntl(Register dst, Address src);
|
||||
void elzcntl(Register dst, Address src, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void lzcntq(Register dst, Register src);
|
||||
void elzcntq(Register dst, Register src, bool no_flags);
|
||||
void lzcntq(Register dst, Address src);
|
||||
void elzcntq(Register dst, Address src, bool no_flags);
|
||||
#endif
|
||||
|
||||
enum Membar_mask_bits {
|
||||
StoreStore = 1 << 3,
|
||||
@ -1679,13 +1618,11 @@ private:
|
||||
void movl(Register dst, Address src);
|
||||
void movl(Address dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void movq(Register dst, Register src);
|
||||
void movq(Register dst, Address src);
|
||||
void movq(Address dst, Register src);
|
||||
void movq(Address dst, int32_t imm32);
|
||||
void movq(Register dst, int32_t imm32);
|
||||
#endif
|
||||
|
||||
// Move Quadword
|
||||
void movq(Address dst, XMMRegister src);
|
||||
@ -1700,7 +1637,6 @@ private:
|
||||
void vmovw(XMMRegister dst, Register src);
|
||||
void vmovw(Register dst, XMMRegister src);
|
||||
|
||||
#ifdef _LP64
|
||||
void movsbq(Register dst, Address src);
|
||||
void movsbq(Register dst, Register src);
|
||||
|
||||
@ -1709,15 +1645,12 @@ private:
|
||||
|
||||
void movslq(Register dst, Address src);
|
||||
void movslq(Register dst, Register src);
|
||||
#endif
|
||||
|
||||
void movswl(Register dst, Address src);
|
||||
void movswl(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void movswq(Register dst, Address src);
|
||||
void movswq(Register dst, Register src);
|
||||
#endif
|
||||
|
||||
void movups(XMMRegister dst, Address src);
|
||||
void vmovups(XMMRegister dst, Address src, int vector_len);
|
||||
@ -1731,18 +1664,14 @@ private:
|
||||
void movzbl(Register dst, Address src);
|
||||
void movzbl(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void movzbq(Register dst, Address src);
|
||||
void movzbq(Register dst, Register src);
|
||||
#endif
|
||||
|
||||
void movzwl(Register dst, Address src);
|
||||
void movzwl(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void movzwq(Register dst, Address src);
|
||||
void movzwq(Register dst, Register src);
|
||||
#endif
|
||||
|
||||
// Unsigned multiply with RAX destination register
|
||||
void mull(Address src);
|
||||
@ -1750,13 +1679,11 @@ private:
|
||||
void mull(Register src);
|
||||
void emull(Register src, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void mulq(Address src);
|
||||
void emulq(Address src, bool no_flags);
|
||||
void mulq(Register src);
|
||||
void emulq(Register src, bool no_flags);
|
||||
void mulxq(Register dst1, Register dst2, Register src);
|
||||
#endif
|
||||
|
||||
// Multiply Scalar Double-Precision Floating-Point Values
|
||||
void mulsd(XMMRegister dst, Address src);
|
||||
@ -1771,26 +1698,22 @@ private:
|
||||
void negl(Address dst);
|
||||
void enegl(Register dst, Address src, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void negq(Register dst);
|
||||
void enegq(Register dst, Register src, bool no_flags);
|
||||
void negq(Address dst);
|
||||
void enegq(Register dst, Address src, bool no_flags);
|
||||
#endif
|
||||
|
||||
void nop(uint i = 1);
|
||||
|
||||
void notl(Register dst);
|
||||
void enotl(Register dst, Register src);
|
||||
|
||||
#ifdef _LP64
|
||||
void notq(Register dst);
|
||||
void enotq(Register dst, Register src);
|
||||
|
||||
void btsq(Address dst, int imm8);
|
||||
void btrq(Address dst, int imm8);
|
||||
void btq(Register src, int imm8);
|
||||
#endif
|
||||
void btq(Register dst, Register src);
|
||||
|
||||
void eorw(Register dst, Register src1, Register src2, bool no_flags);
|
||||
@ -2009,14 +1932,8 @@ private:
|
||||
// Multiply add accumulate
|
||||
void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
|
||||
|
||||
#ifndef _LP64 // no 32bit push/pop on amd64
|
||||
void popl(Address dst);
|
||||
#endif
|
||||
|
||||
#ifdef _LP64
|
||||
void popq(Address dst);
|
||||
void popq(Register dst);
|
||||
#endif
|
||||
|
||||
void popcntl(Register dst, Address src);
|
||||
void epopcntl(Register dst, Address src, bool no_flags);
|
||||
@ -2028,12 +1945,10 @@ private:
|
||||
void evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
|
||||
void evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
|
||||
|
||||
#ifdef _LP64
|
||||
void popcntq(Register dst, Address src);
|
||||
void epopcntq(Register dst, Address src, bool no_flags);
|
||||
void popcntq(Register dst, Register src);
|
||||
void epopcntq(Register dst, Register src, bool no_flags);
|
||||
#endif
|
||||
|
||||
// Prefetches (SSE, SSE2, 3DNOW only)
|
||||
|
||||
@ -2125,10 +2040,6 @@ private:
|
||||
// Vector sum of absolute difference.
|
||||
void vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
|
||||
|
||||
#ifndef _LP64 // no 32bit push/pop on amd64
|
||||
void pushl(Address src);
|
||||
#endif
|
||||
|
||||
void pushq(Address src);
|
||||
|
||||
void rcll(Register dst, int imm8);
|
||||
@ -2160,7 +2071,6 @@ private:
|
||||
void rorl(Register dst, int imm8);
|
||||
void erorl(Register dst, Register src, int imm8, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void rolq(Register dst);
|
||||
void erolq(Register dst, Register src, bool no_flags);
|
||||
void rolq(Register dst, int imm8);
|
||||
@ -2173,9 +2083,6 @@ private:
|
||||
void rorxl(Register dst, Address src, int imm8);
|
||||
void rorxq(Register dst, Register src, int imm8);
|
||||
void rorxq(Register dst, Address src, int imm8);
|
||||
#endif
|
||||
|
||||
void sahf();
|
||||
|
||||
void sall(Register dst, int imm8);
|
||||
void esall(Register dst, Register src, int imm8, bool no_flags);
|
||||
@ -2195,7 +2102,6 @@ private:
|
||||
void sarl(Register dst);
|
||||
void esarl(Register dst, Register src, bool no_flags);
|
||||
|
||||
#ifdef _LP64
|
||||
void salq(Register dst, int imm8);
|
||||
void esalq(Register dst, Register src, int imm8, bool no_flags);
|
||||
void salq(Register dst);
|
||||
@ -2213,7 +2119,6 @@ private:
|
||||
void esarq(Register dst, Register src, int imm8, bool no_flags);
|
||||
void sarq(Register dst);
|
||||
void esarq(Register dst, Register src, bool no_flags);
|
||||
#endif
|
||||
|
||||
void sbbl(Address dst, int32_t imm32);
|
||||
void sbbl(Register dst, int32_t imm32);
|
||||
@ -2254,12 +2159,10 @@ private:
|
||||
void eshrdl(Register dst, Register src1, Register src2, bool no_flags);
|
||||
void shrdl(Register dst, Register src, int8_t imm8);
|
||||
void eshrdl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
|
||||
#ifdef _LP64
|
||||
void shldq(Register dst, Register src, int8_t imm8);
|
||||
void eshldq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
|
||||
void shrdq(Register dst, Register src, int8_t imm8);
|
||||
void eshrdq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags);
|
||||
#endif
|
||||
|
||||
void shll(Register dst, int imm8);
|
||||
void eshll(Register dst, Register src, int imm8, bool no_flags);
|
||||
|
||||
@ -25,58 +25,4 @@
|
||||
#ifndef CPU_X86_ASSEMBLER_X86_INLINE_HPP
|
||||
#define CPU_X86_ASSEMBLER_X86_INLINE_HPP
|
||||
|
||||
#include "asm/assembler.inline.hpp"
|
||||
#include "asm/codeBuffer.hpp"
|
||||
#include "code/codeCache.hpp"
|
||||
|
||||
#ifndef _LP64
|
||||
inline int Assembler::prefix_and_encode(int reg_enc, bool byteinst, bool is_map1)
|
||||
{
|
||||
int opc_prefix = is_map1 ? 0x0F00 : 0;
|
||||
return opc_prefix | reg_enc;
|
||||
}
|
||||
|
||||
inline int Assembler::prefixq_and_encode(int reg_enc, bool is_map1) {
|
||||
int opc_prefix = is_map1 ? 0xF00 : 0;
|
||||
return opc_prefix | reg_enc;
|
||||
}
|
||||
|
||||
inline int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte, bool is_map1) {
|
||||
int opc_prefix = is_map1 ? 0xF00 : 0;
|
||||
return opc_prefix | (dst_enc << 3 | src_enc);
|
||||
}
|
||||
|
||||
inline int Assembler::prefixq_and_encode(int dst_enc, int src_enc, bool is_map1) {
|
||||
int opc_prefix = is_map1 ? 0xF00 : 0;
|
||||
return opc_prefix | dst_enc << 3 | src_enc;
|
||||
}
|
||||
|
||||
inline void Assembler::prefix(Register reg) {}
|
||||
inline void Assembler::prefix(Register dst, Register src, Prefix p) {}
|
||||
inline void Assembler::prefix(Register dst, Address adr, Prefix p) {}
|
||||
|
||||
inline void Assembler::prefix(Address adr, bool is_map1) {
|
||||
if (is_map1) {
|
||||
emit_int8(0x0F);
|
||||
}
|
||||
}
|
||||
|
||||
inline void Assembler::prefixq(Address adr) {}
|
||||
|
||||
inline void Assembler::prefix(Address adr, Register reg, bool byteinst, bool is_map1) {
|
||||
if (is_map1) {
|
||||
emit_int8(0x0F);
|
||||
}
|
||||
}
|
||||
inline void Assembler::prefixq(Address adr, Register reg, bool is_map1) {
|
||||
if (is_map1) {
|
||||
emit_int8(0x0F);
|
||||
}
|
||||
}
|
||||
|
||||
inline void Assembler::prefix(Address adr, XMMRegister reg) {}
|
||||
inline void Assembler::prefixq(Address adr, XMMRegister reg) {}
|
||||
|
||||
#endif // _LP64
|
||||
|
||||
#endif // CPU_X86_ASSEMBLER_X86_INLINE_HPP
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -140,10 +140,10 @@ class MacroAssembler: public Assembler {
|
||||
|
||||
// Support for inc/dec with optimal instruction selection depending on value
|
||||
|
||||
void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
|
||||
void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
|
||||
void increment(Address dst, int value = 1) { LP64_ONLY(incrementq(dst, value)) NOT_LP64(incrementl(dst, value)) ; }
|
||||
void decrement(Address dst, int value = 1) { LP64_ONLY(decrementq(dst, value)) NOT_LP64(decrementl(dst, value)) ; }
|
||||
void increment(Register reg, int value = 1) { incrementq(reg, value); }
|
||||
void decrement(Register reg, int value = 1) { decrementq(reg, value); }
|
||||
void increment(Address dst, int value = 1) { incrementq(dst, value); }
|
||||
void decrement(Address dst, int value = 1) { decrementq(dst, value); }
|
||||
|
||||
void decrementl(Address dst, int value = 1);
|
||||
void decrementl(Register reg, int value = 1);
|
||||
@ -221,7 +221,6 @@ class MacroAssembler: public Assembler {
|
||||
// Normally, JavaThread pointer is available in r15_thread, use that where possible.
|
||||
void get_thread_slow(Register thread);
|
||||
|
||||
#ifdef _LP64
|
||||
// Support for argument shuffling
|
||||
|
||||
// bias in bytes
|
||||
@ -237,7 +236,6 @@ class MacroAssembler: public Assembler {
|
||||
VMRegPair dst,
|
||||
bool is_receiver,
|
||||
int* receiver_offset);
|
||||
#endif // _LP64
|
||||
|
||||
// Support for VM calls
|
||||
//
|
||||
@ -351,9 +349,7 @@ class MacroAssembler: public Assembler {
|
||||
void load_method_holder(Register holder, Register method);
|
||||
|
||||
// oop manipulations
|
||||
#ifdef _LP64
|
||||
void load_narrow_klass_compact(Register dst, Register src);
|
||||
#endif
|
||||
void load_klass(Register dst, Register src, Register tmp);
|
||||
void store_klass(Register dst, Register src, Register tmp);
|
||||
|
||||
@ -379,7 +375,6 @@ class MacroAssembler: public Assembler {
|
||||
// stored using routines that take a jobject.
|
||||
void store_heap_oop_null(Address dst);
|
||||
|
||||
#ifdef _LP64
|
||||
void store_klass_gap(Register dst, Register src);
|
||||
|
||||
// This dummy is to prevent a call to store_heap_oop from
|
||||
@ -414,8 +409,6 @@ class MacroAssembler: public Assembler {
|
||||
|
||||
DEBUG_ONLY(void verify_heapbase(const char* msg);)
|
||||
|
||||
#endif // _LP64
|
||||
|
||||
// Int division/remainder for Java
|
||||
// (as idivl, but checks for special case as described in JVM spec.)
|
||||
// returns idivl instruction offset for implicit exception handling
|
||||
@ -582,7 +575,6 @@ public:
|
||||
Label* L_failure,
|
||||
bool set_cond_codes = false);
|
||||
|
||||
#ifdef _LP64
|
||||
// The 64-bit version, which may do a hashed subclass lookup.
|
||||
void check_klass_subtype_slow_path(Register sub_klass,
|
||||
Register super_klass,
|
||||
@ -592,7 +584,6 @@ public:
|
||||
Register temp4_reg,
|
||||
Label* L_success,
|
||||
Label* L_failure);
|
||||
#endif
|
||||
|
||||
// Three parts of a hashed subclass lookup: a simple linear search,
|
||||
// a table lookup, and a fallback that does linear probing in the
|
||||
@ -629,7 +620,6 @@ public:
|
||||
Register result,
|
||||
u1 super_klass_slot);
|
||||
|
||||
#ifdef _LP64
|
||||
using Assembler::salq;
|
||||
void salq(Register dest, Register count);
|
||||
using Assembler::rorq;
|
||||
@ -657,7 +647,6 @@ public:
|
||||
Register temp1,
|
||||
Register temp2,
|
||||
Register temp3);
|
||||
#endif
|
||||
|
||||
void repne_scanq(Register addr, Register value, Register count, Register limit,
|
||||
Label* L_success,
|
||||
@ -766,10 +755,10 @@ public:
|
||||
// Arithmetics
|
||||
|
||||
|
||||
void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
|
||||
void addptr(Address dst, int32_t src) { addq(dst, src); }
|
||||
void addptr(Address dst, Register src);
|
||||
|
||||
void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
|
||||
void addptr(Register dst, Address src) { addq(dst, src); }
|
||||
void addptr(Register dst, int32_t src);
|
||||
void addptr(Register dst, Register src);
|
||||
void addptr(Register dst, RegisterOrConstant src) {
|
||||
@ -778,12 +767,10 @@ public:
|
||||
}
|
||||
|
||||
void andptr(Register dst, int32_t src);
|
||||
void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
|
||||
void andptr(Register src1, Register src2) { andq(src1, src2); }
|
||||
|
||||
#ifdef _LP64
|
||||
using Assembler::andq;
|
||||
void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
|
||||
#endif
|
||||
|
||||
void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
|
||||
|
||||
@ -796,12 +783,6 @@ public:
|
||||
|
||||
void cmp32(Register src1, Address src2);
|
||||
|
||||
#ifndef _LP64
|
||||
void cmpklass(Address dst, Metadata* obj);
|
||||
void cmpklass(Register dst, Metadata* obj);
|
||||
void cmpoop(Address dst, jobject obj);
|
||||
#endif // _LP64
|
||||
|
||||
void cmpoop(Register src1, Register src2);
|
||||
void cmpoop(Register src1, Address src2);
|
||||
void cmpoop(Register dst, jobject obj, Register rscratch);
|
||||
@ -811,12 +792,11 @@ public:
|
||||
|
||||
void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
|
||||
|
||||
void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
||||
void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
||||
// void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
||||
void cmpptr(Register src1, Register src2) { cmpq(src1, src2); }
|
||||
void cmpptr(Register src1, Address src2) { cmpq(src1, src2); }
|
||||
|
||||
void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
||||
void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
|
||||
void cmpptr(Register src1, int32_t src2) { cmpq(src1, src2); }
|
||||
void cmpptr(Address src1, int32_t src2) { cmpq(src1, src2); }
|
||||
|
||||
// cmp64 to avoild hiding cmpq
|
||||
void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
|
||||
@ -825,26 +805,26 @@ public:
|
||||
|
||||
void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
|
||||
|
||||
void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
|
||||
void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
|
||||
void imulptr(Register dst, Register src) { imulq(dst, src); }
|
||||
void imulptr(Register dst, Register src, int imm32) { imulq(dst, src, imm32); }
|
||||
|
||||
|
||||
void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
|
||||
void negptr(Register dst) { negq(dst); }
|
||||
|
||||
void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
|
||||
void notptr(Register dst) { notq(dst); }
|
||||
|
||||
void shlptr(Register dst, int32_t shift);
|
||||
void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
|
||||
void shlptr(Register dst) { shlq(dst); }
|
||||
|
||||
void shrptr(Register dst, int32_t shift);
|
||||
void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
|
||||
void shrptr(Register dst) { shrq(dst); }
|
||||
|
||||
void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
|
||||
void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
|
||||
void sarptr(Register dst) { sarq(dst); }
|
||||
void sarptr(Register dst, int32_t src) { sarq(dst, src); }
|
||||
|
||||
void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
|
||||
void subptr(Address dst, int32_t src) { subq(dst, src); }
|
||||
|
||||
void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
|
||||
void subptr(Register dst, Address src) { subq(dst, src); }
|
||||
void subptr(Register dst, int32_t src);
|
||||
// Force generation of a 4 byte immediate value even if it fits into 8bit
|
||||
void subptr_imm32(Register dst, int32_t src);
|
||||
@ -854,13 +834,13 @@ public:
|
||||
else subptr(dst, src.as_register());
|
||||
}
|
||||
|
||||
void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
|
||||
void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
|
||||
void sbbptr(Address dst, int32_t src) { sbbq(dst, src); }
|
||||
void sbbptr(Register dst, int32_t src) { sbbq(dst, src); }
|
||||
|
||||
void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
|
||||
void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
|
||||
void xchgptr(Register src1, Register src2) { xchgq(src1, src2); }
|
||||
void xchgptr(Register src1, Address src2) { xchgq(src1, src2); }
|
||||
|
||||
void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
|
||||
void xaddptr(Address src1, Register src2) { xaddq(src1, src2); }
|
||||
|
||||
|
||||
|
||||
@ -870,12 +850,10 @@ public:
|
||||
// Unconditional atomic increment.
|
||||
void atomic_incl(Address counter_addr);
|
||||
void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
|
||||
#ifdef _LP64
|
||||
void atomic_incq(Address counter_addr);
|
||||
void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
|
||||
#endif
|
||||
void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { LP64_ONLY(atomic_incq(counter_addr, rscratch)) NOT_LP64(atomic_incl(counter_addr, rscratch)) ; }
|
||||
void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
|
||||
void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { atomic_incq(counter_addr, rscratch); }
|
||||
void atomic_incptr(Address counter_addr) { atomic_incq(counter_addr); }
|
||||
|
||||
using Assembler::lea;
|
||||
void lea(Register dst, AddressLiteral adr);
|
||||
@ -893,18 +871,18 @@ public:
|
||||
void testq(Address dst, int32_t imm32);
|
||||
void testq(Register dst, int32_t imm32);
|
||||
|
||||
void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
||||
void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
||||
void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
|
||||
void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
|
||||
void orptr(Register dst, Address src) { orq(dst, src); }
|
||||
void orptr(Register dst, Register src) { orq(dst, src); }
|
||||
void orptr(Register dst, int32_t src) { orq(dst, src); }
|
||||
void orptr(Address dst, int32_t imm32) { orq(dst, imm32); }
|
||||
|
||||
void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
|
||||
void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
|
||||
void testptr(Address src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
|
||||
void testptr(Register src, int32_t imm32) { testq(src, imm32); }
|
||||
void testptr(Register src1, Address src2) { testq(src1, src2); }
|
||||
void testptr(Address src, int32_t imm32) { testq(src, imm32); }
|
||||
void testptr(Register src1, Register src2);
|
||||
|
||||
void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
|
||||
void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
|
||||
void xorptr(Register dst, Register src) { xorq(dst, src); }
|
||||
void xorptr(Register dst, Address src) { xorq(dst, src); }
|
||||
|
||||
// Calls
|
||||
|
||||
@ -1033,7 +1011,6 @@ public:
|
||||
void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
|
||||
void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
|
||||
|
||||
#ifdef _LP64
|
||||
private:
|
||||
void sha256_AVX2_one_round_compute(
|
||||
Register reg_old_h,
|
||||
@ -1083,7 +1060,6 @@ public:
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
|
||||
XMMRegister shuf_mask);
|
||||
void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
|
||||
#endif // _LP64
|
||||
|
||||
void fast_md5(Register buf, Address state, Address ofs, Address limit,
|
||||
bool multi_block);
|
||||
@ -1093,68 +1069,15 @@ public:
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp,
|
||||
bool multi_block);
|
||||
|
||||
#ifdef _LP64
|
||||
void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
|
||||
XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp,
|
||||
bool multi_block, XMMRegister shuf_mask);
|
||||
#else
|
||||
void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
|
||||
XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp,
|
||||
bool multi_block);
|
||||
#endif
|
||||
|
||||
void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rcx, Register rdx, Register tmp);
|
||||
|
||||
#ifndef _LP64
|
||||
private:
|
||||
// Initialized in macroAssembler_x86_constants.cpp
|
||||
static address ONES;
|
||||
static address L_2IL0FLOATPACKET_0;
|
||||
static address PI4_INV;
|
||||
static address PI4X3;
|
||||
static address PI4X4;
|
||||
|
||||
public:
|
||||
void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rcx, Register rdx, Register tmp1);
|
||||
|
||||
void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rcx, Register rdx, Register tmp);
|
||||
|
||||
void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
|
||||
XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
|
||||
Register rdx, Register tmp);
|
||||
|
||||
void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rbx, Register rdx);
|
||||
|
||||
void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rcx, Register rdx, Register tmp);
|
||||
|
||||
void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
|
||||
Register edx, Register ebx, Register esi, Register edi,
|
||||
Register ebp, Register esp);
|
||||
|
||||
void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
|
||||
Register esi, Register edi, Register ebp, Register esp);
|
||||
|
||||
void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
|
||||
Register edx, Register ebx, Register esi, Register edi,
|
||||
Register ebp, Register esp);
|
||||
|
||||
void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
|
||||
XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
|
||||
Register rax, Register rcx, Register rdx, Register tmp);
|
||||
#endif // !_LP64
|
||||
|
||||
private:
|
||||
|
||||
// these are private because users should be doing movflt/movdbl
|
||||
@ -1921,8 +1844,8 @@ public:
|
||||
|
||||
void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
|
||||
|
||||
void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
|
||||
void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
|
||||
void cmovptr(Condition cc, Register dst, Address src) { cmovq(cc, dst, src); }
|
||||
void cmovptr(Condition cc, Register dst, Register src) { cmovq(cc, dst, src); }
|
||||
|
||||
void movoop(Register dst, jobject obj);
|
||||
void movoop(Address dst, jobject obj, Register rscratch);
|
||||
@ -1961,15 +1884,15 @@ public:
|
||||
// Can push value or effective address
|
||||
void pushptr(AddressLiteral src, Register rscratch);
|
||||
|
||||
void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
|
||||
void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
|
||||
void pushptr(Address src) { pushq(src); }
|
||||
void popptr(Address src) { popq(src); }
|
||||
|
||||
void pushoop(jobject obj, Register rscratch);
|
||||
void pushklass(Metadata* obj, Register rscratch);
|
||||
|
||||
// sign extend as need a l to ptr sized element
|
||||
void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
|
||||
void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
|
||||
void movl2ptr(Register dst, Address src) { movslq(dst, src); }
|
||||
void movl2ptr(Register dst, Register src) { movslq(dst, src); }
|
||||
|
||||
|
||||
public:
|
||||
@ -1992,7 +1915,6 @@ public:
|
||||
XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
|
||||
XMMRegister tmp4, Register tmp5, Register result, bool ascii);
|
||||
|
||||
#ifdef _LP64
|
||||
void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
|
||||
void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
|
||||
Register y, Register y_idx, Register z,
|
||||
@ -2033,32 +1955,22 @@ public:
|
||||
void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
|
||||
Register result, Register tmp1, Register tmp2,
|
||||
XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
|
||||
#endif
|
||||
|
||||
// CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
|
||||
void update_byte_crc32(Register crc, Register val, Register table);
|
||||
void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
|
||||
|
||||
|
||||
#ifdef _LP64
|
||||
void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
|
||||
void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
|
||||
Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
|
||||
Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
|
||||
#endif // _LP64
|
||||
|
||||
// CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
|
||||
// Note on a naming convention:
|
||||
// Prefix w = register only used on a Westmere+ architecture
|
||||
// Prefix n = register only used on a Nehalem architecture
|
||||
#ifdef _LP64
|
||||
void crc32c_ipl_alg4(Register in_out, uint32_t n,
|
||||
Register tmp1, Register tmp2, Register tmp3);
|
||||
#else
|
||||
void crc32c_ipl_alg4(Register in_out, uint32_t n,
|
||||
Register tmp1, Register tmp2, Register tmp3,
|
||||
XMMRegister xtmp1, XMMRegister xtmp2);
|
||||
#endif
|
||||
void crc32c_pclmulqdq(XMMRegister w_xtmp1,
|
||||
Register in_out,
|
||||
uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
|
||||
@ -2083,10 +1995,8 @@ public:
|
||||
// Fold 128-bit data chunk
|
||||
void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
|
||||
void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
|
||||
#ifdef _LP64
|
||||
// Fold 512-bit data chunk
|
||||
void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
|
||||
#endif // _LP64
|
||||
// Fold 8-bit data
|
||||
void fold_8bit_crc32(Register crc, Register table, Register tmp);
|
||||
void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
|
||||
@ -2120,7 +2030,6 @@ public:
|
||||
|
||||
void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
|
||||
|
||||
#ifdef _LP64
|
||||
void convert_f2i(Register dst, XMMRegister src);
|
||||
void convert_d2i(Register dst, XMMRegister src);
|
||||
void convert_f2l(Register dst, XMMRegister src);
|
||||
@ -2135,7 +2044,6 @@ public:
|
||||
void generate_fill_avx3(BasicType type, Register to, Register value,
|
||||
Register count, Register rtmp, XMMRegister xtmp);
|
||||
#endif // COMPILER2_OR_JVMCI
|
||||
#endif // _LP64
|
||||
|
||||
void vallones(XMMRegister dst, int vector_len);
|
||||
|
||||
@ -2144,11 +2052,9 @@ public:
|
||||
void lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow);
|
||||
void lightweight_unlock(Register obj, Register reg_rax, Register tmp, Label& slow);
|
||||
|
||||
#ifdef _LP64
|
||||
void save_legacy_gprs();
|
||||
void restore_legacy_gprs();
|
||||
void setcc(Assembler::Condition comparison, Register dst);
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif // CPU_X86_MACROASSEMBLER_X86_HPP
|
||||
|
||||
@ -235,17 +235,10 @@ void MacroAssembler::fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1,
|
||||
// and state0 and state1 can never use xmm0 register.
|
||||
// ofs and limit are used for multi-block byte array.
|
||||
// int com.sun.security.provider.DigestBase.implCompressMultiBlock(byte[] b, int ofs, int limit)
|
||||
#ifdef _LP64
|
||||
void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
|
||||
XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp,
|
||||
bool multi_block, XMMRegister shuf_mask) {
|
||||
#else
|
||||
void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
|
||||
XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
|
||||
Register buf, Register state, Register ofs, Register limit, Register rsp,
|
||||
bool multi_block) {
|
||||
#endif
|
||||
Label done_hash, loop0;
|
||||
|
||||
address K256 = StubRoutines::x86::k256_addr();
|
||||
@ -260,9 +253,7 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
palignr(state0, state1, 8);
|
||||
pblendw(state1, msgtmp4, 0xF0);
|
||||
|
||||
#ifdef _LP64
|
||||
movdqu(shuf_mask, ExternalAddress(pshuffle_byte_flip_mask));
|
||||
#endif
|
||||
lea(rax, ExternalAddress(K256));
|
||||
|
||||
bind(loop0);
|
||||
@ -271,11 +262,7 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
|
||||
// Rounds 0-3
|
||||
movdqu(msg, Address(buf, 0));
|
||||
#ifdef _LP64
|
||||
pshufb(msg, shuf_mask);
|
||||
#else
|
||||
pshufb(msg, ExternalAddress(pshuffle_byte_flip_mask));
|
||||
#endif
|
||||
movdqa(msgtmp0, msg);
|
||||
paddd(msg, Address(rax, 0));
|
||||
sha256rnds2(state1, state0);
|
||||
@ -284,11 +271,7 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
|
||||
// Rounds 4-7
|
||||
movdqu(msg, Address(buf, 16));
|
||||
#ifdef _LP64
|
||||
pshufb(msg, shuf_mask);
|
||||
#else
|
||||
pshufb(msg, ExternalAddress(pshuffle_byte_flip_mask));
|
||||
#endif
|
||||
movdqa(msgtmp1, msg);
|
||||
paddd(msg, Address(rax, 16));
|
||||
sha256rnds2(state1, state0);
|
||||
@ -298,11 +281,7 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
|
||||
// Rounds 8-11
|
||||
movdqu(msg, Address(buf, 32));
|
||||
#ifdef _LP64
|
||||
pshufb(msg, shuf_mask);
|
||||
#else
|
||||
pshufb(msg, ExternalAddress(pshuffle_byte_flip_mask));
|
||||
#endif
|
||||
movdqa(msgtmp2, msg);
|
||||
paddd(msg, Address(rax, 32));
|
||||
sha256rnds2(state1, state0);
|
||||
@ -312,11 +291,7 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
|
||||
// Rounds 12-15
|
||||
movdqu(msg, Address(buf, 48));
|
||||
#ifdef _LP64
|
||||
pshufb(msg, shuf_mask);
|
||||
#else
|
||||
pshufb(msg, ExternalAddress(pshuffle_byte_flip_mask));
|
||||
#endif
|
||||
movdqa(msgtmp3, msg);
|
||||
paddd(msg, Address(rax, 48));
|
||||
sha256rnds2(state1, state0);
|
||||
@ -491,7 +466,6 @@ void MacroAssembler::fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegiste
|
||||
|
||||
}
|
||||
|
||||
#ifdef _LP64
|
||||
/*
|
||||
The algorithm below is based on Intel publication:
|
||||
"Fast SHA-256 Implementations on Intel(R) Architecture Processors" by Jim Guilford, Kirk Yap and Vinodh Gopal.
|
||||
@ -1696,5 +1670,3 @@ void MacroAssembler::sha512_update_ni_x1(Register arg_hash, Register arg_msg, Re
|
||||
|
||||
bind(done_hash);
|
||||
}
|
||||
|
||||
#endif //#ifdef _LP64
|
||||
|
||||
@ -30,6 +30,7 @@
|
||||
#include "asm/assembler.hpp"
|
||||
#include "asm/assembler.inline.hpp"
|
||||
#include "asm/macroAssembler.hpp"
|
||||
#include "code/codeCache.hpp"
|
||||
#include "memory/resourceArea.hpp"
|
||||
|
||||
#include "unittest.hpp"
|
||||
Loading…
x
Reference in New Issue
Block a user