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8042309: Some bugfixes for the ppc64 port
Reviewed-by: kvn
This commit is contained in:
Goetz Lindenmaier
parent
142ed91465
commit
9d479b16de
@ -1,3 +1,4 @@
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/*
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* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
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* Copyright 2012, 2014 SAP AG. All rights reserved.
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@ -403,7 +404,7 @@ void CppInterpreterGenerator::generate_compute_interpreter_state(Label& stack_ov
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BLOCK_COMMENT("compute_interpreter_state {");
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// access_flags = method->access_flags();
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// TODO: PPC port: assert(4 == methodOopDesc::sz_access_flags(), "unexpected field size");
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// TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size");
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__ lwa(access_flags, method_(access_flags));
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// parameter_count = method->constMethod->size_of_parameters();
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@ -1053,7 +1054,7 @@ address CppInterpreterGenerator::generate_native_entry(void) {
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assert(access_flags->is_nonvolatile(),
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"access_flags must be in a non-volatile register");
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// Type check.
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// TODO: PPC port: assert(4 == methodOopDesc::sz_access_flags(), "unexpected field size");
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// TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size");
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__ lwz(access_flags, method_(access_flags));
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// We don't want to reload R19_method and access_flags after calls
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@ -1836,7 +1837,7 @@ address CppInterpreterGenerator::generate_normal_entry(void) {
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// Interpreter state fields.
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const Register msg = R24_tmp4;
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// MethodOop fields.
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// Method fields.
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const Register parameter_count = R25_tmp5;
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const Register result_index = R26_tmp6;
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@ -2021,7 +2022,7 @@ address CppInterpreterGenerator::generate_normal_entry(void) {
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__ add(R17_tos, R17_tos, parameter_count);
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// Result stub address array index
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// TODO: PPC port: assert(4 == methodOopDesc::sz_result_index(), "unexpected field size");
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// TODO: PPC port: assert(4 == sizeof(AccessFlags), "unexpected field size");
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__ lwa(result_index, method_(result_index));
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__ li(msg, BytecodeInterpreter::method_resume);
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@ -2707,7 +2708,7 @@ address CppInterpreterGenerator::generate_normal_entry(void) {
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__ ld(R3_ARG1, state_(_result._osr._osr_buf));
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__ mtctr(R12_scratch2);
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// Load method oop, gc may move it during execution of osr'd method.
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// Load method, gc may move it during execution of osr'd method.
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__ ld(R22_tmp2, state_(_method));
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// Load message 'call_method'.
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__ li(R23_tmp3, BytecodeInterpreter::call_method);
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@ -26,6 +26,8 @@
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#ifndef CPU_PPC_VM_FRAME_PPC_INLINE_HPP
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#define CPU_PPC_VM_FRAME_PPC_INLINE_HPP
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#include "code/codeCache.hpp"
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// Inline functions for ppc64 frames:
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// Find codeblob and set deopt_state.
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@ -26,7 +26,7 @@
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#ifndef CPU_PPC_VM_INTERP_MASM_PPC_64_HPP
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#define CPU_PPC_VM_INTERP_MASM_PPC_64_HPP
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#include "assembler_ppc.inline.hpp"
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#include "asm/macroAssembler.hpp"
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#include "interpreter/invocationCounter.hpp"
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// This file specializes the assembler with interpreter-specific macros.
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@ -24,6 +24,7 @@
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*/
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#include "precompiled.hpp"
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#include "asm/assembler.inline.hpp"
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#include "interpreter/interpreter.hpp"
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#include "interpreter/interpreterRuntime.hpp"
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#include "memory/allocation.inline.hpp"
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@ -139,32 +139,16 @@ address AbstractInterpreterGenerator::generate_slow_signature_handler() {
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// Signature is in R3_RET. Signature is callee saved.
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__ mr(signature, R3_RET);
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// Reload method, it may have moved.
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#ifdef CC_INTERP
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__ ld(R19_method, state_(_method));
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#else
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__ ld(R19_method, 0, target_sp);
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__ ld(R19_method, _ijava_state_neg(method), R19_method);
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#endif
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// Get the result handler.
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__ call_VM_leaf(CAST_FROM_FN_PTR(address, InterpreterRuntime::get_result_handler), R16_thread, R19_method);
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// Reload method, it may have moved.
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#ifdef CC_INTERP
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__ ld(R19_method, state_(_method));
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#else
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__ ld(R19_method, 0, target_sp);
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__ ld(R19_method, _ijava_state_neg(method), R19_method);
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#endif
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{
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Label L;
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// test if static
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// _access_flags._flags must be at offset 0.
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// TODO PPC port: requires change in shared code.
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//assert(in_bytes(AccessFlags::flags_offset()) == 0,
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// "MethodOopDesc._access_flags == MethodOopDesc._access_flags._flags");
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// "MethodDesc._access_flags == MethodDesc._access_flags._flags");
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// _access_flags must be a 32 bit value.
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assert(sizeof(AccessFlags) == 4, "wrong size");
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__ lwa(R11_scratch1/*access_flags*/, method_(access_flags));
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@ -32,7 +32,7 @@
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address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
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// we don't have fast jni accessors.
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// We don't have fast jni accessors.
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return (address) -1;
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}
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@ -57,12 +57,12 @@ address JNI_FastGetField::generate_fast_get_int_field() {
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}
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address JNI_FastGetField::generate_fast_get_long_field() {
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// we don't have fast jni accessors.
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// We don't have fast jni accessors.
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return (address) -1;
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}
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address JNI_FastGetField::generate_fast_get_float_field0(BasicType type) {
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// e don't have fast jni accessors.
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// We don't have fast jni accessors.
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return (address) -1;
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}
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@ -898,7 +898,7 @@ source_hpp %{
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// To keep related declarations/definitions/uses close together,
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// we switch between source %{ }% and source_hpp %{ }% freely as needed.
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// Returns true if Node n is followed by a MemBar node that
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// Returns true if Node n is followed by a MemBar node that
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// will do an acquire. If so, this node must not do the acquire
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// operation.
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bool followed_by_acquire(const Node *n);
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@ -908,7 +908,7 @@ source %{
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// Optimize load-acquire.
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//
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// Check if acquire is unnecessary due to following operation that does
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// Check if acquire is unnecessary due to following operation that does
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// acquire anyways.
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// Walk the pattern:
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//
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@ -919,12 +919,12 @@ source %{
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// Proj(ctrl) Proj(mem)
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// | |
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// MemBarRelease/Volatile
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//
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//
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bool followed_by_acquire(const Node *load) {
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assert(load->is_Load(), "So far implemented only for loads.");
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// Find MemBarAcquire.
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const Node *mba = NULL;
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const Node *mba = NULL;
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for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
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const Node *out = load->fast_out(i);
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if (out->Opcode() == Op_MemBarAcquire) {
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@ -937,7 +937,7 @@ bool followed_by_acquire(const Node *load) {
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// Find following MemBar node.
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//
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// The following node must be reachable by control AND memory
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// The following node must be reachable by control AND memory
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// edge to assure no other operations are in between the two nodes.
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//
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// So first get the Proj node, mem_proj, to use it to iterate forward.
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@ -1135,6 +1135,7 @@ class CallStubImpl {
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public:
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// Emit call stub, compiled java to interpreter.
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static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
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// Size of call trampoline stub.
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@ -2755,7 +2756,7 @@ encode %{
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// inputs for new nodes
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m1->add_req(NULL, n_toc);
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m2->add_req(NULL, m1);
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// operands for new nodes
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m1->_opnds[0] = new (C) iRegPdstOper(); // dst
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m1->_opnds[1] = op_src; // src
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@ -2763,29 +2764,29 @@ encode %{
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m2->_opnds[0] = new (C) iRegPdstOper(); // dst
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m2->_opnds[1] = op_src; // src
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m2->_opnds[2] = new (C) iRegLdstOper(); // base
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// Initialize ins_attrib TOC fields.
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m1->_const_toc_offset = -1;
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m2->_const_toc_offset_hi_node = m1;
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// Register allocation for new nodes.
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ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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nodes->push(m1);
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nodes->push(m2);
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assert(m2->bottom_type()->isa_ptr(), "must be ptr");
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} else {
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loadConPNode *m2 = new (C) loadConPNode();
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// inputs for new nodes
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m2->add_req(NULL, n_toc);
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// operands for new nodes
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m2->_opnds[0] = new (C) iRegPdstOper(); // dst
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m2->_opnds[1] = op_src; // src
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m2->_opnds[2] = new (C) iRegPdstOper(); // toc
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// Register allocation for new nodes.
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ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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@ -2977,17 +2978,17 @@ encode %{
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n_sub_base->_opnds[1] = op_crx;
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n_sub_base->_opnds[2] = op_src;
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n_sub_base->_bottom_type = _bottom_type;
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n_shift->add_req(n_region, n_sub_base);
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n_shift->_opnds[0] = op_dst;
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n_shift->_opnds[1] = op_dst;
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n_shift->_bottom_type = _bottom_type;
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ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
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ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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nodes->push(n_move);
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nodes->push(n_compare);
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nodes->push(n_sub_base);
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@ -3064,20 +3065,20 @@ encode %{
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} else {
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// before Power 7
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cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
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n_add_base->add_req(n_region, n_compare, n_shift);
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n_add_base->_opnds[0] = op_dst;
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n_add_base->_opnds[1] = op_crx;
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n_add_base->_opnds[2] = op_dst;
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n_add_base->_bottom_type = _bottom_type;
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assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
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ra_->set_oop(n_add_base, true);
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ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
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ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
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nodes->push(n_compare);
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nodes->push(n_shift);
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nodes->push(n_add_base);
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@ -3634,11 +3635,11 @@ encode %{
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// Req...
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for (uint i = 0; i < req(); ++i) {
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// The expanded node does not need toc any more.
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// Add the inline cache constant here instead. This expresses the
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// Add the inline cache constant here instead. This expresses the
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// register of the inline cache must be live at the call.
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// Else we would have to adapt JVMState by -1.
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if (i == mach_constant_base_node_input()) {
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call->add_req(loadConLNodes_IC._last);
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call->add_req(loadConLNodes_IC._last);
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} else {
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call->add_req(in(i));
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}
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@ -3666,6 +3667,8 @@ encode %{
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%}
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// Compound version of call dynamic
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// Toc is only passed so that it can be used in ins_encode statement.
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// In the code we have to use $constanttablebase.
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enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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MacroAssembler _masm(&cbuf);
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@ -3673,14 +3676,17 @@ encode %{
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Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
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#if 0
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int vtable_index = this->_vtable_index;
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if (_vtable_index < 0) {
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// Must be invalid_vtable_index, not nonvirtual_vtable_index.
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assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
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Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
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AddressLiteral meta = __ allocate_metadata_address((Metadata *)Universe::non_oop_word());
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// Virtual call relocation will point to ic load.
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address virtual_call_meta_addr = __ pc();
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__ load_const_from_method_toc(ic_reg, meta, Rtoc);
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// Load a clear inline cache.
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AddressLiteral empty_ic((address) Universe::non_oop_word());
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__ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
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// CALL to fixup routine. Fixup routine uses ScopeDesc info
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// to determine who we intended to call.
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__ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
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@ -3713,7 +3719,6 @@ encode %{
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"Fix constant in ret_addr_offset()");
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}
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#endif
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guarantee(0, "Fix handling of toc edge: messes up derived/base pairs.");
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Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
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%}
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@ -5439,7 +5444,7 @@ instruct loadI_ac(iRegIdst dst, memory mem) %{
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ins_pipe(pipe_class_memory);
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%}
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// Match loading integer and casting it to unsigned int in
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// Match loading integer and casting it to unsigned int in
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// long register.
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// LoadI + ConvI2L + AndL 0xffffffff.
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instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
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@ -6081,7 +6086,7 @@ instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{
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ins_pipe(pipe_class_default);
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%}
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// This needs a match rule so that build_oop_map knows this is
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// This needs a match rule so that build_oop_map knows this is
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// not a narrow oop.
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instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
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match(Set dst src1);
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@ -6705,7 +6710,7 @@ instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
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size(4);
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ins_encode %{
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// This is a Power7 instruction for which no machine description exists.
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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__ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
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%}
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ins_pipe(pipe_class_default);
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@ -6850,7 +6855,7 @@ instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
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size(4);
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ins_encode %{
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// This is a Power7 instruction for which no machine description exists.
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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__ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
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%}
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ins_pipe(pipe_class_default);
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@ -7067,7 +7072,7 @@ instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc s
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n1->_bottom_type = _bottom_type;
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decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
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n2->add_req(n_region, n2);
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n2->add_req(n_region, n1);
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n2->_opnds[0] = op_dst;
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n2->_opnds[1] = op_dst;
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n2->_bottom_type = _bottom_type;
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@ -7202,7 +7207,7 @@ instruct membar_volatile() %{
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// inline_unsafe_load_store).
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//
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// Add this node again if we found a good solution for inline_unsafe_load_store().
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// Don't forget to look at the implementation of post_store_load_barrier again,
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// Don't forget to look at the implementation of post_store_load_barrier again,
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// we did other fixes in that method.
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//instruct unnecessary_membar_volatile() %{
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// match(MemBarVolatile);
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@ -7240,7 +7245,7 @@ instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
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// exists. Anyways, the scheduler should be off on Power7.
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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int cc = $cmp$$cmpcode;
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__ isel($dst$$Register, $crx$$CondRegister,
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__ isel($dst$$Register, $crx$$CondRegister,
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(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
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%}
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ins_pipe(pipe_class_default);
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@ -7286,7 +7291,7 @@ instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
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// exists. Anyways, the scheduler should be off on Power7.
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// TODO: PPC port $archOpcode(ppc64Opcode_compound);
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int cc = $cmp$$cmpcode;
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -7332,7 +7337,7 @@ instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
|
||||
// exists. Anyways, the scheduler should be off on Power7.
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
|
||||
int cc = $cmp$$cmpcode;
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -7379,7 +7384,7 @@ instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
|
||||
// exists. Anyways, the scheduler should be off on Power7.
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
|
||||
int cc = $cmp$$cmpcode;
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
__ isel($dst$$Register, $crx$$CondRegister,
|
||||
(Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -7525,8 +7530,8 @@ instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
|
||||
// CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
|
||||
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
|
||||
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
|
||||
__ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
|
||||
MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
|
||||
$res$$Register, true);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -7932,7 +7937,23 @@ instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
|
||||
|
||||
// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
|
||||
// positive longs and 0xF...F for negative ones.
|
||||
instruct signmask64I_regI(iRegIdst dst, iRegIsrc src) %{
|
||||
instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
|
||||
// no match-rule, false predicate
|
||||
effect(DEF dst, USE src);
|
||||
predicate(false);
|
||||
|
||||
format %{ "SRADI $dst, $src, #63" %}
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_sradi);
|
||||
__ sradi($dst$$Register, $src$$Register, 0x3f);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
|
||||
// positive longs and 0xF...F for negative ones.
|
||||
instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
|
||||
// no match-rule, false predicate
|
||||
effect(DEF dst, USE src);
|
||||
predicate(false);
|
||||
@ -8896,7 +8917,7 @@ instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %
|
||||
size(4);
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
|
||||
__ rlwinm($dst$$Register, $src1$$Register, 0,
|
||||
__ rlwinm($dst$$Register, $src1$$Register, 0,
|
||||
(31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -9622,14 +9643,14 @@ instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
||||
ins_cost(DEFAULT_COST*4);
|
||||
|
||||
expand %{
|
||||
iRegIdst src1s;
|
||||
iRegIdst src2s;
|
||||
iRegIdst diff;
|
||||
sxtI_reg(src1s, src1); // ensure proper sign extention
|
||||
sxtI_reg(src2s, src2); // ensure proper sign extention
|
||||
subI_reg_reg(diff, src1s, src2s);
|
||||
iRegLdst src1s;
|
||||
iRegLdst src2s;
|
||||
iRegLdst diff;
|
||||
convI2L_reg(src1s, src1); // Ensure proper sign extension.
|
||||
convI2L_reg(src2s, src2); // Ensure proper sign extension.
|
||||
subL_reg_reg(diff, src1s, src2s);
|
||||
// Need to consider >=33 bit result, therefore we need signmaskL.
|
||||
signmask64I_regI(dst, diff);
|
||||
signmask64I_regL(dst, diff);
|
||||
%}
|
||||
%}
|
||||
|
||||
@ -10866,7 +10887,7 @@ instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P supe
|
||||
format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
|
||||
ins_encode %{
|
||||
// TODO: PPC port $archOpcode(ppc64Opcode_compound);
|
||||
__ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
|
||||
__ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
|
||||
$tmp_klass$$Register, NULL, $result$$Register);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
@ -11181,18 +11202,18 @@ instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
||||
ins_cost(DEFAULT_COST*6);
|
||||
|
||||
expand %{
|
||||
iRegIdst src1s;
|
||||
iRegIdst src2s;
|
||||
iRegIdst diff;
|
||||
iRegIdst sm;
|
||||
iRegIdst doz; // difference or zero
|
||||
sxtI_reg(src1s, src1); // Ensure proper sign extention.
|
||||
sxtI_reg(src2s, src2); // Ensure proper sign extention.
|
||||
subI_reg_reg(diff, src2s, src1s);
|
||||
iRegLdst src1s;
|
||||
iRegLdst src2s;
|
||||
iRegLdst diff;
|
||||
iRegLdst sm;
|
||||
iRegLdst doz; // difference or zero
|
||||
convI2L_reg(src1s, src1); // Ensure proper sign extension.
|
||||
convI2L_reg(src2s, src2); // Ensure proper sign extension.
|
||||
subL_reg_reg(diff, src2s, src1s);
|
||||
// Need to consider >=33 bit result, therefore we need signmaskL.
|
||||
signmask64I_regI(sm, diff);
|
||||
andI_reg_reg(doz, diff, sm); // <=0
|
||||
addI_reg_reg(dst, doz, src1s);
|
||||
signmask64L_regL(sm, diff);
|
||||
andL_reg_reg(doz, diff, sm); // <=0
|
||||
addI_regL_regL(dst, doz, src1s);
|
||||
%}
|
||||
%}
|
||||
|
||||
@ -11201,19 +11222,18 @@ instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
|
||||
ins_cost(DEFAULT_COST*6);
|
||||
|
||||
expand %{
|
||||
immI_minus1 m1 %{ -1 %}
|
||||
iRegIdst src1s;
|
||||
iRegIdst src2s;
|
||||
iRegIdst diff;
|
||||
iRegIdst sm;
|
||||
iRegIdst doz; // difference or zero
|
||||
sxtI_reg(src1s, src1); // Ensure proper sign extention.
|
||||
sxtI_reg(src2s, src2); // Ensure proper sign extention.
|
||||
subI_reg_reg(diff, src2s, src1s);
|
||||
iRegLdst src1s;
|
||||
iRegLdst src2s;
|
||||
iRegLdst diff;
|
||||
iRegLdst sm;
|
||||
iRegLdst doz; // difference or zero
|
||||
convI2L_reg(src1s, src1); // Ensure proper sign extension.
|
||||
convI2L_reg(src2s, src2); // Ensure proper sign extension.
|
||||
subL_reg_reg(diff, src2s, src1s);
|
||||
// Need to consider >=33 bit result, therefore we need signmaskL.
|
||||
signmask64I_regI(sm, diff);
|
||||
andcI_reg_reg(doz, sm, m1, diff); // >=0
|
||||
addI_reg_reg(dst, doz, src1s);
|
||||
signmask64L_regL(sm, diff);
|
||||
andcL_reg_reg(doz, diff, sm); // >=0
|
||||
addI_regL_regL(dst, doz, src1s);
|
||||
%}
|
||||
%}
|
||||
|
||||
|
||||
@ -81,24 +81,18 @@ address TemplateInterpreterGenerator::generate_ArrayIndexOutOfBounds_handler(con
|
||||
#if 0
|
||||
// Call special ClassCastException constructor taking object to cast
|
||||
// and target class as arguments.
|
||||
address TemplateInterpreterGenerator::generate_ClassCastException_verbose_handler(const char* name) {
|
||||
address TemplateInterpreterGenerator::generate_ClassCastException_verbose_handler() {
|
||||
address entry = __ pc();
|
||||
|
||||
// Target class oop is in register R6_ARG4 by convention!
|
||||
|
||||
// Expression stack must be empty before entering the VM if an
|
||||
// exception happened.
|
||||
__ empty_expression_stack();
|
||||
// Setup parameters.
|
||||
|
||||
// Thread will be loaded to R3_ARG1.
|
||||
__ load_const_optimized(R4_ARG2, (address) name);
|
||||
__ mr(R5_ARG3, R17_tos);
|
||||
// R6_ARG4 contains specified class.
|
||||
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_ClassCastException_verbose));
|
||||
#ifdef ASSERT
|
||||
// Target class oop is in register R5_ARG3 by convention!
|
||||
__ call_VM(noreg, CAST_FROM_FN_PTR(address, InterpreterRuntime::throw_ClassCastException_verbose, R17_tos, R5_ARG3));
|
||||
// Above call must not return here since exception pending.
|
||||
__ should_not_reach_here();
|
||||
#endif
|
||||
DEBUG_ONLY(__ should_not_reach_here();)
|
||||
return entry;
|
||||
}
|
||||
#endif
|
||||
@ -1538,14 +1532,32 @@ void TemplateInterpreterGenerator::generate_throw_exception() {
|
||||
__ stw(R0, in_bytes(JavaThread::popframe_condition_offset()), R16_thread);
|
||||
|
||||
// Get out of the current method and re-execute the call that called us.
|
||||
__ merge_frames(/*top_frame_sp*/ R21_sender_SP, /*return_pc*/ return_pc, R11_scratch1, R12_scratch2);
|
||||
__ merge_frames(/*top_frame_sp*/ R21_sender_SP, /*return_pc*/ noreg, R11_scratch1, R12_scratch2);
|
||||
__ restore_interpreter_state(R11_scratch1);
|
||||
__ ld(R12_scratch2, _ijava_state_neg(top_frame_sp), R11_scratch1);
|
||||
__ resize_frame_absolute(R12_scratch2, R11_scratch1, R0);
|
||||
__ mtlr(return_pc);
|
||||
if (ProfileInterpreter) {
|
||||
__ set_method_data_pointer_for_bcp();
|
||||
}
|
||||
#if INCLUDE_JVMTI
|
||||
Label L_done;
|
||||
|
||||
__ lbz(R11_scratch1, 0, R14_bcp);
|
||||
__ cmpwi(CCR0, R11_scratch1, Bytecodes::_invokestatic);
|
||||
__ bne(CCR0, L_done);
|
||||
|
||||
// The member name argument must be restored if _invokestatic is re-executed after a PopFrame call.
|
||||
// Detect such a case in the InterpreterRuntime function and return the member name argument, or NULL.
|
||||
__ ld(R4_ARG2, 0, R18_locals);
|
||||
__ call_VM(R11_scratch1, CAST_FROM_FN_PTR(address, InterpreterRuntime::member_name_arg_or_null),
|
||||
R4_ARG2, R19_method, R14_bcp);
|
||||
|
||||
__ cmpdi(CCR0, R11_scratch1, 0);
|
||||
__ beq(CCR0, L_done);
|
||||
|
||||
__ std(R11_scratch1, wordSize, R15_esp);
|
||||
__ bind(L_done);
|
||||
#endif // INCLUDE_JVMTI
|
||||
__ dispatch_next(vtos);
|
||||
}
|
||||
// end of JVMTI PopFrame support
|
||||
|
||||
@ -64,7 +64,7 @@ static void do_oop_store(InterpreterMacroAssembler* _masm,
|
||||
assert_different_registers(Rtmp1, Rtmp2, Rtmp3, Rval, Rbase);
|
||||
|
||||
switch (barrier) {
|
||||
#ifndef SERIALGC
|
||||
#if INCLUDE_ALL_GCS
|
||||
case BarrierSet::G1SATBCT:
|
||||
case BarrierSet::G1SATBCTLogging:
|
||||
{
|
||||
@ -104,7 +104,7 @@ static void do_oop_store(InterpreterMacroAssembler* _masm,
|
||||
__ bind(Ldone);
|
||||
}
|
||||
break;
|
||||
#endif // SERIALGC
|
||||
#endif // INCLUDE_ALL_GCS
|
||||
case BarrierSet::CardTableModRef:
|
||||
case BarrierSet::CardTableExtension:
|
||||
{
|
||||
@ -259,17 +259,17 @@ void TemplateTable::fconst(int value) {
|
||||
switch (value) {
|
||||
default: ShouldNotReachHere();
|
||||
case 0: {
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0);
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0, true);
|
||||
__ lfs(F15_ftos, simm16_offset, R11_scratch1);
|
||||
break;
|
||||
}
|
||||
case 1: {
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0);
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0, true);
|
||||
__ lfs(F15_ftos, simm16_offset, R11_scratch1);
|
||||
break;
|
||||
}
|
||||
case 2: {
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&two, R0);
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&two, R0, true);
|
||||
__ lfs(F15_ftos, simm16_offset, R11_scratch1);
|
||||
break;
|
||||
}
|
||||
@ -282,12 +282,12 @@ void TemplateTable::dconst(int value) {
|
||||
static double one = 1.0;
|
||||
switch (value) {
|
||||
case 0: {
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0);
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&zero, R0, true);
|
||||
__ lfd(F15_ftos, simm16_offset, R11_scratch1);
|
||||
break;
|
||||
}
|
||||
case 1: {
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0);
|
||||
int simm16_offset = __ load_const_optimized(R11_scratch1, (address*)&one, R0, true);
|
||||
__ lfd(F15_ftos, simm16_offset, R11_scratch1);
|
||||
break;
|
||||
}
|
||||
@ -3712,9 +3712,9 @@ void TemplateTable::checkcast() {
|
||||
transition(atos, atos);
|
||||
|
||||
Label Ldone, Lis_null, Lquicked, Lresolved;
|
||||
Register Roffset = R5_ARG3,
|
||||
Register Roffset = R6_ARG4,
|
||||
RobjKlass = R4_ARG2,
|
||||
RspecifiedKlass = R6_ARG4, // Generate_ClassCastException_verbose_handler will expect this register.
|
||||
RspecifiedKlass = R5_ARG3, // Generate_ClassCastException_verbose_handler will read value from this register.
|
||||
Rcpool = R11_scratch1,
|
||||
Rtags = R12_scratch2;
|
||||
|
||||
|
||||
@ -53,41 +53,41 @@ inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *
|
||||
|
||||
inline jlong Atomic::load(volatile jlong* src) { return *src; }
|
||||
|
||||
/*
|
||||
machine barrier instructions:
|
||||
|
||||
- sync two-way memory barrier, aka fence
|
||||
- lwsync orders Store|Store,
|
||||
Load|Store,
|
||||
Load|Load,
|
||||
but not Store|Load
|
||||
- eieio orders memory accesses for device memory (only)
|
||||
- isync invalidates speculatively executed instructions
|
||||
From the POWER ISA 2.06 documentation:
|
||||
"[...] an isync instruction prevents the execution of
|
||||
instructions following the isync until instructions
|
||||
preceding the isync have completed, [...]"
|
||||
From IBM's AIX assembler reference:
|
||||
"The isync [...] instructions causes the processor to
|
||||
refetch any instructions that might have been fetched
|
||||
prior to the isync instruction. The instruction isync
|
||||
causes the processor to wait for all previous instructions
|
||||
to complete. Then any instructions already fetched are
|
||||
discarded and instruction processing continues in the
|
||||
environment established by the previous instructions."
|
||||
|
||||
semantic barrier instructions:
|
||||
(as defined in orderAccess.hpp)
|
||||
|
||||
- release orders Store|Store, (maps to lwsync)
|
||||
Load|Store
|
||||
- acquire orders Load|Store, (maps to lwsync)
|
||||
Load|Load
|
||||
- fence orders Store|Store, (maps to sync)
|
||||
Load|Store,
|
||||
Load|Load,
|
||||
Store|Load
|
||||
*/
|
||||
//
|
||||
// machine barrier instructions:
|
||||
//
|
||||
// - sync two-way memory barrier, aka fence
|
||||
// - lwsync orders Store|Store,
|
||||
// Load|Store,
|
||||
// Load|Load,
|
||||
// but not Store|Load
|
||||
// - eieio orders memory accesses for device memory (only)
|
||||
// - isync invalidates speculatively executed instructions
|
||||
// From the POWER ISA 2.06 documentation:
|
||||
// "[...] an isync instruction prevents the execution of
|
||||
// instructions following the isync until instructions
|
||||
// preceding the isync have completed, [...]"
|
||||
// From IBM's AIX assembler reference:
|
||||
// "The isync [...] instructions causes the processor to
|
||||
// refetch any instructions that might have been fetched
|
||||
// prior to the isync instruction. The instruction isync
|
||||
// causes the processor to wait for all previous instructions
|
||||
// to complete. Then any instructions already fetched are
|
||||
// discarded and instruction processing continues in the
|
||||
// environment established by the previous instructions."
|
||||
//
|
||||
// semantic barrier instructions:
|
||||
// (as defined in orderAccess.hpp)
|
||||
//
|
||||
// - release orders Store|Store, (maps to lwsync)
|
||||
// Load|Store
|
||||
// - acquire orders Load|Store, (maps to lwsync)
|
||||
// Load|Load
|
||||
// - fence orders Store|Store, (maps to sync)
|
||||
// Load|Store,
|
||||
// Load|Load,
|
||||
// Store|Load
|
||||
//
|
||||
|
||||
#define strasm_sync "\n sync \n"
|
||||
#define strasm_lwsync "\n lwsync \n"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user