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8320997: RISC-V: C2 ReverseV
Reviewed-by: fyang, luhenry
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parent
6879c446c6
commit
9f582e56ba
@ -79,6 +79,7 @@ source %{
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case Op_PopCountVL:
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case Op_PopCountVI:
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case Op_ReverseBytesV:
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case Op_ReverseV:
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case Op_RotateLeftV:
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case Op_RotateRightV:
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return UseZvbb;
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@ -4704,6 +4705,32 @@ instruct vround_d(vReg dst, vReg src, fRegD tmp, vRegMask_V0 v0) %{
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ins_pipe(pipe_slow);
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%}
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// -------------------------------- Reverse Bits Vector Operations ------------------------
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instruct vreverse_masked(vReg dst_src, vRegMask_V0 v0) %{
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match(Set dst_src (ReverseV dst_src v0));
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format %{ "vreverse_masked $dst_src, $dst_src, v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vbrev_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vreverse(vReg dst, vReg src) %{
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match(Set dst (ReverseV src));
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format %{ "vreverse $dst, $src" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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uint vlen = Matcher::vector_length(this);
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__ vsetvli_helper(bt, vlen);
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__ vbrev_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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// -------------------------------- Reverse Bytes Vector Operations ------------------------
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instruct vreverse_bytes_masked(vReg dst_src, vRegMask_V0 v0) %{
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@ -25,7 +25,9 @@
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* @bug 8290034
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* @summary Auto-vectorization of Reverse bit operation.
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64"
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
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* os.arch == "aarch64" |
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* (os.arch == "riscv64" & vm.cpu.features ~= ".*zbkb.*" & vm.cpu.features ~= ".*zvbb.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestReverseBitsVector
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*/
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