8320997: RISC-V: C2 ReverseV

Reviewed-by: fyang, luhenry
This commit is contained in:
Hamlin Li 2025-03-25 09:29:40 +00:00
parent 6879c446c6
commit 9f582e56ba
2 changed files with 30 additions and 1 deletions

View File

@ -79,6 +79,7 @@ source %{
case Op_PopCountVL:
case Op_PopCountVI:
case Op_ReverseBytesV:
case Op_ReverseV:
case Op_RotateLeftV:
case Op_RotateRightV:
return UseZvbb;
@ -4704,6 +4705,32 @@ instruct vround_d(vReg dst, vReg src, fRegD tmp, vRegMask_V0 v0) %{
ins_pipe(pipe_slow);
%}
// -------------------------------- Reverse Bits Vector Operations ------------------------
instruct vreverse_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (ReverseV dst_src v0));
format %{ "vreverse_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vbrev_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
instruct vreverse(vReg dst, vReg src) %{
match(Set dst (ReverseV src));
format %{ "vreverse $dst, $src" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vbrev_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
// -------------------------------- Reverse Bytes Vector Operations ------------------------
instruct vreverse_bytes_masked(vReg dst_src, vRegMask_V0 v0) %{

View File

@ -25,7 +25,9 @@
* @bug 8290034
* @summary Auto-vectorization of Reverse bit operation.
* @requires vm.compiler2.enabled
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64"
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
* os.arch == "aarch64" |
* (os.arch == "riscv64" & vm.cpu.features ~= ".*zbkb.*" & vm.cpu.features ~= ".*zvbb.*")
* @library /test/lib /
* @run driver compiler.vectorization.TestReverseBitsVector
*/