mirror of
https://github.com/openjdk/jdk.git
synced 2026-05-12 14:39:49 +00:00
8259948: Aarch64: Add cast nodes for Aarch64 Neon backend
Co-authored-by: Wang Huang <whuang@openjdk.org> Co-authored-by: Wu Yan <wuyan@openjdk.org> Co-authored-by: Miao Zhuojun <mouzhuojun@huawei.com> Reviewed-by: aph, eliu, njian
This commit is contained in:
Wang Huang
Ningsheng Jian
parent
d98b7c2591
commit
9f75d5ce50
@ -2401,9 +2401,6 @@ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType
|
||||
// Special cases
|
||||
switch (opcode) {
|
||||
case Op_VectorMaskCmp:
|
||||
// We don't have VectorReinterpret with bit_size less than 64 support for
|
||||
// now, even for byte type. To be refined with fully VectorCast support.
|
||||
case Op_VectorReinterpret:
|
||||
if (vlen < 2 || bit_size < 64) {
|
||||
return false;
|
||||
}
|
||||
@ -2421,23 +2418,6 @@ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
// Some types of VectorCast are not implemented for now.
|
||||
case Op_VectorCastI2X:
|
||||
if (bt == T_BYTE) {
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case Op_VectorCastS2X:
|
||||
if (vlen < 4 || bit_size < 64) {
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case Op_VectorCastF2X:
|
||||
case Op_VectorCastD2X:
|
||||
if (bt == T_INT || bt == T_SHORT || bt == T_BYTE || bt == T_LONG) {
|
||||
return false;
|
||||
}
|
||||
break;
|
||||
case Op_LoadVectorGather:
|
||||
case Op_StoreVectorScatter:
|
||||
return false;
|
||||
|
||||
@ -150,16 +150,12 @@ instruct reinterpretD2X(vecX dst, vecD src)
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# D2X" %}
|
||||
format %{ " # reinterpret $dst,$src\t# D to X" %}
|
||||
ins_encode %{
|
||||
// If registers are the same, no register move is required - the
|
||||
// upper 64 bits of 'src' are expected to have been initialized
|
||||
// to zero.
|
||||
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
|
||||
__ orr(as_FloatRegister($dst$$reg), __ T8B,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
}
|
||||
// The higher 64-bits of the "dst" register must be cleared to zero.
|
||||
__ orr(as_FloatRegister($dst$$reg), __ T8B,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(vlogical64);
|
||||
%}
|
||||
@ -170,10 +166,9 @@ instruct reinterpretX2D(vecD dst, vecX src)
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# X2D" %}
|
||||
format %{ " # reinterpret $dst,$src\t# X to D" %}
|
||||
ins_encode %{
|
||||
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
|
||||
// the "dst" register must be cleared to zero.
|
||||
// The higher 64-bits of the "dst" register must be cleared to zero.
|
||||
__ orr(as_FloatRegister($dst$$reg), __ T8B,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
@ -181,19 +176,64 @@ instruct reinterpretX2D(vecD dst, vecX src)
|
||||
ins_pipe(vlogical64);
|
||||
%}
|
||||
|
||||
// ------------------------------ Vector cast -------------------------------
|
||||
|
||||
instruct vcvt4Bto4S(vecD dst, vecD src)
|
||||
instruct reinterpretS2X(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\t# convert 4B to 4S vector" %}
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 4);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# S to X" %}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
// The higher bits of the "dst" register must be cleared to zero.
|
||||
__ dup(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct reinterpretX2S(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 4 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# X to S" %}
|
||||
ins_encode %{
|
||||
// The higher bits of the "dst" register must be cleared to zero.
|
||||
__ dup(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct reinterpretS2D(vecD dst, vecD src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 4);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# S to D" %}
|
||||
ins_encode %{
|
||||
// The higher bits of the "dst" register must be cleared to zero.
|
||||
__ dup(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct reinterpretD2S(vecD dst, vecD src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 4 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# D to S" %}
|
||||
ins_encode %{
|
||||
// The higher bits of the "dst" register must be cleared to zero.
|
||||
__ dup(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
// ------------------------------ Vector cast -------------------------------
|
||||
|
||||
instruct vcvt8Bto8S(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
@ -205,13 +245,13 @@ instruct vcvt8Bto8S(vecX dst, vecD src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Sto4B(vecD dst, vecD src)
|
||||
instruct vcvt4Bto4S(vecD dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
|
||||
match(Set dst (VectorCastS2X src));
|
||||
format %{ "xtn $dst, T8B, $src, T8H\t# convert 4S to 4B vector" %}
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\t# convert 4B to 4S vector" %}
|
||||
ins_encode %{
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
@ -227,6 +267,17 @@ instruct vcvt8Sto8B(vecD dst, vecX src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Sto4B(vecD dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
|
||||
match(Set dst (VectorCastS2X src));
|
||||
format %{ "xtn $dst, T8B, $src, T8H\t# convert 4S to 4B vector" %}
|
||||
ins_encode %{
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Sto4I(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
@ -271,20 +322,6 @@ instruct vcvt2Lto2I(vecD dst, vecX src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Bto4I(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
|
||||
"sxtl $dst, T4S, $dst, T4H\t# convert 4B to 4I vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt4Ito4B(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
|
||||
@ -296,49 +333,33 @@ instruct vcvt4Ito4B(vecD dst, vecX src)
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Bto4F(vecX dst, vecD src)
|
||||
instruct vcvt4Bto4I(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
|
||||
"sxtl $dst, T4S, $dst, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
|
||||
"sxtl $dst, T4S, $dst, T4H\t# convert 4B to 4I vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Sto4F(vecX dst, vecD src)
|
||||
instruct vcvt2Lto2F(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastS2X src));
|
||||
format %{ "sxtl $dst, T4S, $src, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4S to 4F vector"
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastL2X src));
|
||||
format %{ "scvtfv T2D, $dst, $src\n\t"
|
||||
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Ito2D(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
|
||||
match(Set dst (VectorCastI2X src));
|
||||
format %{ "sxtl $dst, T2D, $src, T2S\n\t"
|
||||
"scvtfv T2D, $dst, $dst\t# convert 2I to 2D vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
|
||||
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
@ -376,6 +397,141 @@ instruct vcvt2Lto2D(vecX dst, vecX src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Sto4F(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastS2X src));
|
||||
format %{ "sxtl $dst, T4S, $src, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4S to 4F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Ito2D(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
|
||||
match(Set dst (VectorCastI2X src));
|
||||
format %{ "sxtl $dst, T2D, $src, T2S\n\t"
|
||||
"scvtfv T2D, $dst, $dst\t# convert 2I to 2D vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt4Bto4F(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
|
||||
"sxtl $dst, T4S, $dst, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Fto2L(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtl $dst, T2D, $src, T2S\n\t"
|
||||
"fcvtzs $dst, T2D, $dst\t# convert 2F to 2L vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Fto2I(vecD dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtzs $dst, T2S, $src\t# convert 2F to 2I vector" %}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Fto4I(vecX dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtzs $dst, T4S, $src\t# convert 4F to 4I vector" %}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt2Dto2L(vecX dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
|
||||
match(Set dst (VectorCastD2X src));
|
||||
format %{ "fcvtzs $dst, T2D, $src\t# convert 2D to 2L vector" %}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt4Fto4S(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtzs $dst, T4S, $src\n\t"
|
||||
"xtn $dst, T4H, $dst, T4S\t# convert 4F to 4S vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($dst$$reg), __ T4S);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Dto2I(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
|
||||
match(Set dst (VectorCastD2X src));
|
||||
format %{ "fcvtzs $dst, T2D, $src\n\t"
|
||||
"xtn $dst, T2S, $dst, T2D\t# convert 2D to 2I vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt4Fto4B(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtzs $dst, T4S, $src\n\t"
|
||||
"xtn $dst, T4H, $dst, T4S\n\t"
|
||||
"xtn $dst, T8B, $dst, T8H\t# convert 4F to 4B vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($dst$$reg), __ T4S);
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Fto2D(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
|
||||
@ -398,20 +554,6 @@ instruct vcvt2Dto2F(vecD dst, vecX src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}
|
||||
|
||||
instruct vcvt2Lto2F(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastL2X src));
|
||||
format %{ "scvtfv T2D, $dst, $src\n\t"
|
||||
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
|
||||
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
// ------------------------------ Reduction -------------------------------
|
||||
|
||||
instruct reduce_add8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
|
||||
@ -1887,7 +2029,7 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
|
||||
"umov $tmp1, $src1, D, 1\n\t"
|
||||
"umov $tmp2, $src2, D, 1\n\t"
|
||||
"mul $tmp2, $tmp2, $tmp1\n\t"
|
||||
"mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)\n\t"
|
||||
"mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
|
||||
@ -4019,7 +4161,7 @@ instruct vmuladdS2I(vecX dst, vecX src1, vecX src2, vecX tmp) %{
|
||||
effect(TEMP_DEF dst, TEMP tmp);
|
||||
format %{ "smullv $tmp, $src1, $src2\t# vector (4H)\n\t"
|
||||
"smullv $dst, $src1, $src2\t# vector (8H)\n\t"
|
||||
"addpv $dst, $tmp, $dst\t# vector (4S)\n\t" %}
|
||||
"addpv $dst, $tmp, $dst\t# vector (4S)" %}
|
||||
ins_encode %{
|
||||
__ smullv(as_FloatRegister($tmp$$reg), __ T4H,
|
||||
as_FloatRegister($src1$$reg),
|
||||
|
||||
@ -95,43 +95,46 @@ dnl $1 $2
|
||||
REINTERPRET(D, 8)
|
||||
REINTERPRET(X, 16)
|
||||
dnl
|
||||
|
||||
instruct reinterpretD2X(vecX dst, vecD src)
|
||||
define(`REINTERPRET_DX', `
|
||||
instruct reinterpret$1`'2$2`'(vec$2 dst, vec$1 src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == $3 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == $4);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# D2X" %}
|
||||
format %{ " # reinterpret $dst,$src\t# $1 to $2" %}
|
||||
ins_encode %{
|
||||
// If registers are the same, no register move is required - the
|
||||
// upper 64 bits of 'src' are expected to have been initialized
|
||||
// to zero.
|
||||
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
|
||||
__ orr(as_FloatRegister($dst$$reg), __ T8B,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
}
|
||||
%}
|
||||
ins_pipe(vlogical64);
|
||||
%}
|
||||
|
||||
instruct reinterpretX2D(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# X2D" %}
|
||||
ins_encode %{
|
||||
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
|
||||
// the "dst" register must be cleared to zero.
|
||||
// The higher 64-bits of the "dst" register must be cleared to zero.
|
||||
__ orr(as_FloatRegister($dst$$reg), __ T8B,
|
||||
as_FloatRegister($src$$reg),
|
||||
as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(vlogical64);
|
||||
%}
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4
|
||||
REINTERPRET_DX(D, X, 16, 8)
|
||||
REINTERPRET_DX(X, D, 8, 16)
|
||||
dnl
|
||||
define(`REINTERPRET_SX', `
|
||||
instruct reinterpret$1`'2$2`'(vec$3 dst, vec$4 src)
|
||||
%{
|
||||
predicate(n->bottom_type()->is_vect()->length_in_bytes() == $5 &&
|
||||
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == $6);
|
||||
match(Set dst (VectorReinterpret src));
|
||||
ins_cost(INSN_COST);
|
||||
format %{ " # reinterpret $dst,$src\t# $1 to $2" %}
|
||||
ins_encode %{
|
||||
// The higher bits of the "dst" register must be cleared to zero.
|
||||
__ dup(as_FloatRegister($dst$$reg), __ S, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6
|
||||
REINTERPRET_SX(S, X, X, D, 16, 4)
|
||||
REINTERPRET_SX(X, S, D, X, 4, 16)
|
||||
REINTERPRET_SX(S, D, D, D, 8, 4)
|
||||
REINTERPRET_SX(D, S, D, D, 4, 8)
|
||||
dnl
|
||||
|
||||
// ------------------------------ Vector cast -------------------------------
|
||||
dnl
|
||||
@ -147,66 +150,47 @@ instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$5 src)
|
||||
ins_pipe(pipe_class_default);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6 $7 $8
|
||||
VECTOR_CAST_I2I(4, B, S, D, D, sxtl, 8B, 8H)
|
||||
VECTOR_CAST_I2I(8, B, S, X, D, sxtl, 8B, 8H)
|
||||
VECTOR_CAST_I2I(4, S, B, D, D, xtn, 8H, 8B)
|
||||
VECTOR_CAST_I2I(4, B, S, D, D, sxtl, 8B, 8H)
|
||||
VECTOR_CAST_I2I(8, S, B, D, X, xtn, 8H, 8B)
|
||||
VECTOR_CAST_I2I(4, S, B, D, D, xtn, 8H, 8B)
|
||||
VECTOR_CAST_I2I(4, S, I, X, D, sxtl, 4H, 4S)
|
||||
VECTOR_CAST_I2I(4, I, S, D, X, xtn, 4S, 4H)
|
||||
VECTOR_CAST_I2I(2, I, L, X, D, sxtl, 2S, 2D)
|
||||
VECTOR_CAST_I2I(2, L, I, D, X, xtn, 2D, 2S)
|
||||
dnl
|
||||
define(`VECTOR_CAST_B2I', `
|
||||
instruct vcvt4$1to4$2`'(vec$3 dst, vec$4 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
|
||||
match(Set dst (VectorCast$1`'2X src));
|
||||
format %{ "$5 $dst, T$7, $src, T$6\n\t"
|
||||
"$5 $dst, T$9, $dst, T$8\t# convert 4$1 to 4$2 vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ $5(as_FloatRegister($dst$$reg), __ T$7, as_FloatRegister($src$$reg), __ T$6);
|
||||
__ $5(as_FloatRegister($dst$$reg), __ T$9, as_FloatRegister($dst$$reg), __ T$8);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6 $7 $8 $9
|
||||
VECTOR_CAST_B2I(B, I, X, D, sxtl, 8B, 8H, 4H, 4S)
|
||||
VECTOR_CAST_B2I(I, B, D, X, xtn, 4S, 4H, 8H, 8B)
|
||||
|
||||
instruct vcvt4Bto4F(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
|
||||
"sxtl $dst, T4S, $dst, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
dnl
|
||||
define(`VECTOR_CAST_I2F_L', `
|
||||
instruct vcvt$1$2to$1$3`'(vecX dst, vecD src)
|
||||
define(`VECTOR_CAST_I2I_L', `
|
||||
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$5 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
|
||||
match(Set dst (VectorCast$2`'2X src));
|
||||
format %{ "sxtl $dst, T$5, $src, T$4\n\t"
|
||||
"scvtfv T$5, $dst, $dst\t# convert $1$2 to $1$3 vector"
|
||||
format %{ "$6 $dst, T$8, $src, T$7\n\t"
|
||||
"$6 $dst, T$10, $dst, T$9\t# convert $1$2 to $1$3 vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T$5, as_FloatRegister($src$$reg), __ T$4);
|
||||
__ scvtfv(__ T$5, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
__ $6(as_FloatRegister($dst$$reg), __ T$8, as_FloatRegister($src$$reg), __ T$7);
|
||||
__ $6(as_FloatRegister($dst$$reg), __ T$10, as_FloatRegister($dst$$reg), __ T$9);
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6 $7 $8 $9 $10
|
||||
VECTOR_CAST_I2I_L(4, I, B, D, X, xtn, 4S, 4H, 8H, 8B)
|
||||
VECTOR_CAST_I2I_L(4, B, I, X, D, sxtl, 8B, 8H, 4H, 4S)
|
||||
dnl
|
||||
|
||||
instruct vcvt2Lto2F(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastL2X src));
|
||||
format %{ "scvtfv T2D, $dst, $src\n\t"
|
||||
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
|
||||
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VECTOR_CAST_I2F_L(4, S, F, 4H, 4S)
|
||||
VECTOR_CAST_I2F_L(2, I, D, 2S, 2D)
|
||||
%}
|
||||
dnl
|
||||
define(`VECTOR_CAST_I2F', `
|
||||
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$4 src)
|
||||
@ -224,6 +208,106 @@ VECTOR_CAST_I2F(2, I, F, D, 2S)
|
||||
VECTOR_CAST_I2F(4, I, F, X, 4S)
|
||||
VECTOR_CAST_I2F(2, L, D, X, 2D)
|
||||
dnl
|
||||
define(`VECTOR_CAST_I2F_L', `
|
||||
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$5 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
|
||||
match(Set dst (VectorCast$2`'2X src));
|
||||
format %{ "sxtl $dst, T$7, $src, T$6\n\t"
|
||||
"scvtfv T$7, $dst, $dst\t# convert $1$2 to $1$3 vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T$7, as_FloatRegister($src$$reg), __ T$6);
|
||||
__ scvtfv(__ T$7, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6 $7
|
||||
VECTOR_CAST_I2F_L(4, S, F, X, D, 4H, 4S)
|
||||
VECTOR_CAST_I2F_L(2, I, D, X, D, 2S, 2D)
|
||||
dnl
|
||||
|
||||
instruct vcvt4Bto4F(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastB2X src));
|
||||
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
|
||||
"sxtl $dst, T4S, $dst, T4H\n\t"
|
||||
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
|
||||
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
|
||||
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
instruct vcvt2Fto2L(vecX dst, vecD src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtl $dst, T2D, $src, T2S\n\t"
|
||||
"fcvtzs $dst, T2D, $dst\t# convert 2F to 2L vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
dnl
|
||||
define(`VECTOR_CAST_F2I', `
|
||||
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$4 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
|
||||
match(Set dst (VectorCast$2`'2X src));
|
||||
format %{ "fcvtzs $dst, T$5, $src\t# convert $1$2 to $1$3 vector" %}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T$5, as_FloatRegister($src$$reg));
|
||||
%}
|
||||
ins_pipe(pipe_class_default);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5
|
||||
VECTOR_CAST_F2I(2, F, I, D, 2S)
|
||||
VECTOR_CAST_F2I(4, F, I, X, 4S)
|
||||
VECTOR_CAST_F2I(2, D, L, X, 2D)
|
||||
dnl
|
||||
define(`VECTOR_CAST_F2I_L', `
|
||||
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$5 src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
|
||||
match(Set dst (VectorCast$2`'2X src));
|
||||
format %{ "fcvtzs $dst, T$6, $src\n\t"
|
||||
"xtn $dst, T$7, $dst, T$6\t# convert $1$2 to $1$3 vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T$6, as_FloatRegister($src$$reg));
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T$7, as_FloatRegister($dst$$reg), __ T$6);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}')dnl
|
||||
dnl $1 $2 $3 $4 $5 $6 $7
|
||||
VECTOR_CAST_F2I_L(4, F, S, D, X, 4S, 4H)
|
||||
VECTOR_CAST_F2I_L(2, D, I, D, X, 2D, 2S)
|
||||
dnl
|
||||
|
||||
instruct vcvt4Fto4B(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
|
||||
match(Set dst (VectorCastF2X src));
|
||||
format %{ "fcvtzs $dst, T4S, $src\n\t"
|
||||
"xtn $dst, T4H, $dst, T4S\n\t"
|
||||
"xtn $dst, T8B, $dst, T8H\t# convert 4F to 4B vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ fcvtzs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($dst$$reg), __ T4S);
|
||||
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
dnl
|
||||
define(`VECTOR_CAST_F2F', `
|
||||
instruct vcvt2$1to2$2`'(vec$3 dst, vec$4 src)
|
||||
%{
|
||||
@ -240,20 +324,6 @@ VECTOR_CAST_F2F(F, D, X, D, fcvtl, 2S, 2D)
|
||||
VECTOR_CAST_F2F(D, F, D, X, fcvtn, 2D, 2S)
|
||||
dnl
|
||||
|
||||
instruct vcvt2Lto2F(vecD dst, vecX src)
|
||||
%{
|
||||
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
|
||||
match(Set dst (VectorCastL2X src));
|
||||
format %{ "scvtfv T2D, $dst, $src\n\t"
|
||||
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
|
||||
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
|
||||
%}
|
||||
ins_pipe(pipe_slow);
|
||||
%}
|
||||
|
||||
// ------------------------------ Reduction -------------------------------
|
||||
dnl
|
||||
define(`REDUCE_ADD_BORS', `
|
||||
@ -909,7 +979,7 @@ instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
|
||||
"umov $tmp1, $src1, D, 1\n\t"
|
||||
"umov $tmp2, $src2, D, 1\n\t"
|
||||
"mul $tmp2, $tmp2, $tmp1\n\t"
|
||||
"mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)\n\t"
|
||||
"mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)"
|
||||
%}
|
||||
ins_encode %{
|
||||
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
|
||||
@ -1782,7 +1852,7 @@ instruct vmuladdS2I(vecX dst, vecX src1, vecX src2, vecX tmp) %{
|
||||
effect(TEMP_DEF dst, TEMP tmp);
|
||||
format %{ "smullv $tmp, $src1, $src2\t# vector (4H)\n\t"
|
||||
"smullv $dst, $src1, $src2\t# vector (8H)\n\t"
|
||||
"addpv $dst, $tmp, $dst\t# vector (4S)\n\t" %}
|
||||
"addpv $dst, $tmp, $dst\t# vector (4S)" %}
|
||||
ins_encode %{
|
||||
__ smullv(as_FloatRegister($tmp$$reg), __ T4H,
|
||||
as_FloatRegister($src1$$reg),
|
||||
|
||||
@ -2823,6 +2823,16 @@ public:
|
||||
f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
|
||||
}
|
||||
|
||||
// Advanced SIMD scalar copy
|
||||
void dup(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int index = 0)
|
||||
{
|
||||
starti;
|
||||
assert(T != Q, "invalid size");
|
||||
f(0b01011110000, 31, 21);
|
||||
f((1 << T) | (index << (T + 1)), 20, 16);
|
||||
f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
|
||||
}
|
||||
|
||||
// AdvSIMD ZIP/UZP/TRN
|
||||
#define INSN(NAME, opcode) \
|
||||
void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
|
||||
@ -2901,6 +2911,7 @@ public:
|
||||
INSN(frintn, 0, 0b00, 0b01, 0b11000);
|
||||
INSN(frintm, 0, 0b00, 0b01, 0b11001);
|
||||
INSN(frintp, 0, 0b10, 0b01, 0b11000);
|
||||
INSN(fcvtzs, 0, 0b10, 0b01, 0b11011);
|
||||
#undef ASSERTION
|
||||
|
||||
#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S)
|
||||
|
||||
@ -1522,6 +1522,7 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);",
|
||||
["stxp", "__ stxp(r4, zr, zr, r5);", "stxp\tw4, xzr, xzr, [x5]"],
|
||||
["stxpw", "__ stxpw(r6, zr, zr, sp);", "stxp\tw6, wzr, wzr, [sp]"],
|
||||
["dup", "__ dup(v0, __ T16B, zr);", "dup\tv0.16b, wzr"],
|
||||
["dup", "__ dup(v0, __ S, v1);", "dup\ts0, v1.s[0]"],
|
||||
["mov", "__ mov(v1, __ T1D, 0, zr);", "mov\tv1.d[0], xzr"],
|
||||
["mov", "__ mov(v1, __ T2S, 1, zr);", "mov\tv1.s[1], wzr"],
|
||||
["mov", "__ mov(v1, __ T4H, 2, zr);", "mov\tv1.h[2], wzr"],
|
||||
@ -1535,6 +1536,7 @@ generate(SpecialCases, [["ccmn", "__ ccmn(zr, zr, 3u, Assembler::LE);",
|
||||
["umov", "__ umov(r0, v1, __ B, 3);", "umov\tw0, v1.b[3]"],
|
||||
["fmov", "__ fmovhid(r0, v1);", "fmov\tx0, v1.d[1]"],
|
||||
["ld1", "__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0)));", "ld1\t{v31.2d, v0.2d}, [x1], x0"],
|
||||
["fcvtzs", "__ fcvtzs(v0, __ T4S, v1);", "fcvtzs\tv0.4s, v1.4s"],
|
||||
# SVE instructions
|
||||
["cpy", "__ sve_cpy(z0, __ S, p0, v1);", "mov\tz0.s, p0/m, s1"],
|
||||
["cpy", "__ sve_cpy(z0, __ B, p0, 127, true);", "mov\tz0.b, p0/m, 127"],
|
||||
@ -1750,7 +1752,8 @@ while i < len(bytes):
|
||||
i += 4
|
||||
if i%16 == 0:
|
||||
print
|
||||
print "\n };"
|
||||
print
|
||||
print " };"
|
||||
print "// END Generated code -- do not edit"
|
||||
|
||||
infile.close()
|
||||
|
||||
@ -712,6 +712,7 @@
|
||||
__ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5]
|
||||
__ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp]
|
||||
__ dup(v0, __ T16B, zr); // dup v0.16b, wzr
|
||||
__ dup(v0, __ S, v1); // dup s0, v1.s[0]
|
||||
__ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr
|
||||
__ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr
|
||||
__ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr
|
||||
@ -725,6 +726,7 @@
|
||||
__ umov(r0, v1, __ B, 3); // umov w0, v1.b[3]
|
||||
__ fmovhid(r0, v1); // fmov x0, v1.d[1]
|
||||
__ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0
|
||||
__ fcvtzs(v0, __ T4S, v1); // fcvtzs v0.4s, v1.4s
|
||||
__ sve_cpy(z0, __ S, p0, v1); // mov z0.s, p0/m, s1
|
||||
__ sve_cpy(z0, __ B, p0, 127, true); // mov z0.b, p0/m, 127
|
||||
__ sve_cpy(z1, __ H, p0, -128, true); // mov z1.h, p0/m, -128
|
||||
@ -1042,30 +1044,30 @@
|
||||
0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061,
|
||||
0x120cb166, 0x321764bc, 0x52174681, 0x720c0227,
|
||||
0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01,
|
||||
0x14000000, 0x17ffffd7, 0x1400034c, 0x94000000,
|
||||
0x97ffffd4, 0x94000349, 0x3400000a, 0x34fffa2a,
|
||||
0x340068ca, 0x35000008, 0x35fff9c8, 0x35006868,
|
||||
0xb400000b, 0xb4fff96b, 0xb400680b, 0xb500001d,
|
||||
0xb5fff91d, 0xb50067bd, 0x10000013, 0x10fff8b3,
|
||||
0x10006753, 0x90000013, 0x36300016, 0x3637f836,
|
||||
0x363066d6, 0x3758000c, 0x375ff7cc, 0x3758666c,
|
||||
0x14000000, 0x17ffffd7, 0x1400034e, 0x94000000,
|
||||
0x97ffffd4, 0x9400034b, 0x3400000a, 0x34fffa2a,
|
||||
0x3400690a, 0x35000008, 0x35fff9c8, 0x350068a8,
|
||||
0xb400000b, 0xb4fff96b, 0xb400684b, 0xb500001d,
|
||||
0xb5fff91d, 0xb50067fd, 0x10000013, 0x10fff8b3,
|
||||
0x10006793, 0x90000013, 0x36300016, 0x3637f836,
|
||||
0x36306716, 0x3758000c, 0x375ff7cc, 0x375866ac,
|
||||
0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc,
|
||||
0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f,
|
||||
0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016,
|
||||
0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0,
|
||||
0x54006440, 0x54000001, 0x54fff541, 0x540063e1,
|
||||
0x54000002, 0x54fff4e2, 0x54006382, 0x54000002,
|
||||
0x54fff482, 0x54006322, 0x54000003, 0x54fff423,
|
||||
0x540062c3, 0x54000003, 0x54fff3c3, 0x54006263,
|
||||
0x54000004, 0x54fff364, 0x54006204, 0x54000005,
|
||||
0x54fff305, 0x540061a5, 0x54000006, 0x54fff2a6,
|
||||
0x54006146, 0x54000007, 0x54fff247, 0x540060e7,
|
||||
0x54000008, 0x54fff1e8, 0x54006088, 0x54000009,
|
||||
0x54fff189, 0x54006029, 0x5400000a, 0x54fff12a,
|
||||
0x54005fca, 0x5400000b, 0x54fff0cb, 0x54005f6b,
|
||||
0x5400000c, 0x54fff06c, 0x54005f0c, 0x5400000d,
|
||||
0x54fff00d, 0x54005ead, 0x5400000e, 0x54ffefae,
|
||||
0x54005e4e, 0x5400000f, 0x54ffef4f, 0x54005def,
|
||||
0x54006480, 0x54000001, 0x54fff541, 0x54006421,
|
||||
0x54000002, 0x54fff4e2, 0x540063c2, 0x54000002,
|
||||
0x54fff482, 0x54006362, 0x54000003, 0x54fff423,
|
||||
0x54006303, 0x54000003, 0x54fff3c3, 0x540062a3,
|
||||
0x54000004, 0x54fff364, 0x54006244, 0x54000005,
|
||||
0x54fff305, 0x540061e5, 0x54000006, 0x54fff2a6,
|
||||
0x54006186, 0x54000007, 0x54fff247, 0x54006127,
|
||||
0x54000008, 0x54fff1e8, 0x540060c8, 0x54000009,
|
||||
0x54fff189, 0x54006069, 0x5400000a, 0x54fff12a,
|
||||
0x5400600a, 0x5400000b, 0x54fff0cb, 0x54005fab,
|
||||
0x5400000c, 0x54fff06c, 0x54005f4c, 0x5400000d,
|
||||
0x54fff00d, 0x54005eed, 0x5400000e, 0x54ffefae,
|
||||
0x54005e8e, 0x5400000f, 0x54ffef4f, 0x54005e2f,
|
||||
0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60,
|
||||
0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
|
||||
0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200,
|
||||
@ -1097,7 +1099,7 @@
|
||||
0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176,
|
||||
0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422,
|
||||
0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a,
|
||||
0xbd1b1869, 0x58004e3b, 0x1800000b, 0xf8945060,
|
||||
0xbd1b1869, 0x58004e7b, 0x1800000b, 0xf8945060,
|
||||
0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035,
|
||||
0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380,
|
||||
0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b11,
|
||||
@ -1182,78 +1184,78 @@
|
||||
0x6e2ee5ac, 0x6e7ee7bc, 0xba5fd3e3, 0x3a5f03e5,
|
||||
0xfa411be4, 0x7a42cbe2, 0x93df03ff, 0xc820ffff,
|
||||
0x8822fc7f, 0xc8247cbf, 0x88267fff, 0x4e010fe0,
|
||||
0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1,
|
||||
0x4e042c20, 0x4e062c20, 0x4e052c20, 0x4e083c20,
|
||||
0x0e0c3c20, 0x0e0a3c20, 0x0e073c20, 0x9eae0020,
|
||||
0x4cc0ac3f, 0x05a08020, 0x05104fe0, 0x05505001,
|
||||
0x05906fe2, 0x05d03005, 0x05101fea, 0x05901feb,
|
||||
0x04b0e3e0, 0x0470e7e1, 0x042f9c20, 0x043f9c35,
|
||||
0x047f9c20, 0x04ff9c20, 0x04299420, 0x04319160,
|
||||
0x0461943e, 0x04a19020, 0x042053ff, 0x047f5401,
|
||||
0x25208028, 0x2538cfe0, 0x2578d001, 0x25b8efe2,
|
||||
0x25f8f007, 0x2538dfea, 0x25b8dfeb, 0xa400a3e0,
|
||||
0xa420a7e0, 0xa4484be0, 0xa467afe0, 0xa4a8a7ea,
|
||||
0xa547a814, 0xa4084ffe, 0xa55c53e0, 0xa5e1540b,
|
||||
0xe400fbf6, 0xe408ffff, 0xe420e7e0, 0xe4484be0,
|
||||
0xe460efe0, 0xe547e400, 0xe4014be0, 0xe4a84fe0,
|
||||
0xe5f15000, 0x858043e0, 0x85a043ff, 0xe59f5d08,
|
||||
0x0420e3e9, 0x0460e3ea, 0x04a0e3eb, 0x04e0e3ec,
|
||||
0x25104042, 0x25104871, 0x25904861, 0x25904c92,
|
||||
0x05344020, 0x05744041, 0x05b44062, 0x05f44083,
|
||||
0x252c8840, 0x253c1420, 0x25681572, 0x25a21ce3,
|
||||
0x25ea1e34, 0x0522c020, 0x05e6c0a4, 0x2401a001,
|
||||
0x2443a051, 0x24858881, 0x24c78cd1, 0x24850891,
|
||||
0x24c70cc1, 0x250f9001, 0x25508051, 0x25802491,
|
||||
0x25df28c1, 0x25850c81, 0x251e10d1, 0x65816001,
|
||||
0x65c36051, 0x65854891, 0x65c74cc1, 0x05733820,
|
||||
0x05b238a4, 0x05f138e6, 0x0570396a, 0x65d0a001,
|
||||
0x65d6a443, 0x65d4a826, 0x6594ac26, 0x6554ac26,
|
||||
0x6556ac26, 0x6552ac26, 0x65cbac85, 0x65caac01,
|
||||
0x65dea833, 0x659ca509, 0x65d8a801, 0x65dcac01,
|
||||
0x655cb241, 0x0520a1e0, 0x0521a601, 0x052281e0,
|
||||
0x05238601, 0x04a14026, 0x0568aca7, 0x05b23230,
|
||||
0x853040af, 0xc5b040af, 0xe57080af, 0xe5b080af,
|
||||
0x1e601000, 0x1e603000, 0x1e621000, 0x1e623000,
|
||||
0x1e641000, 0x1e643000, 0x1e661000, 0x1e663000,
|
||||
0x1e681000, 0x1e683000, 0x1e6a1000, 0x1e6a3000,
|
||||
0x1e6c1000, 0x1e6c3000, 0x1e6e1000, 0x1e6e3000,
|
||||
0x1e701000, 0x1e703000, 0x1e721000, 0x1e723000,
|
||||
0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000,
|
||||
0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000,
|
||||
0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000,
|
||||
0xf8208193, 0xf83101b6, 0xf83c13fe, 0xf821239a,
|
||||
0xf824309e, 0xf826535e, 0xf8304109, 0xf82c7280,
|
||||
0xf8216058, 0xf8a08309, 0xf8ba03d0, 0xf8a312ea,
|
||||
0xf8aa21e4, 0xf8a2310b, 0xf8aa522f, 0xf8a2418a,
|
||||
0xf8ac71af, 0xf8a26287, 0xf8fa8090, 0xf8e20184,
|
||||
0xf8f01215, 0xf8f022ab, 0xf8f7334c, 0xf8f751dc,
|
||||
0xf8eb4038, 0xf8ec715f, 0xf8f06047, 0xf863826d,
|
||||
0xf8710070, 0xf86113cb, 0xf86521e8, 0xf87d301e,
|
||||
0xf8745287, 0xf87742bc, 0xf87b70b9, 0xf8616217,
|
||||
0xb83f8185, 0xb82901fc, 0xb83d13f6, 0xb83320bf,
|
||||
0xb82e33f0, 0xb830529b, 0xb830416c, 0xb82973c6,
|
||||
0xb831639b, 0xb8be8147, 0xb8b4008a, 0xb8b81231,
|
||||
0xb8b623a3, 0xb8af3276, 0xb8b35056, 0xb8af4186,
|
||||
0xb8b071ab, 0xb8b763c1, 0xb8f38225, 0xb8e202d0,
|
||||
0xb8ed12aa, 0xb8fd219b, 0xb8fb3023, 0xb8ff5278,
|
||||
0xb8f14389, 0xb8fb70ef, 0xb8f563f7, 0xb87983e2,
|
||||
0xb87b0150, 0xb8771073, 0xb8702320, 0xb87a3057,
|
||||
0xb870508c, 0xb87c43be, 0xb87070db, 0xb86961fd,
|
||||
0xce273c87, 0xce080ac9, 0xce7e8e9b, 0xce808b45,
|
||||
0xce79806e, 0xce758768, 0xcec0835a, 0xce608ad8,
|
||||
0x043100c4, 0x046105e3, 0x65c900a6, 0x65d60a87,
|
||||
0x65c80545, 0x0416a63e, 0x04001f8b, 0x0450979a,
|
||||
0x04dabe0d, 0x045381a5, 0x04918b4f, 0x049006cb,
|
||||
0x0497a264, 0x045eadd1, 0x04881062, 0x040a04d7,
|
||||
0x04810f71, 0x04dca450, 0x65c084c3, 0x65cd8d93,
|
||||
0x65c69a68, 0x65878ae0, 0x65c29db3, 0x049da0e6,
|
||||
0x6582b911, 0x65c0b6d6, 0x65c1a1e2, 0x65cda494,
|
||||
0x65c18107, 0x65af1493, 0x65e52b36, 0x65ab4ed0,
|
||||
0x65f06a8d, 0x0451448f, 0x049c7c86, 0x0429335d,
|
||||
0x04bc3162, 0x047a3027, 0x04e831d1, 0x05a56b15,
|
||||
0x05b66e35, 0x041a367d, 0x041832e4, 0x04d926f3,
|
||||
0x04482113, 0x04ca3a2e, 0x658727d5, 0x6586358a,
|
||||
0x65d82709, 0x044138c4,
|
||||
0x5e040420, 0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1,
|
||||
0x4e071fe1, 0x4e042c20, 0x4e062c20, 0x4e052c20,
|
||||
0x4e083c20, 0x0e0c3c20, 0x0e0a3c20, 0x0e073c20,
|
||||
0x9eae0020, 0x4cc0ac3f, 0x4ea1b820, 0x05a08020,
|
||||
0x05104fe0, 0x05505001, 0x05906fe2, 0x05d03005,
|
||||
0x05101fea, 0x05901feb, 0x04b0e3e0, 0x0470e7e1,
|
||||
0x042f9c20, 0x043f9c35, 0x047f9c20, 0x04ff9c20,
|
||||
0x04299420, 0x04319160, 0x0461943e, 0x04a19020,
|
||||
0x042053ff, 0x047f5401, 0x25208028, 0x2538cfe0,
|
||||
0x2578d001, 0x25b8efe2, 0x25f8f007, 0x2538dfea,
|
||||
0x25b8dfeb, 0xa400a3e0, 0xa420a7e0, 0xa4484be0,
|
||||
0xa467afe0, 0xa4a8a7ea, 0xa547a814, 0xa4084ffe,
|
||||
0xa55c53e0, 0xa5e1540b, 0xe400fbf6, 0xe408ffff,
|
||||
0xe420e7e0, 0xe4484be0, 0xe460efe0, 0xe547e400,
|
||||
0xe4014be0, 0xe4a84fe0, 0xe5f15000, 0x858043e0,
|
||||
0x85a043ff, 0xe59f5d08, 0x0420e3e9, 0x0460e3ea,
|
||||
0x04a0e3eb, 0x04e0e3ec, 0x25104042, 0x25104871,
|
||||
0x25904861, 0x25904c92, 0x05344020, 0x05744041,
|
||||
0x05b44062, 0x05f44083, 0x252c8840, 0x253c1420,
|
||||
0x25681572, 0x25a21ce3, 0x25ea1e34, 0x0522c020,
|
||||
0x05e6c0a4, 0x2401a001, 0x2443a051, 0x24858881,
|
||||
0x24c78cd1, 0x24850891, 0x24c70cc1, 0x250f9001,
|
||||
0x25508051, 0x25802491, 0x25df28c1, 0x25850c81,
|
||||
0x251e10d1, 0x65816001, 0x65c36051, 0x65854891,
|
||||
0x65c74cc1, 0x05733820, 0x05b238a4, 0x05f138e6,
|
||||
0x0570396a, 0x65d0a001, 0x65d6a443, 0x65d4a826,
|
||||
0x6594ac26, 0x6554ac26, 0x6556ac26, 0x6552ac26,
|
||||
0x65cbac85, 0x65caac01, 0x65dea833, 0x659ca509,
|
||||
0x65d8a801, 0x65dcac01, 0x655cb241, 0x0520a1e0,
|
||||
0x0521a601, 0x052281e0, 0x05238601, 0x04a14026,
|
||||
0x0568aca7, 0x05b23230, 0x853040af, 0xc5b040af,
|
||||
0xe57080af, 0xe5b080af, 0x1e601000, 0x1e603000,
|
||||
0x1e621000, 0x1e623000, 0x1e641000, 0x1e643000,
|
||||
0x1e661000, 0x1e663000, 0x1e681000, 0x1e683000,
|
||||
0x1e6a1000, 0x1e6a3000, 0x1e6c1000, 0x1e6c3000,
|
||||
0x1e6e1000, 0x1e6e3000, 0x1e701000, 0x1e703000,
|
||||
0x1e721000, 0x1e723000, 0x1e741000, 0x1e743000,
|
||||
0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000,
|
||||
0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000,
|
||||
0x1e7e1000, 0x1e7e3000, 0xf8208193, 0xf83101b6,
|
||||
0xf83c13fe, 0xf821239a, 0xf824309e, 0xf826535e,
|
||||
0xf8304109, 0xf82c7280, 0xf8216058, 0xf8a08309,
|
||||
0xf8ba03d0, 0xf8a312ea, 0xf8aa21e4, 0xf8a2310b,
|
||||
0xf8aa522f, 0xf8a2418a, 0xf8ac71af, 0xf8a26287,
|
||||
0xf8fa8090, 0xf8e20184, 0xf8f01215, 0xf8f022ab,
|
||||
0xf8f7334c, 0xf8f751dc, 0xf8eb4038, 0xf8ec715f,
|
||||
0xf8f06047, 0xf863826d, 0xf8710070, 0xf86113cb,
|
||||
0xf86521e8, 0xf87d301e, 0xf8745287, 0xf87742bc,
|
||||
0xf87b70b9, 0xf8616217, 0xb83f8185, 0xb82901fc,
|
||||
0xb83d13f6, 0xb83320bf, 0xb82e33f0, 0xb830529b,
|
||||
0xb830416c, 0xb82973c6, 0xb831639b, 0xb8be8147,
|
||||
0xb8b4008a, 0xb8b81231, 0xb8b623a3, 0xb8af3276,
|
||||
0xb8b35056, 0xb8af4186, 0xb8b071ab, 0xb8b763c1,
|
||||
0xb8f38225, 0xb8e202d0, 0xb8ed12aa, 0xb8fd219b,
|
||||
0xb8fb3023, 0xb8ff5278, 0xb8f14389, 0xb8fb70ef,
|
||||
0xb8f563f7, 0xb87983e2, 0xb87b0150, 0xb8771073,
|
||||
0xb8702320, 0xb87a3057, 0xb870508c, 0xb87c43be,
|
||||
0xb87070db, 0xb86961fd, 0xce273c87, 0xce080ac9,
|
||||
0xce7e8e9b, 0xce808b45, 0xce79806e, 0xce758768,
|
||||
0xcec0835a, 0xce608ad8, 0x043100c4, 0x046105e3,
|
||||
0x65c900a6, 0x65d60a87, 0x65c80545, 0x0416a63e,
|
||||
0x04001f8b, 0x0450979a, 0x04dabe0d, 0x045381a5,
|
||||
0x04918b4f, 0x049006cb, 0x0497a264, 0x045eadd1,
|
||||
0x04881062, 0x040a04d7, 0x04810f71, 0x04dca450,
|
||||
0x65c084c3, 0x65cd8d93, 0x65c69a68, 0x65878ae0,
|
||||
0x65c29db3, 0x049da0e6, 0x6582b911, 0x65c0b6d6,
|
||||
0x65c1a1e2, 0x65cda494, 0x65c18107, 0x65af1493,
|
||||
0x65e52b36, 0x65ab4ed0, 0x65f06a8d, 0x0451448f,
|
||||
0x049c7c86, 0x0429335d, 0x04bc3162, 0x047a3027,
|
||||
0x04e831d1, 0x05a56b15, 0x05b66e35, 0x041a367d,
|
||||
0x041832e4, 0x04d926f3, 0x04482113, 0x04ca3a2e,
|
||||
0x658727d5, 0x6586358a, 0x65d82709, 0x044138c4,
|
||||
|
||||
};
|
||||
// END Generated code -- do not edit
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user