From a7a09f69abc6c4730599d3de9067c2fde75c5172 Mon Sep 17 00:00:00 2001
From: Anjian-Wen <wenanjian@bytedance.com>
Date: Fri, 14 Mar 2025 05:53:04 +0000
Subject: [PATCH] =?UTF-8?q?8349632:=20RISC-V:=20Add=20Zfa=C2=A0fminm/fmaxm?=
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Reviewed-by: fyang
---
 src/hotspot/cpu/riscv/assembler_riscv.hpp | 20 ++++++++
 src/hotspot/cpu/riscv/riscv.ad            | 60 +++++++++++++++++++++++
 2 files changed, 80 insertions(+)

diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
index a08550b7137..8b4d013b0d7 100644
--- a/src/hotspot/cpu/riscv/assembler_riscv.hpp
+++ b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -1450,6 +1450,26 @@ enum operand_size { int8, int16, int32, uint32, int64 };
     fp_base<D_64_dp, 0b11110>(Rd, Rs1, 0b00001, 0b000);
   }
 
+  void fminm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b010);
+  }
+
+  void fmaxm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b011);
+  }
+
+  void fminm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b010);
+  }
+
+  void fmaxm_d(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
+    assert_cond(UseZfa);
+    fp_base<D_64_dp, 0b00101>(Rd, Rs1, Rs2, 0b011);
+  }
+
 // ==========================
 // RISC-V Vector Extension
 // ==========================
diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
index cecca0a5402..08b777085b1 100644
--- a/src/hotspot/cpu/riscv/riscv.ad
+++ b/src/hotspot/cpu/riscv/riscv.ad
@@ -7349,6 +7349,7 @@ instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
 
 // Math.max(FF)F
 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MaxF src1 src2));
   effect(KILL cr);
 
@@ -7363,8 +7364,23 @@ instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  predicate(UseZfa);
+  match(Set dst (MaxF src1 src2));
+
+  format %{ "maxF $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fmaxm_s(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Math.min(FF)F
 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MinF src1 src2));
   effect(KILL cr);
 
@@ -7379,8 +7395,23 @@ instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
+  predicate(UseZfa);
+  match(Set dst (MinF src1 src2));
+
+  format %{ "minF $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fminm_s(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Math.max(DD)D
 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MaxD src1 src2));
   effect(KILL cr);
 
@@ -7395,8 +7426,23 @@ instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  predicate(UseZfa);
+  match(Set dst (MaxD src1 src2));
+
+  format %{ "maxD $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fmaxm_d(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Math.min(DD)D
 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
+  predicate(!UseZfa);
   match(Set dst (MinD src1 src2));
   effect(KILL cr);
 
@@ -7411,6 +7457,20 @@ instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
   ins_pipe(pipe_class_default);
 %}
 
+instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
+  predicate(UseZfa);
+  match(Set dst (MinD src1 src2));
+
+  format %{ "minD $dst, $src1, $src2" %}
+
+  ins_encode %{
+    __ fminm_d(as_FloatRegister($dst$$reg),
+               as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
+  %}
+
+  ins_pipe(pipe_class_default);
+%}
+
 // Float.isInfinite
 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
 %{