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8172850: Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
Regression test and additional asserts. The problem is fixed by 8087341. Reviewed-by: kvn
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@ -2097,6 +2097,7 @@ const RegMask &PhiNode::out_RegMask() const {
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uint ideal_reg = _type->ideal_reg();
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assert( ideal_reg != Node::NotAMachineReg, "invalid type at Phi" );
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if( ideal_reg == 0 ) return RegMask::Empty;
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assert(ideal_reg != Op_RegFlags, "flags register is not spillable");
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return *(Compile::current()->matcher()->idealreg2spillmask[ideal_reg]);
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}
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@ -292,7 +292,14 @@ void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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// Copy any flags as well
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_phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
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} else {
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const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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int ireg = m->ideal_reg();
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if (ireg == 0 || ireg == Op_RegFlags) {
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assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
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m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::PhiInput));
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C->record_method_not_compilable("attempted to spill a non-spillable item");
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return;
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}
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const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
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copy = new MachSpillCopyNode(MachSpillCopyNode::PhiInput, m, *rm, *rm);
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// Find a good place to insert. Kinda tricky, use a subroutine
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insert_copy_with_overlap(pred,copy,phi_name,src_name);
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@ -326,7 +333,14 @@ void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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b->insert_node(copy, l++);
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l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
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} else {
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const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
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int ireg = m->ideal_reg();
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if (ireg == 0 || ireg == Op_RegFlags) {
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assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
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m->_idx, m->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::TwoAddress));
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C->record_method_not_compilable("attempted to spill a non-spillable item");
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return;
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}
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const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
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copy = new MachSpillCopyNode(MachSpillCopyNode::TwoAddress, m, *rm, *rm);
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// Insert the copy in the basic block, just before us
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b->insert_node(copy, l++);
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@ -373,7 +387,14 @@ void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
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if( k < b->_num_succs )
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continue; // Live out; do not pre-split
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// Split the lrg at this use
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const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
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int ireg = inp->ideal_reg();
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if (ireg == 0 || ireg == Op_RegFlags) {
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assert(false, "attempted to spill a non-spillable item: %d: %s, ireg = %d, spill_type: %s",
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inp->_idx, inp->Name(), ireg, MachSpillCopyNode::spill_type(MachSpillCopyNode::DebugUse));
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C->record_method_not_compilable("attempted to spill a non-spillable item");
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return;
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}
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const RegMask *rm = C->matcher()->idealreg2spillmask[ireg];
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Node* copy = new MachSpillCopyNode(MachSpillCopyNode::DebugUse, inp, *rm, *rm);
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// Insert the copy in the use-def chain
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n->set_req(inpidx, copy );
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@ -643,6 +643,7 @@ const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
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}
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// Values outside the domain represent debug info
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assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
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return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
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}
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@ -85,6 +85,7 @@ Matcher::Matcher()
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idealreg2spillmask [Op_VecX] = NULL;
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idealreg2spillmask [Op_VecY] = NULL;
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idealreg2spillmask [Op_VecZ] = NULL;
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idealreg2spillmask [Op_RegFlags] = NULL;
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idealreg2debugmask [Op_RegI] = NULL;
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idealreg2debugmask [Op_RegN] = NULL;
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@ -97,6 +98,7 @@ Matcher::Matcher()
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idealreg2debugmask [Op_VecX] = NULL;
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idealreg2debugmask [Op_VecY] = NULL;
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idealreg2debugmask [Op_VecZ] = NULL;
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idealreg2debugmask [Op_RegFlags] = NULL;
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idealreg2mhdebugmask[Op_RegI] = NULL;
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idealreg2mhdebugmask[Op_RegN] = NULL;
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@ -109,6 +111,7 @@ Matcher::Matcher()
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idealreg2mhdebugmask[Op_VecX] = NULL;
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idealreg2mhdebugmask[Op_VecY] = NULL;
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idealreg2mhdebugmask[Op_VecZ] = NULL;
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idealreg2mhdebugmask[Op_RegFlags] = NULL;
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debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
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}
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101
hotspot/test/compiler/gcbarriers/TestMembarDependencies.java
Normal file
101
hotspot/test/compiler/gcbarriers/TestMembarDependencies.java
Normal file
@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 only, as
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* published by the Free Software Foundation.
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*
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* This code is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* version 2 for more details (a copy is included in the LICENSE file that
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* accompanied this code).
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*
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* You should have received a copy of the GNU General Public License version
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* 2 along with this work; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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* or visit www.oracle.com if you need additional information or have any
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* questions.
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*/
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/*
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* @test TestMembarDependencies
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* @bug 8172850
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* @summary Tests correct scheduling of memory loads around MembarVolatile emitted by GC barriers.
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* @library /test/lib /
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* @modules java.base/jdk.internal.misc
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* java.management
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* @run driver compiler.membars.TestMembarDependencies
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*/
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package compiler.membars;
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import jdk.test.lib.process.OutputAnalyzer;
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import jdk.test.lib.process.ProcessTools;
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public class TestMembarDependencies {
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private static TestMembarDependencies f1;
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private static TestMembarDependencies f2;
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public static void main(String args[]) throws Exception {
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if (args.length == 0) {
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// For debugging, add "-XX:+TraceOptoPipelining"
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OutputAnalyzer oa = ProcessTools.executeTestJvm("-XX:+IgnoreUnrecognizedVMOptions",
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"-XX:-TieredCompilation", "-XX:-BackgroundCompilation", "-XX:+PrintOpto",
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"-XX:CompileCommand=compileonly,compiler.membars.TestMembarDependencies::test*",
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"-XX:CompileCommand=dontinline,compiler.membars.TestMembarDependencies::test_m1",
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TestMembarDependencies.class.getName(), "run");
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// C2 should not crash or bail out from compilation
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oa.shouldHaveExitValue(0);
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oa.shouldNotMatch("Bailout: Recompile without subsuming loads");
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System.out.println(oa.getOutput());
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} else {
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f2 = new TestMembarDependencies();
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// Trigger compilation of test1 and test2
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for (int i = 0; i < 10_000; ++i) {
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f2.test1(f2);
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f2.test2(f2);
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}
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}
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}
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public void test_m1() { }
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public void test_m2() { }
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public void test1(TestMembarDependencies obj) {
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// Try/catch/finally is used to create a CFG block without a test + jmpCon
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// allowing GCM to schedule the testN_mem_reg0 instruction into that block.
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try {
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// Method call defines memory state that is then
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// used by subsequent instructions/blocks (see below).
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test_m1();
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} catch (Exception e) {
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} finally {
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// Oop write to field emits a GC post-barrier with a MembarVolatile
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// which has a wide memory effect (kills all memory). This creates an
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// anti-dependency on all surrounding memory loads.
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f1 = obj;
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}
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// The empty method m2 is inlined but the null check of f2 remains. It is encoded
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// as CmpN(LoadN(MEM), NULL) where MEM is the memory after the call to test_m1().
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// This is matched to testN_mem_reg0 on x86 which is scheduled before the barrier
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// in the try/catch block due to the anti-dependency on the MembarVolatile.
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// C2 crashes in the register allocator when trying to spill the flag register
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// to keep the result of the testN instruction live from the try/catch block
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// until it is here.
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f2.test_m2();
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}
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public void test2(TestMembarDependencies obj) {
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// Same as test1 but without try/catch/finally.
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// This causes C2 to bail out in block local scheduling because testN_mem_reg0 is
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// scheduled into a block that already contains another test + jmpCon instruction.
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test_m1();
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f1 = obj;
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f2.test_m2();
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}
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}
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