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Merge
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commit
aa49aa7eab
@ -565,3 +565,4 @@ b2d0a906afd73dcf27f572217eb1be0f196ec16c jdk-9+157
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94b4e2e5331d38eab6a3639c3511b2e0715df0e9 jdk-9+160
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191ffbdb3d7b734288daa7fb76b37a0a85dfe7eb jdk-9+161
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b01c519b715ef6f785d0631adee0a6537cf6c12e jdk-9+162
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983fe207555724d98f4876991e1cbafbcf2733e8 jdk-9+163
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@ -15501,7 +15501,7 @@ instruct string_compareLU(iRegP_R1 str1, iRegI_R2 cnt1, iRegP_R3 str2, iRegI_R4
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%}
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instruct string_indexofUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
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iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
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@ -15520,7 +15520,7 @@ instruct string_indexofUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2
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%}
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instruct string_indexofLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
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iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
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@ -15539,7 +15539,7 @@ instruct string_indexofLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2
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%}
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instruct string_indexofUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
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iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
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@ -15558,7 +15558,7 @@ instruct string_indexofUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2
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%}
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instruct string_indexofLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2 cnt2,
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iRegI_R0 result, iRegI tmp1, iRegI tmp2, iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LU);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
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@ -15577,8 +15577,8 @@ instruct string_indexofLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2, iRegI_R2
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%}
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instruct string_indexof_conUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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immI_le_4 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
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iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
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iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
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@ -15598,8 +15598,8 @@ instruct string_indexof_conUU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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%}
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instruct string_indexof_conLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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immI_le_4 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
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iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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immI_le_4 int_cnt2, iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
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iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
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@ -15619,8 +15619,8 @@ instruct string_indexof_conLL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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%}
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instruct string_indexof_conUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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immI_1 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
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iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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immI_1 int_cnt2, iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
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iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
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@ -15640,8 +15640,8 @@ instruct string_indexof_conUL(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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%}
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instruct string_indexof_conLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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immI_1 int_cnt2, iRegI_R0 result, iRegI tmp1, iRegI tmp2,
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iRegI tmp3, iRegI tmp4, rFlagsReg cr)
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immI_1 int_cnt2, iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
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iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
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%{
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predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LU);
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match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
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@ -15661,8 +15661,8 @@ instruct string_indexof_conLU(iRegP_R1 str1, iRegI_R4 cnt1, iRegP_R3 str2,
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%}
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instruct string_indexofU_char(iRegP_R1 str1, iRegI_R2 cnt1, iRegI_R3 ch,
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iRegI_R0 result, iRegI tmp1, iRegI tmp2,
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iRegI tmp3, rFlagsReg cr)
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iRegI_R0 result, iRegINoSp tmp1, iRegINoSp tmp2,
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iRegINoSp tmp3, rFlagsReg cr)
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%{
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match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
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effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch,
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@ -16101,7 +16101,7 @@ instruct replicate2D(vecX dst, vRegD src)
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// ====================REDUCTION ARITHMETIC====================================
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instruct reduce_add2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp, iRegI tmp2)
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instruct reduce_add2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegINoSp tmp, iRegINoSp tmp2)
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%{
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match(Set dst (AddReductionVI src1 src2));
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ins_cost(INSN_COST);
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@ -16120,7 +16120,7 @@ instruct reduce_add2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp, iReg
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ins_pipe(pipe_class_default);
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%}
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instruct reduce_add4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegI tmp2)
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instruct reduce_add4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegINoSp tmp2)
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%{
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match(Set dst (AddReductionVI src1 src2));
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ins_cost(INSN_COST);
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@ -16138,7 +16138,7 @@ instruct reduce_add4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegI
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ins_pipe(pipe_class_default);
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%}
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instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp)
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instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegINoSp tmp)
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%{
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match(Set dst (MulReductionVI src1 src2));
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ins_cost(INSN_COST);
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@ -16157,7 +16157,7 @@ instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegI tmp)
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ins_pipe(pipe_class_default);
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%}
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instruct reduce_mul4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegI tmp2)
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instruct reduce_mul4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, vecX tmp, iRegINoSp tmp2)
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%{
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match(Set dst (MulReductionVI src1 src2));
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ins_cost(INSN_COST);
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@ -225,7 +225,10 @@ Node *CastIINode::Ideal(PhaseGVN *phase, bool can_reshape) {
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}
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// Similar to ConvI2LNode::Ideal() for the same reasons
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if (can_reshape && !phase->C->major_progress()) {
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// Do not narrow the type of range check dependent CastIINodes to
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// avoid corruption of the graph if a CastII is replaced by TOP but
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// the corresponding range check is not removed.
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if (can_reshape && !_range_check_dependency && !phase->C->major_progress()) {
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const TypeInt* this_type = this->type()->is_int();
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const TypeInt* in_type = phase->type(in(1))->isa_int();
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if (in_type != NULL && this_type != NULL &&
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@ -294,8 +294,7 @@ Node *ConvI2LNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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}
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#ifdef _LP64
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// Convert ConvI2L(AddI(x, y)) to AddL(ConvI2L(x), ConvI2L(y)) or
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// ConvI2L(CastII(AddI(x, y))) to AddL(ConvI2L(CastII(x)), ConvI2L(CastII(y))),
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// Convert ConvI2L(AddI(x, y)) to AddL(ConvI2L(x), ConvI2L(y))
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// but only if x and y have subranges that cannot cause 32-bit overflow,
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// under the assumption that x+y is in my own subrange this->type().
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@ -319,13 +318,6 @@ Node *ConvI2LNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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Node* z = in(1);
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int op = z->Opcode();
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Node* ctrl = NULL;
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if (op == Op_CastII && z->as_CastII()->has_range_check()) {
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// Skip CastII node but save control dependency
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ctrl = z->in(0);
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z = z->in(1);
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op = z->Opcode();
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}
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if (op == Op_AddI || op == Op_SubI) {
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Node* x = z->in(1);
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Node* y = z->in(2);
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@ -385,8 +377,8 @@ Node *ConvI2LNode::Ideal(PhaseGVN *phase, bool can_reshape) {
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}
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assert(rxlo == (int)rxlo && rxhi == (int)rxhi, "x should not overflow");
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assert(rylo == (int)rylo && ryhi == (int)ryhi, "y should not overflow");
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Node* cx = phase->C->constrained_convI2L(phase, x, TypeInt::make(rxlo, rxhi, widen), ctrl);
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Node* cy = phase->C->constrained_convI2L(phase, y, TypeInt::make(rylo, ryhi, widen), ctrl);
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Node* cx = phase->C->constrained_convI2L(phase, x, TypeInt::make(rxlo, rxhi, widen), NULL);
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Node* cy = phase->C->constrained_convI2L(phase, y, TypeInt::make(rylo, ryhi, widen), NULL);
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switch (op) {
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case Op_AddI: return new AddLNode(cx, cy);
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case Op_SubI: return new SubLNode(cx, cy);
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@ -2372,7 +2372,7 @@ bool LibraryCallKit::inline_unsafe_access(bool is_store, const BasicType type, c
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// the barriers get omitted and the unsafe reference begins to "pollute"
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// the alias analysis of the rest of the graph, either Compile::can_alias
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// or Compile::must_alias will throw a diagnostic assert.)
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bool need_mem_bar;
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bool need_mem_bar = false;
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switch (kind) {
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case Relaxed:
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need_mem_bar = mismatched && !adr_type->isa_aryptr();
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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*
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* This code is free software; you can redistribute it and/or modify it
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@ -23,7 +23,7 @@
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/*
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* @test
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* @bug 8078262
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* @bug 8078262 8177095
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* @summary Tests correct dominator information after loop peeling.
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*
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* @run main/othervm -Xcomp
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@ -40,14 +40,16 @@ public class TestLoopPeeling {
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public static void main(String args[]) {
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TestLoopPeeling test = new TestLoopPeeling();
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try {
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test.testArrayAccess(0, 1);
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test.testArrayAccess1(0, 1);
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test.testArrayAccess2(0);
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test.testArrayAccess3(0, false);
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test.testArrayAllocation(0, 1);
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} catch (Exception e) {
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// Ignore exceptions
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}
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}
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public void testArrayAccess(int index, int inc) {
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public void testArrayAccess1(int index, int inc) {
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int storeIndex = -1;
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for (; index < 10; index += inc) {
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@ -63,7 +65,7 @@ public class TestLoopPeeling {
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if (index == 42) {
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// This store and the corresponding range check are moved out of the
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// loop and both used after old loop and the peeled iteration exit.
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// loop and both used after main loop and the peeled iteration exit.
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// For the peeled iteration, storeIndex is always -1 and the ConvI2L
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// is replaced by TOP. However, the range check is not folded because
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// we don't do the split if optimization in PhaseIdealLoop2.
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@ -77,6 +79,44 @@ public class TestLoopPeeling {
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}
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}
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public int testArrayAccess2(int index) {
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// Load1 and the corresponding range check are moved out of the loop
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// and both are used after the main loop and the peeled iteration exit.
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// For the peeled iteration, storeIndex is always Integer.MIN_VALUE and
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// for the main loop it is 0. Hence, the merging phi has type int:<=0.
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// Load1 reads the array at index ConvI2L(CastII(AddI(storeIndex, -1)))
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// where the CastII is range check dependent and has type int:>=0.
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// The CastII gets pushed through the AddI and its type is changed to int:>=1
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// which does not overlap with the input type of storeIndex (int:<=0).
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// The CastII is replaced by TOP causing a cascade of other eliminations.
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// Since the control path through the range check CmpU(AddI(storeIndex, -1))
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// is not eliminated, the graph is in a corrupted state. We fail once we merge
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// with the result of Load2 because we get data from a non-dominating region.
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int storeIndex = Integer.MIN_VALUE;
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for (; index < 10; ++index) {
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if (index == 42) {
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return array[storeIndex-1]; // Load1
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}
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storeIndex = 0;
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}
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return array[42]; // Load2
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}
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public int testArrayAccess3(int index, boolean b) {
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// Same as testArrayAccess2 but manifests as crash in register allocator.
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int storeIndex = Integer.MIN_VALUE;
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for (; index < 10; ++index) {
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if (b) {
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return 0;
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}
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if (index == 42) {
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return array[storeIndex-1]; // Load1
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}
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storeIndex = 0;
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}
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return array[42]; // Load2
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}
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public byte[] testArrayAllocation(int index, int inc) {
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int allocationCount = -1;
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byte[] result;
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@ -88,7 +128,7 @@ public class TestLoopPeeling {
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if (index == 42) {
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// This allocation and the corresponding size check are moved out of the
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// loop and both used after old loop and the peeled iteration exit.
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// loop and both used after main loop and the peeled iteration exit.
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// For the peeled iteration, allocationCount is always -1 and the ConvI2L
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// is replaced by TOP. However, the size check is not folded because
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// we don't do the split if optimization in PhaseIdealLoop2.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
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* Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
|
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
|
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*
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* This code is free software; you can redistribute it and/or modify it
|
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@ -183,7 +183,7 @@ jvmtiError get_module(JNIEnv *env,
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err = (*jvmti)->GetNamedModule(jvmti, loader, pkg_name, module_ptr);
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if (err != JVMTI_ERROR_NONE) {
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printf(" Error in GetNamedModule for package \"%s\": %s (%d)\n",
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pkg_name, TranslateError(err), err);
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name, TranslateError(err), err);
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return err;
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}
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printf(" returned module: %p\n", *module_ptr);
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