diff --git a/src/hotspot/cpu/riscv/frame_riscv.hpp b/src/hotspot/cpu/riscv/frame_riscv.hpp index 15fe0e8f1f8..3692c99193e 100644 --- a/src/hotspot/cpu/riscv/frame_riscv.hpp +++ b/src/hotspot/cpu/riscv/frame_riscv.hpp @@ -131,7 +131,7 @@ // Entry frames // n.b. these values are determined by the layout defined in // stubGenerator for the Java call stub - entry_frame_after_call_words = 34, + entry_frame_after_call_words = 35, entry_frame_call_wrapper_offset = -10, // we don't need a save area diff --git a/src/hotspot/cpu/riscv/riscv_v.ad b/src/hotspot/cpu/riscv/riscv_v.ad index 36f4d499c38..86309ec9128 100644 --- a/src/hotspot/cpu/riscv/riscv_v.ad +++ b/src/hotspot/cpu/riscv/riscv_v.ad @@ -2986,7 +2986,6 @@ instruct vloadcon(vReg dst, immI0 src) %{ __ vsetvli_helper(bt, Matcher::vector_length(this)); __ vid_v(as_VectorRegister($dst$$reg)); if (is_floating_point_type(bt)) { - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); } %} @@ -3201,7 +3200,6 @@ instruct vcvtBtoX(vReg dst, vReg src) %{ __ integer_extend_v(as_VectorRegister($dst$$reg), bt == T_FLOAT ? T_INT : T_LONG, Matcher::vector_length(this), as_VectorRegister($src$$reg), T_BYTE, true /* is_signed */); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); } else { __ integer_extend_v(as_VectorRegister($dst$$reg), bt, @@ -3267,7 +3265,6 @@ instruct vcvtStoX_fp(vReg dst, vReg src) %{ Matcher::vector_length(this), as_VectorRegister($src$$reg), T_SHORT, true /* is_signed */); __ vsetvli_helper(bt, Matcher::vector_length(this)); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($dst$$reg)); %} ins_pipe(pipe_slow); @@ -3335,7 +3332,6 @@ instruct vcvtItoF(vReg dst, vReg src) %{ format %{ "vcvtItoF $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this)); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -3348,7 +3344,6 @@ instruct vcvtItoD(vReg dst, vReg src) %{ format %{ "vcvtItoD $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_INT, Matcher::vector_length(this), Assembler::mf2); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfwcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -3376,7 +3371,6 @@ instruct vcvtLtoF(vReg dst, vReg src) %{ format %{ "vcvtLtoF $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfncvt_f_x_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -3388,7 +3382,6 @@ instruct vcvtLtoD(vReg dst, vReg src) %{ format %{ "vcvtLtoD $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_DOUBLE, Matcher::vector_length(this)); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfcvt_f_x_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -3446,7 +3439,6 @@ instruct vcvtFtoD(vReg dst, vReg src) %{ format %{ "vcvtFtoD $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfwcvt_f_f_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); @@ -3494,7 +3486,6 @@ instruct vcvtDtoF(vReg dst, vReg src) %{ format %{ "vcvtDtoF $dst, $src" %} ins_encode %{ __ vsetvli_helper(T_FLOAT, Matcher::vector_length(this), Assembler::mf2); - __ csrwi(CSR_FRM, C2_MacroAssembler::rne); __ vfncvt_f_f_w(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg)); %} ins_pipe(pipe_slow); diff --git a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp index df447abaa06..7ee17438b28 100644 --- a/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp +++ b/src/hotspot/cpu/riscv/stubGenerator_riscv.cpp @@ -127,8 +127,9 @@ class StubGenerator: public StubCodeGenerator { // [ return_from_Java ] <--- sp // [ argument word n ] // ... - // -34 [ argument word 1 ] - // -33 [ saved f27 ] <--- sp_after_call + // -35 [ argument word 1 ] + // -34 [ saved FRM in Floating-point Control and Status Register ] <--- sp_after_call + // -33 [ saved f27 ] // -32 [ saved f26 ] // -31 [ saved f25 ] // -30 [ saved f24 ] @@ -165,8 +166,9 @@ class StubGenerator: public StubCodeGenerator { // Call stub stack layout word offsets from fp enum call_stub_layout { - sp_after_call_off = -33, + sp_after_call_off = -34, + frm_off = sp_after_call_off, f27_off = -33, f26_off = -32, f25_off = -31, @@ -214,6 +216,7 @@ class StubGenerator: public StubCodeGenerator { const Address sp_after_call (fp, sp_after_call_off * wordSize); + const Address frm_save (fp, frm_off * wordSize); const Address call_wrapper (fp, call_wrapper_off * wordSize); const Address result (fp, result_off * wordSize); const Address result_type (fp, result_type_off * wordSize); @@ -296,6 +299,16 @@ class StubGenerator: public StubCodeGenerator { __ fsd(f26, f26_save); __ fsd(f27, f27_save); + __ frrm(t0); + __ sd(t0, frm_save); + // Set frm to the state we need. We do want Round to Nearest. We + // don't want non-IEEE rounding modes. + Label skip_fsrmi; + guarantee(__ RoundingMode::rne == 0, "must be"); + __ beqz(t0, skip_fsrmi); + __ fsrmi(__ RoundingMode::rne); + __ bind(skip_fsrmi); + // install Java thread in global register now we have saved // whatever value it held __ mv(xthread, c_rarg7); @@ -415,6 +428,14 @@ class StubGenerator: public StubCodeGenerator { __ ld(x9, x9_save); + // restore frm + Label skip_fsrm; + __ ld(t0, frm_save); + __ frrm(t1); + __ beq(t0, t1, skip_fsrm); + __ fsrm(t0); + __ bind(skip_fsrm); + __ ld(c_rarg0, call_wrapper); __ ld(c_rarg1, result); __ ld(c_rarg2, result_type);