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8153837: AArch64: Handle special cases for MaxINode & MinINode

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Reviewed-by: fyang, aph
This commit is contained in:
Dmitry Chuyko 2023-01-18 14:56:53 +00:00
parent 754f6e6116
commit b3684f4bac
3 changed files with 498 additions and 39 deletions
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339
src/hotspot/cpu/aarch64/aarch64.ad
View File

@ -11164,7 +11164,6 @@ instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
// BEGIN This section of the file is automatically generated. Do not edit --------------
// This section is generated from aarch64_ad.m4
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct regL_not_reg(iRegLNoSp dst,
@ -12980,6 +12979,7 @@ instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
// Rotations
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct extrOrL(iRegLNoSp dst, iRegL src1, iRegL src2, immI lshift, immI rshift, rFlagsReg cr)
@ -13051,7 +13051,6 @@ instruct extrAddI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2, immI lshift,
ins_pipe(ialu_reg_reg_extr);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct rorI_imm(iRegINoSp dst, iRegI src, immI shift)
@ -13765,6 +13764,298 @@ instruct SubExtI_uxth_and_shift(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2,
ins_pipe(ialu_reg_reg_shift);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE src2, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 lt\t" %}
ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
$src2$$Register,
Assembler::LT);
%}
ins_pipe(icond_reg_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE src2, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 gt\t" %}
ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
$src2$$Register,
Assembler::GT);
%}
ins_pipe(icond_reg_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm0_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, zr lt\t" %}
ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
zr,
Assembler::LT);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm0_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, zr gt\t" %}
ins_encode %{
__ cselw($dst$$Register,
$src1$$Register,
zr,
Assembler::GT);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm1_le(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csincw $dst, $src1, zr le\t" %}
ins_encode %{
__ csincw($dst$$Register,
$src1$$Register,
zr,
Assembler::LE);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_imm1_gt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csincw $dst, $src1, zr gt\t" %}
ins_encode %{
__ csincw($dst$$Register,
$src1$$Register,
zr,
Assembler::GT);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_immM1_lt(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csinvw $dst, $src1, zr lt\t" %}
ins_encode %{
__ csinvw($dst$$Register,
$src1$$Register,
zr,
Assembler::LT);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmovI_reg_immM1_ge(iRegINoSp dst, iRegI src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "csinvw $dst, $src1, zr ge\t" %}
ins_encode %{
__ csinvw($dst$$Register,
$src1$$Register,
zr,
Assembler::GE);
%}
ins_pipe(icond_reg);
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_lt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_lt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_le(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_le(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
%{
match(Set dst (MinI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_lt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct minI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
%{
match(Set dst (MinI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_lt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_imm0(iRegINoSp dst, iRegIorL2I src, immI0 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_gt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_imm0_reg(iRegINoSp dst, immI0 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm0_gt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_imm1(iRegINoSp dst, iRegIorL2I src, immI_1 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_gt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_imm1_reg(iRegINoSp dst, immI_1 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_imm1_gt(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_reg_immM1(iRegINoSp dst, iRegIorL2I src, immI_M1 imm)
%{
match(Set dst (MaxI src imm));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_ge(dst, src, cr);
%}
%}
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct maxI_immM1_reg(iRegINoSp dst, immI_M1 imm, iRegIorL2I src)
%{
match(Set dst (MaxI imm src));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_imm0(cr, src);
cmovI_reg_immM1_ge(dst, src, cr);
%}
%}
// END This section of the file is automatically generated. Do not edit --------------
@ -15775,24 +16066,21 @@ instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg
// ============================================================================
// Max and Min
instruct cmovI_reg_reg_lt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect( DEF dst, USE src1, USE src2, USE cr );
// Like compI_reg_reg or compI_reg_immI0 but without match rule and second zero parameter.
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 lt\t" %}
instruct compI_reg_imm0(rFlagsReg cr, iRegI src)
%{
effect(DEF cr, USE src);
ins_cost(INSN_COST);
format %{ "cmpw $src, 0" %}
ins_encode %{
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::LT);
__ cmpw($src$$Register, 0);
%}
ins_pipe(icond_reg_reg);
ins_pipe(icmp_reg_imm);
%}
instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
instruct minI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
%{
match(Set dst (MinI src1 src2));
ins_cost(INSN_COST * 3);
@ -15802,31 +16090,13 @@ instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
compI_reg_reg(cr, src1, src2);
cmovI_reg_reg_lt(dst, src1, src2, cr);
%}
%}
// FROM HERE
instruct cmovI_reg_reg_gt(iRegINoSp dst, iRegI src1, iRegI src2, rFlagsReg cr)
%{
effect( DEF dst, USE src1, USE src2, USE cr );
ins_cost(INSN_COST * 2);
format %{ "cselw $dst, $src1, $src2 gt\t" %}
ins_encode %{
__ cselw(as_Register($dst$$reg),
as_Register($src1$$reg),
as_Register($src2$$reg),
Assembler::GT);
%}
ins_pipe(icond_reg_reg);
%}
instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
instruct maxI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2)
%{
match(Set dst (MaxI src1 src2));
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
compI_reg_reg(cr, src1, src2);
@ -15834,6 +16104,7 @@ instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
%}
%}
// ============================================================================
// Branch Instructions

86
src/hotspot/cpu/aarch64/aarch64_ad.m4
View File

@ -27,8 +27,10 @@ dnl 2. shift patterns
dnl
// BEGIN This section of the file is automatically generated. Do not edit --------------
// This section is generated from aarch64_ad.m4
dnl
define(`ORL2I', `ifelse($1,I,orL2I)')
define(`upcase', `translit(`$*', `a-z', `A-Z')')dnl
define(`downcase', `translit(`$*', `A-Z', `a-z')')dnl
define(`ORL2I', `ifelse($1,I,orL2I)')dnl
dnl
define(`BASE_SHIFT_INSN',
`// This pattern is automatically generated from aarch64_ad.m4
@ -189,7 +191,7 @@ ALL_SHIFT_KINDS_WITHOUT_ROR(Add, add)
ALL_SHIFT_KINDS_WITHOUT_ROR(Sub, sub)
dnl
dnl EXTEND mode, rshift_op, src, lshift_count, rshift_count
define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)') dnl
define(`EXTEND', `($2$1 (LShift$1 $3 $4) $5)')dnl
define(`BFM_INSN',`// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
@ -212,7 +214,7 @@ instruct $4$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift_count, immI rsh
ins_pipe(ialu_reg_shift);
%}
')
')dnl
BFM_INSN(L, 63, RShift, sbfm)
BFM_INSN(I, 31, RShift, sbfmw)
BFM_INSN(L, 63, URShift, ubfm)
@ -336,7 +338,7 @@ instruct ubfizIConvI2LAndI(iRegLNoSp dst, iRegI src, immI_bitmask msk)
%}
// Rotations dnl
// Rotations
define(`EXTRACT_INSN',`
// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
@ -539,4 +541,78 @@ dnl
ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
dnl
define(`CMOV_INSN', `// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmov$1_reg_reg_$3(iReg$1NoSp dst, iReg$1 src1, iReg$1 src2, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE src2, USE cr);
ins_cost(INSN_COST * 2);
format %{ "$2 $dst, $src1, $src2 $3\t" %}
ins_encode %{
__ $2($dst$$Register,
$src1$$Register,
$src2$$Register,
Assembler::upcase($3));
%}
ins_pipe(icond_reg_reg);
%}
')dnl
CMOV_INSN(I, cselw, lt)
CMOV_INSN(I, cselw, gt)
dnl
define(`CMOV_DRAW_INSN', `// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
instruct cmov$1_reg_imm$2_$4(iReg$1NoSp dst, iReg$1 src1, rFlagsReg cr)
%{
effect(DEF dst, USE src1, USE cr);
ins_cost(INSN_COST * 2);
format %{ "$3 $dst, $src1, zr $4\t" %}
ins_encode %{
__ $3($dst$$Register,
$src1$$Register,
zr,
Assembler::upcase($4));
%}
ins_pipe(icond_reg);
%}
')dnl
CMOV_DRAW_INSN(I, 0, cselw, lt)
CMOV_DRAW_INSN(I, 0, cselw, gt)
CMOV_DRAW_INSN(I, 1, csincw, le)
CMOV_DRAW_INSN(I, 1, csincw, gt)
CMOV_DRAW_INSN(I, M1, csinvw, lt)
CMOV_DRAW_INSN(I, M1, csinvw, ge)
dnl
define(`MINMAX_DRAW_INSN', `// This pattern is automatically generated from aarch64_ad.m4
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
ifelse($6,,
instruct downcase($1)$2_reg_imm$4(iReg$2NoSp dst, iReg$2`'ORL2I($2) src, imm$2$3$4 imm),
instruct downcase($1)$2_imm$4_reg(iReg$2NoSp dst, imm$2$3$4 imm, iReg$2`'ORL2I($2) src))
%{
ifelse($6,,
match(Set dst ($1$2 src imm));,
match(Set dst ($1$2 imm src));)
ins_cost(INSN_COST * 3);
expand %{
rFlagsReg cr;
comp$2_reg_imm0(cr, src);
cmov$2_reg_imm$4_$5(dst, src, cr);
%}
%}
')dnl
MINMAX_DRAW_INSN(Min, I, , 0, lt)
MINMAX_DRAW_INSN(Min, I, , 0, lt, rev)
MINMAX_DRAW_INSN(Min, I, _, 1, le)
MINMAX_DRAW_INSN(Min, I, _, 1, le, rev)
MINMAX_DRAW_INSN(Min, I, _, M1, lt)
MINMAX_DRAW_INSN(Min, I, _, M1, lt, rev)
dnl
MINMAX_DRAW_INSN(Max, I, , 0, gt)
MINMAX_DRAW_INSN(Max, I, , 0, gt, rev)
MINMAX_DRAW_INSN(Max, I, _, 1, gt)
MINMAX_DRAW_INSN(Max, I, _, 1, gt, rev)
MINMAX_DRAW_INSN(Max, I, _, M1, ge)
MINMAX_DRAW_INSN(Max, I, _, M1, ge, rev)

112
test/hotspot/jtreg/compiler/intrinsics/math/TestMinMaxIntrinsics.java Normal file
View File

@ -0,0 +1,112 @@
/*
* Copyright (c) 2022, BELLSOFT. All rights reserved.
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*/
/**
* @test
* @bug 8153837
* @summary Test integer min and max intrinsics
* @requires vm.flavor == "server" & (vm.opt.TieredStopAtLevel == null | vm.opt.TieredStopAtLevel == 4)
* @library /test/lib /
* @modules java.base/jdk.internal.misc
*
* @build jdk.test.whitebox.WhiteBox
* @run driver jdk.test.lib.helpers.ClassFileInstaller jdk.test.whitebox.WhiteBox
*
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions -XX:+WhiteBoxAPI
* -server -XX:-BackgroundCompilation -XX:-UseOnStackReplacement
* compiler.intrinsics.math.TestMinMaxIntrinsics
*/
package compiler.intrinsics.math;
import java.lang.reflect.Method;
import java.util.function.IntUnaryOperator;
import java.util.function.IntBinaryOperator;
import jdk.test.whitebox.WhiteBox;
import static jdk.test.lib.Asserts.assertEQ;
import static jdk.test.lib.Asserts.assertTrue;
import static compiler.whitebox.CompilerWhiteBoxTest.COMP_LEVEL_FULL_OPTIMIZATION;
public class TestMinMaxIntrinsics {
static WhiteBox wb = WhiteBox.getWhiteBox();
static int[] intCases = { Integer.MIN_VALUE, -2, -1, 0, 1, 2, Integer.MAX_VALUE };
public static long im3l = Integer.MIN_VALUE * 3L;
static void test(IntUnaryOperator std, IntUnaryOperator alt) throws ReflectiveOperationException {
for (int a : intCases) {
assertEQ(std.applyAsInt(a), alt.applyAsInt(a), String.format("Failed on %d", a));
}
var method = alt.getClass().getDeclaredMethod("applyAsInt", int.class);
wb.enqueueMethodForCompilation(method, COMP_LEVEL_FULL_OPTIMIZATION);
assertTrue(wb.isMethodCompiled(method));
for (int a : intCases) {
assertEQ(std.applyAsInt(a), alt.applyAsInt(a), String.format("Failed on %d", a));
}
}
static void test(IntBinaryOperator std, IntBinaryOperator alt) throws ReflectiveOperationException {
for (int a : intCases) {
for (int b : intCases) {
assertEQ(std.applyAsInt(a, b), alt.applyAsInt(a, b), String.format("Failed on %d, %d", a, b));
}
}
var method = alt.getClass().getDeclaredMethod("applyAsInt", int.class, int.class);
wb.enqueueMethodForCompilation(method, COMP_LEVEL_FULL_OPTIMIZATION);
assertTrue(wb.isMethodCompiled(method));
for (int a : intCases) {
for (int b : intCases) {
assertEQ(std.applyAsInt(a, b), alt.applyAsInt(a, b), String.format("Failed on %d, %d", a, b));
}
}
}
static int maxL2I(long a, int b) {
return Math.max((int) a, b);
}
static void testL2I() throws NoSuchMethodException {
assertEQ(0, maxL2I(im3l, 0));
var method = TestMinMaxIntrinsics.class.getDeclaredMethod("maxL2I", long.class, int.class);
wb.enqueueMethodForCompilation(method, COMP_LEVEL_FULL_OPTIMIZATION);
assertTrue(wb.isMethodCompiled(method));
assertEQ(0, maxL2I(im3l, 0));
}
public static void main(String[] args) throws Exception {
test(a -> (a <= 0) ? a : 0, a -> Math.min(a, 0));
test(a -> (a <= 1) ? a : 1, a -> Math.min(a, 1));
test(a -> (a <= -1) ? a : -1, a -> Math.min(a, -1));
test(a -> (0 >= a) ? 0 : a, a -> Math.max(0, a));
test(a -> (1 >= a) ? 1 : a, a -> Math.max(1, a));
test(a -> (-1 >= a) ? -1 : a, a -> Math.max(-1, a));
test((a, b) -> (a <= b) ? a : b, (a, b) -> Math.min(a, b));
test((a, b) -> (a >= b) ? a : b, (a, b) -> Math.max(a, b));
testL2I();
}
}