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Implement bitwise_blend in IGVN
The latest changes: 1. Defined a new IR `VectorBitwiseBlendNode` 2. Do the optimization in IGVN: // XorV(a, AndV(sel, XorV(a, b))) => VectorBitwiseBlend(a, b, sel) // XorV(a, AndV(sel, XorV(a, b)), mask) => // VectorBlend(a, VectorBitwiseBlend(a, b, sel), mask) 3. Adjust the ad file match rules to match `VectorBitwiseBlendNode`. 4. Adjust the JTReg tests to check `VectorBitwiseBlendNode`.
This commit is contained in:
erfang
parent
a4e3e393f5
commit
b3fe4a975f
@ -317,6 +317,13 @@ source %{
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return false; // NEON only, since SLI/USHR are not available in SVE
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}
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break;
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case Op_VectorBitwiseBlend:
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// Use NEON BSL when UseSVE < 2; SVE1 has no BSL so larger vectors are
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// not supported on UseSVE == 1 machines.
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if (UseSVE < 2 && length_in_bytes > 16) {
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return false;
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}
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break;
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default:
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break;
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}
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@ -7053,76 +7060,25 @@ instruct vblend_sve(vReg dst, vReg src1, vReg src2, pReg pg) %{
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// ------------------------------ Vector bitwise blend -------------------------
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instruct vbitwise_blend_neon_sve1(vReg dst_src1, vReg src2, vReg src3) %{
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instruct vbitwise_blend_neon_sve1(vReg src1, vReg src2, vReg dst_src3) %{
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predicate(UseSVE < 2 &&
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VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)));
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match(Set dst_src1 (XorV src3 (AndV dst_src1 (XorV src2 src3))));
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// Second form: inner XorV may have operands (src3, src2) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV src3 (AndV dst_src1 (XorV src3 src2))));
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format %{ "vbitwise_blend_neon_sve1 $dst_src1, $src2, $src3" %}
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match(Set dst_src3 (VectorBitwiseBlend (Binary src1 src2) dst_src3));
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format %{ "vbitwise_blend_neon_sve1 $src1, $src2, $dst_src3" %}
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ins_encode %{
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uint length_in_bytes = Matcher::vector_length_in_bytes(this);
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Assembler::SIMD_Arrangement T = length_in_bytes == 16 ? __ T16B : __ T8B;
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__ bsl($dst_src1$$FloatRegister, T, $src2$$FloatRegister, $src3$$FloatRegister);
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__ bsl($dst_src3$$FloatRegister, T, $src2$$FloatRegister, $src1$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_sve2(vReg dst_src1, vReg src2, vReg src3) %{
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instruct vbitwise_blend_sve2(vReg src1, vReg dst_src2, vReg src3) %{
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predicate(UseSVE == 2);
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match(Set dst_src1 (XorV src2 (AndV src3 (XorV dst_src1 src2))));
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// Second form: inner XorV may have operands (src2, dst_src1) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV src2 (AndV src3 (XorV src2 dst_src1))));
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format %{ "vbitwise_blend_sve2 $dst_src1, $src2, $src3" %}
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match(Set dst_src2 (VectorBitwiseBlend (Binary src1 dst_src2) src3));
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format %{ "vbitwise_blend_sve2 $src1, $dst_src2, $src3" %}
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ins_encode %{
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__ sve_bsl($dst_src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_masked_sve1(vReg dst_src1, vReg src2, vReg src3, pReg pg) %{
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predicate(UseSVE == 1 &&
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Matcher::vector_length_in_bytes(n) <= 16);
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match(Set dst_src1 (XorV (Binary src3 (AndV dst_src1 (XorV src2 src3))) pg));
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// Second form: inner XorV may have operands (src3, src2) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV (Binary src3 (AndV dst_src1 (XorV src3 src2))) pg));
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format %{ "vbitwise_blend_masked_sve1 $dst_src1, $pg, $src2, $src3" %}
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ins_encode %{
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uint length_in_bytes = Matcher::vector_length_in_bytes(this);
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Assembler::SIMD_Arrangement T = length_in_bytes == 16 ? __ T16B : __ T8B;
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ bsl($dst_src1$$FloatRegister, T, $src2$$FloatRegister, $src3$$FloatRegister);
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// sve_sel reads src3 after bsl overwrites dst_src1.
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assert($dst_src1$$FloatRegister != $src3$$FloatRegister,
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"dst_src1 and src3 must not alias");
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__ sve_sel($dst_src1$$FloatRegister, __ elemType_to_regVariant(bt),
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$pg$$PRegister, $dst_src1$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_masked_sve2(vReg dst_src1, vReg src2, vReg src3, pReg pg) %{
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predicate(UseSVE == 2);
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match(Set dst_src1 (XorV (Binary src2 (AndV src3 (XorV dst_src1 src2))) pg));
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// Second form: inner XorV may have operands (src2, dst_src1) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV (Binary src2 (AndV src3 (XorV src2 dst_src1))) pg));
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format %{ "vbitwise_blend_masked_sve2 $dst_src1, $pg, $src2, $src3" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ sve_bsl($dst_src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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// sve_sel reads src2 after sve_bsl overwrites dst_src1.
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assert($dst_src1$$FloatRegister != $src2$$FloatRegister,
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"dst_src1 and src2 must not alias");
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__ sve_sel($dst_src1$$FloatRegister, __ elemType_to_regVariant(bt),
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$pg$$PRegister, $dst_src1$$FloatRegister, $src2$$FloatRegister);
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__ sve_bsl($dst_src2$$FloatRegister, $src1$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -307,6 +307,13 @@ source %{
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return false; // NEON only, since SLI/USHR are not available in SVE
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}
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break;
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case Op_VectorBitwiseBlend:
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// Use NEON BSL when UseSVE < 2; SVE1 has no BSL so larger vectors are
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// not supported on UseSVE == 1 machines.
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if (UseSVE < 2 && length_in_bytes > 16) {
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return false;
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}
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break;
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default:
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break;
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}
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@ -4756,76 +4763,25 @@ instruct vblend_sve(vReg dst, vReg src1, vReg src2, pReg pg) %{
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// ------------------------------ Vector bitwise blend -------------------------
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instruct vbitwise_blend_neon_sve1(vReg dst_src1, vReg src2, vReg src3) %{
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instruct vbitwise_blend_neon_sve1(vReg src1, vReg src2, vReg dst_src3) %{
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predicate(UseSVE < 2 &&
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VM_Version::use_neon_for_vector(Matcher::vector_length_in_bytes(n)));
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match(Set dst_src1 (XorV src3 (AndV dst_src1 (XorV src2 src3))));
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// Second form: inner XorV may have operands (src3, src2) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV src3 (AndV dst_src1 (XorV src3 src2))));
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format %{ "vbitwise_blend_neon_sve1 $dst_src1, $src2, $src3" %}
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match(Set dst_src3 (VectorBitwiseBlend (Binary src1 src2) dst_src3));
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format %{ "vbitwise_blend_neon_sve1 $src1, $src2, $dst_src3" %}
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ins_encode %{
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uint length_in_bytes = Matcher::vector_length_in_bytes(this);
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Assembler::SIMD_Arrangement T = length_in_bytes == 16 ? __ T16B : __ T8B;
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__ bsl($dst_src1$$FloatRegister, T, $src2$$FloatRegister, $src3$$FloatRegister);
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__ bsl($dst_src3$$FloatRegister, T, $src2$$FloatRegister, $src1$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_sve2(vReg dst_src1, vReg src2, vReg src3) %{
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instruct vbitwise_blend_sve2(vReg src1, vReg dst_src2, vReg src3) %{
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predicate(UseSVE == 2);
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match(Set dst_src1 (XorV src2 (AndV src3 (XorV dst_src1 src2))));
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// Second form: inner XorV may have operands (src2, dst_src1) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV src2 (AndV src3 (XorV src2 dst_src1))));
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format %{ "vbitwise_blend_sve2 $dst_src1, $src2, $src3" %}
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match(Set dst_src2 (VectorBitwiseBlend (Binary src1 dst_src2) src3));
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format %{ "vbitwise_blend_sve2 $src1, $dst_src2, $src3" %}
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ins_encode %{
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__ sve_bsl($dst_src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_masked_sve1(vReg dst_src1, vReg src2, vReg src3, pReg pg) %{
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predicate(UseSVE == 1 &&
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Matcher::vector_length_in_bytes(n) <= 16);
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match(Set dst_src1 (XorV (Binary src3 (AndV dst_src1 (XorV src2 src3))) pg));
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// Second form: inner XorV may have operands (src3, src2) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV (Binary src3 (AndV dst_src1 (XorV src3 src2))) pg));
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format %{ "vbitwise_blend_masked_sve1 $dst_src1, $pg, $src2, $src3" %}
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ins_encode %{
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uint length_in_bytes = Matcher::vector_length_in_bytes(this);
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Assembler::SIMD_Arrangement T = length_in_bytes == 16 ? __ T16B : __ T8B;
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ bsl($dst_src1$$FloatRegister, T, $src2$$FloatRegister, $src3$$FloatRegister);
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// sve_sel reads src3 after bsl overwrites dst_src1.
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assert($dst_src1$$FloatRegister != $src3$$FloatRegister,
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"dst_src1 and src3 must not alias");
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__ sve_sel($dst_src1$$FloatRegister, __ elemType_to_regVariant(bt),
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$pg$$PRegister, $dst_src1$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vbitwise_blend_masked_sve2(vReg dst_src1, vReg src2, vReg src3, pReg pg) %{
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predicate(UseSVE == 2);
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match(Set dst_src1 (XorV (Binary src2 (AndV src3 (XorV dst_src1 src2))) pg));
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// Second form: inner XorV may have operands (src2, dst_src1) after Ideal/GVN.
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// adlc only auto-swaps commutative ops when at least one operand is a subtree,
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// not when both sides are leaves, so both shapes need explicit match rules.
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match(Set dst_src1 (XorV (Binary src2 (AndV src3 (XorV src2 dst_src1))) pg));
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format %{ "vbitwise_blend_masked_sve2 $dst_src1, $pg, $src2, $src3" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ sve_bsl($dst_src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
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// sve_sel reads src2 after sve_bsl overwrites dst_src1.
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assert($dst_src1$$FloatRegister != $src2$$FloatRegister,
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"dst_src1 and src2 must not alias");
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__ sve_sel($dst_src1$$FloatRegister, __ elemType_to_regVariant(bt),
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$pg$$PRegister, $dst_src1$$FloatRegister, $src2$$FloatRegister);
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__ sve_bsl($dst_src2$$FloatRegister, $src1$$FloatRegister, $src3$$FloatRegister);
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%}
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ins_pipe(pipe_slow);
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%}
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@ -512,6 +512,7 @@ macro(VectorMaskWrapper)
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macro(VectorMaskCmp)
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macro(VectorMaskCast)
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macro(VectorTest)
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macro(VectorBitwiseBlend)
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macro(VectorBlend)
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macro(VectorRearrange)
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macro(VectorLoadMask)
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@ -2385,7 +2385,8 @@ void Matcher::find_shared_post_visit(Node* n, uint opcode) {
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break;
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}
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case Op_VectorBlend:
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case Op_VectorInsert: {
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case Op_VectorInsert:
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case Op_VectorBitwiseBlend: {
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Node* pair = new BinaryNode(n->in(1), n->in(2));
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n->set_req(1, pair);
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n->set_req(2, n->in(3));
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@ -874,6 +874,7 @@ VectorNode* VectorNode::make(int vopc, Node* n1, Node* n2, Node* n3, const TypeV
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case Op_SignumVD: return new SignumVDNode(n1, n2, n3, vt);
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case Op_SignumVF: return new SignumVFNode(n1, n2, n3, vt);
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case Op_VectorBlend: return new VectorBlendNode(n1, n2, n3);
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case Op_VectorBitwiseBlend: return new VectorBitwiseBlendNode(n1, n2, n3, vt);
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default:
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fatal("Missed vector creation for '%s'", NodeClassNames[vopc]);
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return nullptr;
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@ -2768,6 +2769,73 @@ Node* XorVNode::Ideal_XorV_VectorMaskCmp(PhaseGVN* phase, bool can_reshape) {
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return res;
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}
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// XorV(a, AndV(sel, XorV(a, b))) => VectorBitwiseBlend(a, b, sel)
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// XorV(a, AndV(sel, XorV(a, b)), mask) =>
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// VectorBlend(a, VectorBitwiseBlend(a, b, sel), mask)
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Node* XorVNode::Ideal_XorV_to_VectorBitwiseBlend(PhaseGVN* phase, bool can_reshape) {
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const TypeVect* vt = vect_type();
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BasicType bt = vt->element_basic_type();
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uint vlen = vt->length();
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if (!Matcher::match_rule_supported_vector(Op_VectorBitwiseBlend, vlen, bt)) {
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return nullptr;
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}
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bool is_masked = is_predicated_vector();
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if (is_masked &&
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!Matcher::match_rule_supported_vector(Op_VectorBlend, vlen, bt)) {
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return nullptr;
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}
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// For the predicated case in(1) is fixed as the merge source. Otherwise the
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// outer XorV is commutative.
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Node* a = nullptr;
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Node* andv = nullptr;
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if (is_masked) {
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a = in(1);
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andv = in(2);
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} else if (in(2)->Opcode() == Op_AndV) {
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andv = in(2);
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a = in(1);
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} else {
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andv = in(1);
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a = in(2);
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}
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if (andv->Opcode() != Op_AndV || andv->is_predicated_vector()) {
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return nullptr;
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}
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Node* sel = nullptr;
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Node* inner_xor = nullptr;
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if (andv->in(2)->Opcode() == Op_XorV) {
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inner_xor = andv->in(2);
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sel = andv->in(1);
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} else if (andv->in(1)->Opcode() == Op_XorV) {
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inner_xor = andv->in(1);
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sel = andv->in(2);
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} else {
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return nullptr;
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}
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if (inner_xor->is_predicated_vector()) {
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return nullptr;
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}
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Node* b = nullptr;
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if (inner_xor->in(1) == a) {
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b = inner_xor->in(2);
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} else if (inner_xor->in(2) == a) {
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b = inner_xor->in(1);
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} else {
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return nullptr;
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}
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Node* blend = new VectorBitwiseBlendNode(a, b, sel, vt);
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if (!is_masked) {
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return blend;
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}
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blend = phase->transform(blend);
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return new VectorBlendNode(a, blend, in(3));
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}
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Node* XorVNode::Ideal(PhaseGVN* phase, bool can_reshape) {
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// (XorV src src) => (Replicate zero)
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// (XorVMask src src) => (MaskAll zero)
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@ -2786,6 +2854,11 @@ Node* XorVNode::Ideal(PhaseGVN* phase, bool can_reshape) {
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if (res != nullptr) {
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return res;
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}
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res = Ideal_XorV_to_VectorBitwiseBlend(phase, can_reshape);
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if (res != nullptr) {
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return res;
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}
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return VectorNode::Ideal(phase, can_reshape);
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}
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@ -1075,6 +1075,7 @@ class XorVNode : public VectorNode {
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virtual int Opcode() const;
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virtual Node* Ideal(PhaseGVN* phase, bool can_reshape);
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Node* Ideal_XorV_VectorMaskCmp(PhaseGVN* phase, bool can_reshape);
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Node* Ideal_XorV_to_VectorBitwiseBlend(PhaseGVN* phase, bool can_reshape);
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};
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// Vector xor byte, short, int, long as a reduction
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@ -1802,6 +1803,14 @@ class VectorBlendNode : public VectorNode {
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Node* vec_mask() const { return in(3); }
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};
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// Vector bitwise blend (bit-select): (sel & vec_true) | (~sel & vec_false).
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class VectorBitwiseBlendNode : public VectorNode {
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public:
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VectorBitwiseBlendNode(Node* vec_false, Node* vec_true, Node* sel, const TypeVect* vt)
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: VectorNode(vec_false, vec_true, sel, vt) {}
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virtual int Opcode() const;
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};
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// Rearrange lane elements from a source vector under the control of a shuffle
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// (indexes) vector. Each lane in the shuffle vector specifies which lane from
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// the source vector to select for the corresponding output lane. All indexes
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@ -2392,26 +2392,6 @@ public class IRNode {
|
||||
machOnlyNameRegex(VAND_NOT_L_MASKED, "vand_notL_masked");
|
||||
}
|
||||
|
||||
public static final String VBITWISE_BLEND_NEON_SVE1 = PREFIX + "VBITWISE_BLEND_NEON_SVE1" + POSTFIX;
|
||||
static {
|
||||
machOnlyNameRegex(VBITWISE_BLEND_NEON_SVE1, "vbitwise_blend_neon_sve1");
|
||||
}
|
||||
|
||||
public static final String VBITWISE_BLEND_SVE2 = PREFIX + "VBITWISE_BLEND_SVE2" + POSTFIX;
|
||||
static {
|
||||
machOnlyNameRegex(VBITWISE_BLEND_SVE2, "vbitwise_blend_sve2");
|
||||
}
|
||||
|
||||
public static final String VBITWISE_BLEND_MASKED_SVE1 = PREFIX + "VBITWISE_BLEND_MASKED_SVE1" + POSTFIX;
|
||||
static {
|
||||
machOnlyNameRegex(VBITWISE_BLEND_MASKED_SVE1, "vbitwise_blend_masked_sve1");
|
||||
}
|
||||
|
||||
public static final String VBITWISE_BLEND_MASKED_SVE2 = PREFIX + "VBITWISE_BLEND_MASKED_SVE2" + POSTFIX;
|
||||
static {
|
||||
machOnlyNameRegex(VBITWISE_BLEND_MASKED_SVE2, "vbitwise_blend_masked_sve2");
|
||||
}
|
||||
|
||||
public static final String RISCV_VAND_NOTI_VX = PREFIX + "RISCV_VAND_NOTI_VX" + POSTFIX;
|
||||
static {
|
||||
machOnlyNameRegex(RISCV_VAND_NOTI_VX, "vand_notI_vx");
|
||||
@ -2462,6 +2442,12 @@ public class IRNode {
|
||||
vectorNode(VECTOR_BLEND_D, "VectorBlend", TYPE_DOUBLE);
|
||||
}
|
||||
|
||||
public static final String VECTOR_BITWISE_BLEND = PREFIX + "VECTOR_BITWISE_BLEND" + POSTFIX;
|
||||
static {
|
||||
String regex = START + "VectorBitwiseBlend" + MID + END;
|
||||
afterBarrierExpansionToBeforeMatching(VECTOR_BITWISE_BLEND, regex);
|
||||
}
|
||||
|
||||
public static final String VECTOR_MASK_CMP_I = VECTOR_PREFIX + "VECTOR_MASK_CMP_I" + POSTFIX;
|
||||
static {
|
||||
vectorNode(VECTOR_MASK_CMP_I, "VectorMaskCmp", TYPE_INT);
|
||||
|
||||
@ -93,10 +93,10 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testUnmaskedBlendByte() {
|
||||
ByteVector va = ByteVector.fromArray(B_SPECIES, ba, 0);
|
||||
@ -106,10 +106,10 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testUnmaskedBlendShort() {
|
||||
ShortVector va = ShortVector.fromArray(S_SPECIES, sa, 0);
|
||||
@ -119,10 +119,10 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testUnmaskedBlendInt() {
|
||||
IntVector va = IntVector.fromArray(I_SPECIES, ia, 0);
|
||||
@ -132,10 +132,10 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testUnmaskedBlendLong() {
|
||||
LongVector va = LongVector.fromArray(L_SPECIES, la, 0);
|
||||
@ -145,13 +145,12 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve", "false" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_B, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "sve", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_B, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testMaskedBlendByte() {
|
||||
VectorMask<Byte> mask = VectorMask.fromArray(B_SPECIES, mask_arr, 0);
|
||||
@ -162,13 +161,12 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve", "false" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_S, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "sve", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_S, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testMaskedBlendShort() {
|
||||
VectorMask<Short> mask = VectorMask.fromArray(S_SPECIES, mask_arr, 0);
|
||||
@ -179,13 +177,12 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve", "false" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_I, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "sve", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_I, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testMaskedBlendInt() {
|
||||
VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, mask_arr, 0);
|
||||
@ -196,13 +193,12 @@ public class VectorBitwiseBlendTest {
|
||||
}
|
||||
|
||||
@Test
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_NEON_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve", "false" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_L, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "asimd", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE1, "= 1" },
|
||||
applyIfCPUFeatureAnd = { "sve", "true", "sve2", "false" },
|
||||
applyIf = { "MaxVectorSize", "<= 16" })
|
||||
@IR(counts = { IRNode.VBITWISE_BLEND_MASKED_SVE2, "= 1" },
|
||||
@IR(counts = { IRNode.VECTOR_BLEND_L, "= 1",
|
||||
IRNode.VECTOR_BITWISE_BLEND, "= 1" },
|
||||
applyIfCPUFeature = { "sve2", "true" })
|
||||
public static void testMaskedBlendLong() {
|
||||
VectorMask<Long> mask = VectorMask.fromArray(L_SPECIES, mask_arr, 0);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user