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8352022: RISC-V: Support Zfa fminm_h/fmaxm_h for float16

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Reviewed-by: fyang, mli
This commit is contained in:
Anjian-Wen 2025-03-18 11:01:18 +00:00 committed by Fei Yang
parent 20f1bca077
commit b891bfa7e6
2 changed files with 41 additions and 0 deletions
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10
src/hotspot/cpu/riscv/assembler_riscv.hpp
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@ -1450,6 +1450,16 @@ enum operand_size { int8, int16, int32, uint32, int64 };
fp_base<D_64_dp, 0b11110>(Rd, Rs1, 0b00001, 0b000);
}
void fminm_h(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<H_16_hp, 0b00101>(Rd, Rs1, Rs2, 0b010);
}
void fmaxm_h(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<H_16_hp, 0b00101>(Rd, Rs1, Rs2, 0b011);
}
void fminm_s(FloatRegister Rd, FloatRegister Rs1, FloatRegister Rs2) {
assert_cond(UseZfa);
fp_base<S_32_sp, 0b00101>(Rd, Rs1, Rs2, 0b010);

31
src/hotspot/cpu/riscv/riscv.ad
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@ -8386,6 +8386,7 @@ instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
instruct min_max_HF_reg(fRegF dst, fRegF src1, fRegF src2)
%{
predicate(!UseZfa);
match(Set dst (MinHF src1 src2));
match(Set dst (MaxHF src1 src2));
format %{ "min_max_hf $dst, $src1, $src2" %}
@ -8404,6 +8405,36 @@ instruct min_max_HF_reg(fRegF dst, fRegF src1, fRegF src2)
ins_pipe(pipe_class_default);
%}
instruct minHF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
%{
predicate(UseZfa);
match(Set dst (MinHF src1 src2));
format %{ "min_hf $dst, $src1, $src2" %}
ins_encode %{
__ fminm_h(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct maxHF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
%{
predicate(UseZfa);
match(Set dst (MaxHF src1 src2));
format %{ "max_hf $dst, $src1, $src2" %}
ins_encode %{
__ fmaxm_h(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
%{
match(Set dst (FmaHF src3 (Binary src1 src2)));