infernap12/jdk
1
0
Fork 0
mirror of https://github.com/openjdk/jdk.git synced 2026-05-14 15:39:45 +00:00
Code Issues Packages Projects Releases Wiki Activity

8213196: [ppc] [s390]: prepare code for gcc7.3.1 warning (int-in-bool-context)

Browse Source 
Reviewed-by: mdoerr, stuefe
This commit is contained in:
Lutz Schmidt 2018-11-05 14:02:04 +01:00
parent 3798a62adb
commit b9aa498282
2 changed files with 22 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/hotspot/cpu/ppc/ppc.ad
View File

@ -7629,7 +7629,7 @@ instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7642,7 +7642,7 @@ instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7675,7 +7675,7 @@ instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7688,7 +7688,7 @@ instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7722,7 +7722,7 @@ instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7735,7 +7735,7 @@ instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7768,7 +7768,7 @@ instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7781,7 +7781,7 @@ instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
ins_pipe(pipe_class_default);
%}
@ -7794,7 +7794,7 @@ instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
Label done;
@ -7816,7 +7816,7 @@ instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
Label done;
@ -9277,7 +9277,7 @@ instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
format %{ "CMOVE $dst, neg($src1), $crx" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
Label done;
@ -9340,7 +9340,7 @@ instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
format %{ "CMOVE $dst, neg($src1), $crx" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
Label done;
@ -11114,7 +11114,7 @@ instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
format %{ "cmovI $crx, $dst, $src" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
ins_pipe(pipe_class_default);
%}
@ -11128,7 +11128,7 @@ instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
format %{ "cmovI $crx, $dst, $src" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8));
ins_encode( enc_cmove_bso_reg(dst, crx, src) );
ins_pipe(pipe_class_default);
%}
@ -11383,7 +11383,7 @@ instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
format %{ "cmovL $crx, $dst, $src" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
ins_pipe(pipe_class_default);
%}
@ -11397,7 +11397,7 @@ instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
format %{ "cmovL $crx, $dst, $src" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
size((false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8));
ins_encode( enc_cmove_bso_reg(dst, crx, src) );
ins_pipe(pipe_class_default);
%}
@ -11890,7 +11890,7 @@ instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
format %{ "cmovI $crx, $dst, -1, 0, +1" %}
// Worst case is branch + move + branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
size((false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmove);
Label done;
@ -12229,7 +12229,7 @@ instruct cmov_bns_less(flagsReg crx) %{
format %{ "cmov $crx" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
size((false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12));
ins_encode %{
// TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
Label done;

8
src/hotspot/cpu/s390/s390.ad
View File

@ -6480,7 +6480,7 @@ instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2,
match(DivModI dst1src1 src2);
effect(KILL cr);
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
size(VM_Version::has_CompareBranch() ? 24 : 26);
size((VM_Version::has_CompareBranch() ? 24 : 26));
format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
ins_encode %{
Register d1s1 = $dst1src1$$Register;
@ -6513,7 +6513,7 @@ instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp,
match(Set dst (DivI src1 src2));
effect(KILL tmp, KILL cr);
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
size(VM_Version::has_CompareBranch() ? 20 : 22);
size((VM_Version::has_CompareBranch() ? 20 : 22));
format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
ins_encode %{
Register a = $src1$$Register;
@ -6564,7 +6564,7 @@ instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flags
match(DivModL dst1src1 src2);
effect(KILL cr);
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
size(VM_Version::has_CompareBranch() ? 22 : 24);
size((VM_Version::has_CompareBranch() ? 22 : 24));
format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
ins_encode %{
Register d1s1 = $dst1src1$$Register;
@ -6594,7 +6594,7 @@ instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
match(Set dst (DivL dst src));
effect(KILL tmp, KILL cr);
ins_cost(2 * DEFAULT_COST + BRANCH_COST);
size(VM_Version::has_CompareBranch() ? 18 : 20);
size((VM_Version::has_CompareBranch() ? 18 : 20));
format %{ "DIVG_checked $dst, $src\t # long, treats special case 0x80../-1" %}
ins_encode %{
Register b = $src$$Register;